Method for adjusting at least one operating point of at least one integrated circuit of a system on a chip, and corresponding system on a chip

Abstract

A system on a chip includes at least one integrated circuit that is configured to operate at least at one operating point. A monitoring circuit acquires at least the cumulative duration of activity of the at least one integrated circuit. An evaluation circuit establish at least one instantaneous state of aging of the at least one integrated circuit based on the at least one cumulative duration of activity. An adjustment circuit operates to change the at least one operating point on the basis of the at least one state of aging of the at least one integrated circuit.

Claims

1. A method for adjusting at least one operating point of at least one integrated circuit of a system on a chip, the system on a chip comprising a first integrated circuit configured to operate at a first operating point and a second integrated circuit configured to operate at a second operating point, the second operating point being less constraining than the first operating point, the method comprising: monitoring to acquire at least one cumulative duration of activity of said at least one integrated circuit; evaluating to establish a state of aging of said at least one integrated circuit on the basis of said cumulative duration of activity; and adjusting said at least one operating point of said at least one integrated circuit on the basis of said state of aging by changing the first operating point of the first integrated circuit to match the second operating point when the state of aging of the first integrated circuit, equal to the cumulative duration of activity of the first integrated circuit, exceeds a first threshold value.

2. The method according to claim 1, wherein adjusting further comprises changing the second operating point of both the first and second integrated circuits to a third operating point, said third operating point being less constraining than the second operating point, when the states of aging of the first and second integrated circuit, which are equal to the cumulative durations of activity of the first and second integrated circuit respectively, exceed a second threshold value.

3. The method according to claim 1, wherein adjusting comprises an changing operating points by stages.

4. The method according to claim 1, wherein evaluating and adjusting step are executed on each restart of the system on a chip.

5. A method for adjusting at least one operating point of at least one integrated circuit of a system on a chip, comprising: monitoring to acquire at least one cumulative duration of activity of at least one integrated circuit by acquiring at least one physical parameter representing use of said at least one integrated circuit; evaluating to establish a state of aging of said at least one integrated circuit on the basis of said cumulative duration of activity by determining at least one instantaneous state of aging of said at least one integrated circuit on the basis of said at least one physical parameter; and adjusting said at least one operating point of said at least one integrated circuit on the basis of said state of aging by changing said at least one operating point with allowance for at least one operating margin; and calculating said at least one operating margin of said at least one integrated circuit by comparing said at least one instantaneous state of aging with a presumed state of aging.

6. The method according to claim 1, wherein monitoring to acquire at least one cumulative duration of activity of the at least one integrated circuit comprises monitoring to acquire at least one cumulative duration of activity of the at least one integrated circuit at an operating point defined as critical.

7. A method for adjusting at least one operating point of at least one integrated circuit of a system on a chip, wherein the at least one integrated circuit comprises a first integrated circuit configured to operate at a first operating point, the method comprising: monitoring to acquire at least one cumulative duration of activity of at least one integrated circuit; evaluating to establish a state of aging of said at least one integrated circuit on the basis of said cumulative duration of activity; and adjusting said at least one operating point of said at least one integrated circuit said state of aging, wherein adjusting comprises changing the first operating point of the first integrated circuit to a second operating point, said second operating point being dedicated to the first integrated circuit and less constraining than the first operating point, when the state of aging of the first integrated circuit, equal to the cumulative duration of activity of the first integrated circuit, exceeds a first threshold value.

8. The method according to claim 7, wherein the system on a chip further comprises a second integrated circuit configured to operate at a third operating point, and wherein adjusting comprises changing the third operating point of the second integrated circuit to a fourth operating point, said fourth operating point dedicated to the second integrated circuit and less constraining than the third operating point, when the state of aging of the second integrated circuit, equal to the cumulative duration of activity of the second integrated circuit, exceeds a second threshold value.

9. A method for adjusting at least one operating point of at least one integrated circuit of a system on a chip, comprising: monitoring to acquire at least one cumulative duration of activity of at least one integrated circuit, wherein monitoring further comprises acquiring a supply voltage applied to said at least one integrated circuit; evaluating to establish a state of aging of said at least one integrated circuit on the basis of said cumulative duration of activity, wherein evaluating comprises the establishing a state of aging of said at least one integrated circuit on the basis of the cumulative duration of activity and on the basis of at least one supply voltage previously applied to said at least one integrated circuit; and adjusting said at least one operating point of said at least one integrated circuit on the basis of said state of aging.

10. The method according to claim 9, wherein adjusting comprises a changing by stages of said at least one operating point of said at least one integrated circuit to at least one other operating point dedicated to said at least one integrated circuit, said at least one other operating point being less constraining than said at least one operating point.

11. The method according to claim 9, wherein monitoring to acquire at least one cumulative duration of activity of the at least one integrated circuit comprises monitoring to acquire at least one cumulative duration of activity of the at least one integrated circuit at an operating point defined as critical.

12. The method according to claim 5, wherein the acquisition performed during monitoring occurs continuously during the operation of the system on a chip.

13. The method according to claim 12, wherein evaluating and adjusting are executed periodically in real time during the operation of the system on a chip.

14. The method according to claim 12, wherein monitoring to acquire at least one cumulative duration of activity of the at least one integrated circuit comprises monitoring to acquire at least one cumulative duration of activity of the at least one integrated circuit at an operating point defined as critical.

15. A method for adjusting at least one operating point of at least one integrated circuit of a system on a chip, comprising: monitoring to acquire at least one cumulative duration of activity of at least one integrated circuit, and sending a warning signal in case of a hardware malfunction; evaluating to establish a state of aging of said at least one integrated circuit said cumulative duration of activity; and adjusting said at least one operating point of said at least one integrated circuit on the basis of said state of aging by changing the operating point of said at least one integrated circuit to a secure operating point in response to said warning signal.

16. The method according to claim 15, wherein monitoring to acquire at least one cumulative duration of activity of the at least one integrated circuit comprises monitoring to acquire at least one cumulative duration of activity of the at least one integrated circuit at an operating point defined as critical.

17. A system on a chip, comprising: at least one integrated circuit configured to operate at least at one operating point, the at least one integrated circuit comprises a first integrated circuit configured to operate at a first operating point and a second integrated circuit is configured to operate at a second operating point, said second operating point being less constraining than the first operating point; a monitoring circuit configured to acquire at least one cumulative duration of activity of said at least one integrated circuit; an evaluation circuit configured to establish at least one instantaneous state of aging of said at least one integrated circuit on the basis of said at least one cumulative duration of activity; and an adjustment circuit configured to adjust said at least one operating point on the basis of said at least one instantaneous state of aging of said at least one integrated circuit by changing the operating point of the first integrated circuit to the second operating point when the state of aging of the first integrated circuit, equal to the cumulative duration of activity of the first integrated circuit, exceeds a first threshold value.

18. The system on a chip according to claim 17, wherein the adjustment circuit is further configured to change the second operating point of the first and second integrated circuits to a third operating point, said third operating point being less constraining than the second operating point, when the states of aging of the first and second integrated circuits, which are equal to the cumulative durations of activity of the first and second integrated circuit respectively, exceed a second threshold value.

19. The system on a chip according to claim 17, wherein the adjustment circuit is configured to change said at least one operating point by stages.

20. The system on a chip according to claim 17, wherein the evaluation circuit and the adjustment circuit are configured to establish the instantaneous state of aging and to change said operating point on each restart of the system on a chip.

21. The system on a chip according to claim 17, wherein the monitoring circuit is configured to acquire the cumulative duration of activity continuously during the operation of the system on a chip.

22. The system on a chip according to claim 17, wherein said system is a component of an apparatus comprising one of a compute or a mobile telephone.

23. The system on a chip according to claim 17, wherein the monitoring circuit acquires the at least one cumulative duration of activity of the at least one integrated circuit at an operating point defined as critical.

24. A system on a chip, comprising: at least one integrated circuit configured to operate at least at one operating point, wherein the at least one integrated circuit comprises a first integrated circuit configured to operate at a first operating point; a monitoring circuit configured to acquire at least one cumulative duration of activity of said at least one integrated circuit; an evaluation circuit configured to establish at least one instantaneous state of aging of said at least one integrated circuit on the basis of said at least one cumulative duration of activity; and an adjustment circuit configured to adjust said at least one operating point on the basis of said at least one instantaneous state of aging of said at least one integrated circuit, and wherein the adjustment serves to adjust the operating point of said first integrated circuit to a second operating point, said second operating point being dedicated to the first integrated circuit and less constraining than the first operating point, when the state of aging of the first integrated circuit, equal to the cumulative duration of activity of the first integrated circuit, exceeds a first threshold value.

25. The system on a chip according to claim 24, wherein the at least one integrated circuit further comprises a second integrated circuit configured to operate at a third operating point, and wherein the adjustment circuit is configured to change the third operating point of the second integrated circuit to a fourth operating point, said fourth operating point dedicated to the second integrated circuit and less constraining than the third operating point, when the state of aging of said second integrated circuit, equal to the cumulative duration of activity of the second integrated circuit, exceeds a second threshold value.

26. A system on a chip comprising: at least one integrated circuit configured to operate at least at one operating point; a monitoring circuit configured to acquire at least one cumulative duration of activity of said at least one integrated circuit and to acquire a supply voltage applied to said at least one integrated circuit; an evaluation circuit is configured to establish at least one instantaneous state of aging of said at least one integrated circuit on the basis of said at least one cumulative duration of activity and on the basis of the supply voltages previously applied to said at least one integrated circuit; and an adjustment circuit configured to adjust said at least one operating point on the basis of said at least one instantaneous state of aging of said at least one integrated circuit.

27. The system on a chip according to claim 26, wherein the adjustment circuit is configured to change by stages said at least one operating point of said at least one integrated circuit to at least one other operating point dedicated to said at least one integrated circuit, said at least one other operating point being less constraining than said at least one operating point.

28. The system on a chip according to claim 26, wherein the monitoring circuit acquires the at least one cumulative duration of activity of the at least one integrated circuit at an operating point defined as critical.

29. A system on a chip comprising: at least one integrated circuit configured to operate at least at one operating point; a monitoring circuit configured to acquire at least one cumulative duration of activity of said at least one integrated circuit and to acquire at least one physical parameter representing use of said at least one integrated circuit; an evaluation circuit is configured to establish at least one instantaneous state of aging of said at least one integrated circuit on the basis of said at least one cumulative duration of activity and the physical parameter, and to calculate at least one operating margin of said at least one integrated circuit by comparing said at least one instantaneous state of aging with a presumed state of aging; and an adjustment circuit configured to adjust said at least one operating point on the basis of said at least one instantaneous state of aging of said at least one integrated circuit and on the basis of said at least one operating margin.

30. The system on a chip according to claim 29, wherein the evaluation circuit and the adjustment circuit are configured to calculate said at least one operating margin and to change said at least one operating point periodically in real time.

31. The system on a chip according to claim 29, wherein the monitoring circuit acquires the at least one cumulative duration of activity of the at least one integrated circuit at an operating point defined as critical.

32. A system on a chip, comprising: at least one integrated circuit configured to operate at least at one operating point; a monitoring circuit configured to acquire at least one cumulative duration of activity of said at least one integrated circuit, wherein the monitoring circuit comprises break circuits associated with said at least one integrated circuit, the break circuits comprising one of critical path replicas and in-situ sensors configured to send a warning signal to an adjustment circuit in case of hardware malfunction; an evaluation circuit configured to establish at least one instantaneous state of aging of said at least one integrated circuit on the basis of said at least one cumulative duration of activity; and wherein the adjustment circuit configured to adjust said at least one operating point on the basis of said at least one instantaneous state of aging of said at least one integrated circuit and to change the operating point of said at least one integrated circuit to a secure operating point in response to said warning signal.

33. The system on a chip according to claim 32, wherein the monitoring circuit acquires the at least one cumulative duration of activity of the at least one integrated circuit at an operating point defined as critical.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Other advantages and features of the invention will be apparent from a perusal of the detailed description of applications and embodiments which are not limiting in any way, and the appended drawings, in which:

(2) FIG. 1 shows schematically and in a simplified manner an embodiment of a system on a chip SOC;

(3) FIG. 2 shows a timing diagram of various operations described in relation to FIG. 1;

(4) FIGS. 3 and 4 show graphs of OPP versus DCA;

(5) FIG. 5 shows a graph of voltage versus time;

(6) FIG. 6 shows a system on chip with a calculation unit configured to execute certain functions, for example defined in software executed by a processor; and

(7) FIGS. 7 and 8 each show an example of a product or apparatus equipped with an embodiment of a system on a chip SOC.

DETAILED DESCRIPTION

(8) FIG. 1 shows schematically and in a simplified manner an embodiment of a system on a chip SOC comprising a processor 1 configured to execute software means 2.

(9) The system on a chip comprises, in a usual way, passive components and active components such as integrated circuits, which for the sake of simplicity are not shown.

(10) The integrated circuit, forming the processor 1 for example, is configured to operate optimally at an operating point which is natural to it.

(11) An operating point, or Operating Performance Point (OPP), also referred to as an operating point, is an entity used by those skilled in the art to denote a good compromise between the parameters applied to a component.

(12) An operating point is, for example, defined by at least one supply voltage and a clock frequency.

(13) The supply voltages are generated by a switched mode power supply stage 3 (for example, a Voltage Switched Mode Power Supply (VSMPS) and are then distributed 19 in the system on a chip SOC, and more particularly in the integrated circuits of the processor 1.

(14) The processor 1 has a monitoring circuit 4 configured to acquire the activity time of at least one integrated circuit at a given operating point, and to read 10 and update 11 a cumulative duration of activity of said at least one integrated circuit in a non-volatile memory 5.

(15) At the start of a period of activity of an integrated circuit, the monitoring circuit 4 reads the preceding value of the cumulative duration of activity of said integrated circuit in the memory 5, and measures the time elapsed during said period of activity.

(16) After the period of activity, the monitoring circuit adds the measured activity time to the preceding value of cumulative duration of activity and records the new value of cumulative duration of activity in the memory 5.

(17) The monitoring circuit 4 may, for example, be implemented in software form in the processor 1.

(18) The system on a chip SOC comprises a secure processor 6, commonly known as a Trusted Execution Environment (TEE).

(19) The secure processor 6 is a secure processor or a secure area of a processor which is not easily accessed by a user or a program external to the system on a chip SOC as such.

(20) A parameterization circuit (PMT) 7 is configured to control the various physical parameters which enable the system on a chip SOC to operate.

(21) The parameterization circuit 7 is, notably, capable of controlling the power supply stage 3, and is thus capable of modifying the operating point of an integrated circuit of the system on a chip SOC, by modifying its supply voltage.

(22) The parameterization circuit 7 is, for example, implemented as a software module incorporated into an independent microcontroller.

(23) An evaluation circuit is configured to establish a state of aging on the basis of said cumulative duration of activity.

(24) In a first embodiment, the evaluation circuit is formed by the interaction of the secure processor 6 and the parameterization circuit 7. In fact, the secure processor is used to read 12 the cumulative duration of activity and to transmit 13 the cumulative duration of activity to the parameterization circuit 7.

(25) More precisely, the secure processor 6 is used here as a reliable intermediary, making it possible, for example, to avoid external corruption of the memory 5 or of the parameterization circuit 7.

(26) The parameterization circuit 7 establishes a state of aging on the basis of said cumulative duration of activity. In this embodiment, the state of aging of an integrated circuit is directly its cumulative duration of activity at a given operating point.

(27) The state of aging is then transmitted 14 to the secure processor 6 which writes 15 the state of aging to the memory 5.

(28) In this embodiment, if the state of aging of an integrated circuit, that is to say its cumulative duration of activity at an operating point defined as critical, reaches a threshold value, then the parameterization circuit 7 controls 18 the power supply stage 3 so as to modify 19 the operating point of the integrated circuit in question.

(29) The parameterization circuit 7 and the power supply stage 3 thus form an adjustment circuit capable of adjusting the operating point of an integrated circuit with allowance for its state of aging.

(30) An operating point defined as critical has, for example, a lower voltage and/or a higher frequency than other operating points, called regular.

(31) FIG. 2 shows a timing diagram of various operations described in relation to FIG. 1. The four downward vertical arrows represent the passage of time.

(32) The reading 12 of the cumulative duration of activity and its transmission 13 to the parameterization circuit 7, followed by a calculation time 21, the transmission 14 and the writing 15 to the memory 5 of the state of aging, together with the control 18 of the power supply stage 3, are executed in a preliminary phase 20.

(33) The calculation time 21 is the time required for the calculation of the state of aging of an integrated circuit, together with, if necessary, the calculation of the optimal adjustment of an operating point, and more particularly the voltage generated by the power supply stage 3 for this operating point.

(34) The preliminary phase 20 is executed on each start-up of the system on a chip SOC.

(35) The reading 10 and updating 11 of the cumulative duration of activity of the integrated circuit in a non-volatile memory 5 are carried out continuously during the use of the system on a chip, whenever the respective integrated circuit is active 22.

(36) The adjustment of the operating points of the integrated circuits of the system on a chip SOC is carried out on each start-up of the system SOC.

(37) FIG. 3 shows an embodiment of a first variant of this application in the form of a graph on which the cumulative duration of activity DCA is shown on the horizontal axis and a scale OPP representing the operating points is shown on the vertical axis.

(38) The scale OPP may represent, for example, the supply voltage of the operating points represented by it.

(39) A first integrated circuit CI1 is configured to operate at a first critical operating point 31, then, when the cumulative duration of activity DCA of this integrated circuit CI1 at this critical operating point 31 reaches a first threshold value VS1, the adjustment circuit (references 3 and 7) sets this integrated circuit CI1 to a regular operating point 32.

(40) The regular operating point 32 is, for example, an operating point of a second integrated circuit CI2.

(41) Similarly, when the cumulative duration of activity of the second integrated circuit CI2 and the first integrated circuit CI1 at this regular operating point exceeds a second threshold value VS2, the adjustment circuit sets these circuits CI1, CI2 to a third operating point 33, which is less constraining than the preceding operating points 31, 32. The expression less constraining operating point, used here and throughout the detailed part of the description, is taken to mean that the operating point of an integrated circuit which is less constraining than another operating point is, for example, an operating point of which at least some parameters, such as the operating voltage and frequency, have values enabling the integrated circuit to operate with greater tolerance to operating hazards, such as those due to the aging of the integrated circuit, than would be the case with the values of the same parameters associated with the other operating point.

(42) The threshold values of cumulative duration of activity may be, for example, 3 years of activity for a critical operating point (VS1), or 7 years of activity for a regular operating point (VS2).

(43) Briefly, this variant can be used to switch from first critical operating points of the system on a chip to second regular operating points at specified instants, which are set at the time of the design of said system on a chip.

(44) This makes it possible, for example, to use the maximum performance of some integrated circuits of the system on a chip at the start of the life of said system and to maintain reliable operation of the same integrated circuits after they have aged.

(45) As many stages as may be necessary may be provided, each stage corresponding to a change of operating point after a threshold value of cumulative duration of activity has been exceeded.

(46) FIG. 4 shows an embodiment of another variant of this application in the form of a graph having the same construction as that shown in FIG. 3.

(47) In this variant, the second operating points may be different operating points from the regular operating points applied to other integrated circuits of the system on a chip.

(48) These second operating points may, for example, be set during the design of the system on a chip to optimize the operation of the integrated circuits, after a period of aging equal to a first threshold value of cumulative duration of activity.

(49) This corresponds to an adjustment of certain operating points performed during the life of said system on a chip according to a schedule and optimal values dedicated to this integrated circuit and specified during the design of said system on a chip.

(50) More precisely, a first integrated circuit CI10 is configured to operate at a first critical operating point 41, then, when the cumulative duration of activity DCA of this integrated circuit CI10 at this critical operating point 41 reaches a first threshold value VS10, the adjustment circuit sets this integrated circuit CI10 to a dedicated operating point 42, less constraining than the initial critical operating point 41.

(51) The dedicated operating point 42 is not necessarily an operating point of a second integrated circuit CI20.

(52) When the cumulative duration of activity DCA of the first integrated circuit CI10 at this dedicated operating point 42 reaches another threshold value VS30, the adjustment circuit sets this integrated circuit CI10 to a dedicated operating point 45, which is itself less constraining than the preceding dedicated operating point 42.

(53) Similarly, when the cumulative duration of activity of a second integrated circuit CI20 at a third operating point 43 exceeds a second threshold value VS20, the adjustment circuit sets these circuits CI20 to a fourth operating point 44, which is less constraining than the preceding operating point 43.

(54) In the preceding variants, the adjustment of an operating point is carried out on the first restart of the system on a chip, after the cumulative duration of activity of an integrated circuit has exceeded the corresponding threshold value.

(55) This adjustment and this scheduling may advantageously allow for the mission profile for which the system on a chip SOC is designed.

(56) The mission profile of a system on a chip may also be configured by a user, for example by being initialized before the first use or modified during the life of the system on a chip.

(57) According to another embodiment, the state of aging of an integrated circuit is the result of a calculation allowing for the cumulative duration of activity, the values of the supply voltage provided to this integrated circuit during its previous activity, and its previous state of aging.

(58) The data relating to the previous activities are read in the memory 5.

(59) This calculation is based on a physical and/or empirical model of the aging of each of the integrated circuits.

(60) The adjustment of operating point may advantageously allow for not only the state of aging of the integrated circuit, but also the temperature of the system, the constraints to which the system is subjected, for example those due to current draws, or the precision of the power supply stage, in the form of fixed constants corresponding to a mission profile.

(61) The mission profile may, for example, be provided during the design of the system on a chip, or may be configured by a user.

(62) Additionally, in this embodiment, the adjustment of the operating point is carried out on each start-up of the system on a chip SOC, and the value of the supply voltage of the adjusted operating point is calculated on the basis of a predetermined formula which is a function of the cumulative duration of activity and the preceding state of aging.

(63) Said calculation is executed by the parameterization circuit 7.

(64) The new applied voltage and the new state of aging are then recorded in the memory 5, by means of the secure processor 6, and will form the data relating to previous activities for a subsequent calculation of the value of a supply voltage.

(65) On the first start-up, the supply voltage is set to a default value.

(66) The supply voltage will then increase by stages during the life of the system on a chip, on the basis of the use made of said system on a chip.

(67) FIG. 5 shows an example of the variation of said supply voltage, in the form of a graph showing time t on the horizontal axis and the supply voltage V on the vertical axis. The horizontal axis is, notably, marked out by restart events RES of the system on a chip SOC.

(68) In other words, in this embodiment, a monitoring circuit, implemented in software form by the processor 1 for example, records the time spent by integrated circuits at critical operating points, and a dynamic adjustment of the operating points is carried out on the next restart of the system on a chip.

(69) Thus, on each start-up of the system on a chip, the voltage applied to an integrated circuit, preferably an integrated circuit forming a calculation unit, is calibrated on the basis of the uses made of this integrated circuit after the first operation of the system on a chip.

(70) FIG. 6 shows an embodiment described in co-pending application for patent entitled METHOD FOR ESTIMATING AN OPERATING PROFILE OF AN INTEGRATED CIRCUIT OF A SYSTEM-ON-A-CHIP, AND CORRESPONDING SYSTEM-ON-A-CHIP, U.S. patent application Ser. No. 15/468,798 filed Mar. 24, 2017, now U.S. patent Ser. No. 10/302,693 issued May 28, 2019, which claims priority to French Application for Patent No. 1657535 filed Aug. 3, 2016 (incorporated by reference).

(71) In this embodiment, the physical parameters 61 representing the use of an integrated circuit are acquired, by means of in-situ sensors for example, assigned to the integrated circuits concerned.

(72) The physical parameters may be, for example, the voltage 611, the temperature 612, the duration of activity 613 of the integrated circuit, or its operating frequency 614.

(73) An evaluation circuit 62, implemented in software form in a processor 60 for example, is configured to determine an instantaneous state of aging 63 of the integrated circuit.

(74) The instantaneous state of aging is calculated on the basis of equations 64 modeling the attrition of an integrated circuit on the basis of said measured physical parameters 61.

(75) On the other hand, a second evaluation circuit 620, again implemented in software form in a processor 60 for example, is configured to determine a presumed state of aging 68, depending solely on a cumulative duration of activity 65 and a mission profile 66.

(76) The two evaluation circuits 62 and 620 are separate in this representation, but may be formed by a single evaluation circuitry, for example one implemented in software form in the processor 60.

(77) The presumed state of aging 68 corresponds to an estimated state of aging associated with a mission profile 66 multiplied by an actual rate of use equal to the ratio between the cumulative duration of activity 65 and a total estimated life 67 for an integrated circuit in this mission profile 66.

(78) In other words, the instantaneous state of aging reflects the real aging of the integrated circuit, whereas the presumed state of aging reflects the predicted aging of the integrated circuit in a given mission profile.

(79) The difference between the instantaneous state of aging and the presumed state of aging gives a margin value 69.

(80) This margin 69 is transmitted to the secure processor 6, which updates the state of aging of the integrated circuit on the basis of the margin 69, transmitted 13 to the adjustment circuit (this circuit being formed, notably, by the control 18 of the parameterization circuit 7 in the power supply stage 3) and recorded 15 in the memory 5.

(81) The adjustment circuit of the system on a chip is configured to adjust the operating point of this integrated circuit subsequently in such a way as to optimize its operation within the limit of said operating margin.

(82) In this embodiment, the physical measurements and the evaluation of the states of aging are carried out continuously, in a period of between one microsecond and one second, together with the adjustment of an operating point.

(83) In a variant, the mission profile may be configurable by a user 100, for example in systems on chips designed to execute different missions.

(84) Otherwise, the estimated state of aging is set during the design of the system on a chip SOC so as to correspond to the most constraining mission profile, of the type used in industrial conditions. The calculated margin will be greater if the mission profile is overdesigned, but will have no visible effect on the result of the adjustment of an operating point.

(85) The various embodiments of a system on a chip SOC described above may further comprise break circuits associated with integrated circuits of the system on a chip, configured to detect a hardware malfunction, such as critical path replicas or in-situ sensor-triggers. Said break circuits form an additional part of the monitoring circuit.

(86) In case of malfunction, the break circuits send a warning signal (referred to as a flag) to the adjustment circuit. The adjustment circuit is configured so that it then adjusts the operating point of the defective integrated circuit to another operating point, called the secure operating point. The secure operating point is, for example, an operating point which is less constraining than the operating point in which the integrated circuit has suffered a malfunction.

(87) FIGS. 7 and 8 each show an example of a product or apparatus equipped with an embodiment of a system on a chip SOC as detailed above, namely a personal computer 700 and a mobile telephone 800 respectively. It will be apparent to those skilled in the art that the embodiments of a system on a chip SOC detailed above may be used in any other known product not mentioned here.

(88) Clearly, the proposed solution for the management of aging is not limited to the embodiments and applications detailed above, but covers all variants thereof; for example, the passive components or components other than integrated circuits forming the logic of a processor may benefit from such management of their aging.

(89) Additionally, the embodiments and installation described are applied to an operating point of at least one integrated circuit, but, by way of example, numerous operating points of different components of the system on a chip, or a global operating point, or only the most critical operating points, may be managed simultaneously or independently.