FREQUENCY MULTIPLIER CIRCUITRY, CORRESPONDING SYSTEM AND VEHICLE

Abstract

In an embodiment a circuit includes frequency multiplier circuitry having input nodes configured to receive an input signal and an anti-phase version thereof, the input signal having a first frequency value, wherein the frequency multiplier circuitry is configured to produce a current signal at a second frequency value that is an even multiple of the first frequency value and a transformer including a primary side and a secondary side, wherein the primary side comprises a primary inductance coupled to the frequency multiplier circuitry to receive the current signal therefrom, wherein the secondary side is configured to provide a frequency multiplied voltage signal, and wherein the frequency multiplier circuitry and the transformer are cascaded between at least one first node and a second node, the at least one first node and the second node couplable to a supply node and ground.

Claims

1. A circuit comprising: frequency multiplier circuitry having input nodes configured to receive an input signal and an anti-phase version thereof, the input signal having a first frequency value, wherein the frequency multiplier circuitry is configured to produce a current signal at a second frequency value that is an even multiple of the first frequency value; a transformer comprising a primary side and a secondary side, wherein the primary side comprises a primary inductance coupled to the frequency multiplier circuitry to receive the current signal therefrom, wherein the secondary side is configured to provide a frequency multiplied voltage signal, and wherein the frequency multiplier circuitry and the transformer are cascaded between at least one first node and a second node, the at least one first node and the second node couplable to a supply node and ground; a first shunt resonator coupled between the supply node and the at least one first node; a second shunt resonator coupled between the second node and ground; and a bypass current path coupled between the at least one first node and the second node.

2. The circuit of claim 1, wherein the transformer is arranged between the at least one first node and the frequency multiplier circuitry.

3. The circuit of claim 1, wherein the transformer is arranged between the frequency multiplier circuitry and the second node.

4. The circuit of claim 1, wherein the frequency multiplier circuitry comprises a first transistor having a first control terminal configured to receive the input signal and a second transistor having a second control terminal configured to receive the anti-phase version of the input signal, the first transistor and the second transistor having respective current paths therethrough arranged in parallel in a current line from the at least one node to the second node and a common source node.

5. The circuit of claim 4, wherein the frequency multiplier circuitry further comprises at least one third transistor having a control terminal configured to receive a biasing voltage and the bypass current path therethrough along the current line from the at least one node to the second node.

6. The circuit of claim 4, wherein the frequency multiplier circuitry further comprises a third transistor having a third control terminal configured to receive a biasing voltage and a fourth transistor having a fourth control terminal configured to receive the biasing voltage, the third transistor and the fourth transistor having respective bypass current paths therethrough arranged in parallel in the current line from the at least one node to the second node and a common node, wherein the first transistor and the third transistor have respective current paths coupled therebetween, and wherein the second transistor and the fourth transistor have respective current paths coupled therebetween.

7. The circuit of claim 1, wherein the frequency multiplier circuitry comprises a first transistor having a first control terminal configured to receive the input signal and a second transistor having a second control terminal configured to receive the anti-phase version of the input signal, wherein the first transistor has a first current path therethrough between a first node of the at least one node, wherein the second transistor has a second current path therethrough between a second node of the at least one node, wherein the first and second transistors have a common source node and respective current paths therethrough arranged in parallel, wherein the frequency multiplier circuitry further comprising a third transistor having a third control terminal configured to receive a biasing voltage and a fourth transistor having a fourth control terminal configured to receive the biasing voltage, wherein the third transistor has a third current path therethrough between the first node of the at least one node and the primary inductance of the primary side, wherein the fourth transistor has a fourth current path therethrough between the second node of the at least one node and the primary inductance of the primary side of the transformer circuit, and wherein the first transistor and the third transistor have respective current paths coupled therebetween and wherein said second transistor and the fourth transistor have respective current paths coupled therebetween.

8. The circuit of claim 1, wherein the bypass current path comprises a resonating series arrangement of an inductance and a capacitance configured to resonate at a frequency equal to the second frequency value of the frequency multiplied current signal, and/or wherein at least one of the first shunt resonator and the second shunt resonator comprises a resonant circuit network configured to provide a first impedance value at a frequency equal to the second frequency value of the frequency multiplied current signal and a second impedance value at a frequency different from second frequency value of the frequency multiplied current signal.

9. The circuit of claim 1, wherein the frequency multiplier circuitry is configured to produce the current signal having the second frequency value that is twice the first frequency value of the input signal.

10. A frequency multiplier arrangement comprising: a cascaded arrangement of a plurality of circuits, wherein each circuit of the plurality of circuits is the circuit according to claim 1, wherein at least one of the circuits in the cascaded arrangement has its input node coupled to an output node of another one of the circuits in the cascaded arrangement.

11. A system comprising: the frequency multiplier arrangement according to claim 10; and a power amplifier coupled to the circuit and configured to receive the frequency multiplied voltage signal therefrom, the power amplifier configured to: amplify the frequency multiplied voltage signal, and provide an amplified frequency multiplied signal as a result; and a transmitter antenna coupled to the power amplifier and configured to transmit the amplified frequency multiplied signal.

12. The system of claim 11, further comprising a vehicular radar system comprising: a receiver antenna configured to receive an echo signal based on the transmitted amplified frequency multiplied signal; and a mixer stage coupled to the frequency multiplier arrangement, the mixer stage configured to apply frequency mixing to the frequency multiplied voltage signal and to the echo signal thereby producing a mixed signal as a result.

13. A system comprising: the circuit according to claim 1; a power amplifier coupled to the circuit and configured to receive the frequency multiplied voltage signal therefrom, the power amplifier configured to: amplify the frequency multiplied voltage signal, and provide an amplified frequency multiplied signal as a result; and a transmitter antenna coupled to the power amplifier and configured to transmit the amplified frequency multiplied signal.

14. The system of claim 13, further comprising a frequency synthesizer coupled to the circuit and configured to provide thereto the input signal at the first frequency.

15. The system of claim 14, wherein the frequency synthesizer is configured to provide the input signal at the first frequency value such that the second frequency value of the frequency multiplied voltage signal lies in a millimeter wavelength range.

16. The system of claim 13, further comprising a vehicular radar system comprising: a receiver antenna configured to receive an echo signal based on the transmitted amplified frequency multiplied signal; and a mixer stage coupled to the circuit, the mixer stage configured to apply frequency mixing to the frequency multiplied voltage signal and to the echo signal, thereby producing a mixed signal as a result.

17. A vehicle comprising: the system according to claim 13.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0031] One or more embodiments will now be described, by way of non-limiting example only, with reference to the annexed Figures, wherein:

[0032] FIG. 1 is a diagram exemplary of a vehicle equipped with a system;

[0033] FIG. 2 is a diagram exemplary of a circuit;

[0034] FIG. 3 is a diagram exemplary of an embodiment of the circuit;

[0035] FIG. 4 is a diagram of principles underlying one or more embodiments;

[0036] FIG. 5 is a diagram exemplary of one or more embodiments of signals of the circuit of FIG. 3;

[0037] FIGS. 6-8 are diagrams exemplary of alternative embodiments of the circuit of FIG. 3; and

[0038] FIG. 9 is a diagram exemplary of a cascade arrangement.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

[0039] In the ensuing description, one or more specific details are illustrated, aimed at providing an in-depth understanding of examples of embodiments of this description. The embodiments may be obtained without one or more of the specific details, or with other methods, components, materials, etc. In other cases, known structures, materials, or operations are not illustrated or described in detail so that certain aspects of embodiments will not be obscured.

[0040] Reference to “an embodiment” or “one embodiment” in the framework of the present description is intended to indicate that a particular configuration, structure, or characteristic described in relation to the embodiment is comprised in at least one embodiment. Hence, phrases such as “in an embodiment” or “in one embodiment” that may be present in one or more points of the present description do not necessarily refer to one and the same embodiment.

[0041] Moreover, particular conformations, structures, or characteristics may be combined in any adequate way in one or more embodiments.

[0042] The drawings are in simplified form and are not to precise scale.

[0043] Throughout the figures annexed herein, like parts or elements are indicated with like references/numerals and a corresponding description will not be repeated for brevity.

[0044] The references used herein are provided merely for convenience and hence do not define the extent of protection or the scope of the embodiments.

[0045] As exemplified in FIG. 1, a vehicle V can be equipped with a radar system 10 and antennas 20, 22 in order to detect an object O, for instance an obstacle along a traveling path of the vehicle V.

[0046] Distance R (and speed) of the object O are detected by measuring a time delay d between a transmitted signal (whose wave-front is shown in solid lines) and the received echo signal (whose wave-front is shown in dashed lines).

[0047] As exemplified in FIG. 1, the radar system 10, e.g., Frequency-Modulated Continuous-Wave (briefly, FMCW) radar system, comprises:

[0048] a transmitter chain 18, configured to provide a RF signal to drive a transmitting antenna 20,

[0049] a receiver chain 24 configured to detect the echo signal reflected from the obstacle 0,

[0050] a processing system 30 configured to drive the transmission of signals from the transmitter chain 18 and to process signals detected by the receiver chain 24.

[0051] As exemplified in FIG. 1, the transmitter chain 18 comprises:

[0052] a frequency synthesizer 11 configured to generate a local oscillator signal LO,

[0053] a frequency multiplier 12 coupled to the synthesizer ii and configured to receive the LO signal therefrom, the frequency multiplier 12 configured to provide an even harmonic of the LO signal,

[0054] a (transmitter) amplifier, e.g., a Variable-Gain Amplifier (briefly, VGA) or a power amplifier (briefly, PA), coupled to the frequency multiplier 12 to receive the (even) harmonic of the LO signal therefrom, the amplifier 14 configured to amplify the harmonic of the LO signal produced via the frequency multiplier 12 and to operate/drive a transmission (briefly, TX) antenna 20 therewith.

[0055] As exemplified in FIG. 1, the corresponding incoming (echo) signal received at a receiving (briefly, RX) antenna 22 is fed to the receiver chain 24, comprising:

[0056] a low noise amplifier (LNA) 26, coupled to the antenna to receive the echo signal therefrom, and

[0057] a mixer stage 28, coupled to the LNA 26 to receive the detected echo signal therefrom and coupled to the frequency multiplier 12 to receive the (even) harmonic of the local oscillator signal LO therefrom, the mixer stage 28 configured to produce a down-converted frequency signal IF based on the echo signal and the LO signal.

[0058] In one or more embodiments, the radar system 10 may be a system-on-chip integrated in a semiconductor device. For instance, the proposed frequency multiplier 12 can be integrated in a 28-nm FD-SOI CMOS technology device equipped on-board a transmitter stage of a mm-wave 77 GHz CMOS radar system.

[0059] As exemplified herein, the frequency multiplier circuitry is configured to produce a current signal having a second frequency value that is twice the first frequency value of the input signal.

[0060] For the sake of simplicity, one or more embodiments are discussed with respect to a frequency multiplier stage having a multiplication factor equal to two, that is a frequency doubler, being otherwise understood that such a multiplication factor is purely exemplary and in no way limiting. One or more embodiments apply to notionally any even integer multiplication factor.

[0061] As exemplified in FIG. 2, the frequency doubler 12 comprises:

[0062] a frequency multiplier 120 configured to receive a, e.g., high-quality, input signal V.sub.f0 at an input frequency f.sub.0 and to produce a high frequency output signal i.sub.2f0 having an output signal frequency 2f.sub.0 multiple of the input signal frequency f.sub.0 by an integer multiplication factor, e.g., a push-push voltage-to-current frequency doubler 120 configured to produce an output current signal i.sub.2f0 at twice the input frequency f.sub.0,

[0063] a transformer load 122 coupled to the frequency multiplier 120 and configured to receive the high frequency signal i.sub.2f0 therefrom, the transformer load 122 configured to provide a differential output signal V.sub.OUT to user circuits, e.g., to the power amplifier 14,

[0064] power supply rails VDD, GND comprising a first power supply rail VDD configured to provide a voltage level VDD referred to a ground level GND and a second power supply rail GND configured to provide the ground level,

[0065] shunt circuitry 124a, 124b, comprising a first, e.g., resonant, shunt circuit portion 124a interposed the first power supply rail VDD and a first node D of the transformer load 122 and a second, e.g., resonant, shunt circuit portion 124b, interposed the second power supply rail GND and a second node S of the frequency multiplier 120,

[0066] a bypass current path 126, e.g., a bypass stage interposed the first node D of the transformer load 122 and the second node S of the frequency multiplier 120, the bypass stage 126 configured to couple the first power supply rail VDD with the second shunt resonator 124b and the second power supply rail GND to the first shunt circuit portion 124a.

[0067] In one or more embodiments, the input signal V.sub.f0 has an input frequency value f.sub.0 such that the multiplied frequency value f.sub.2 of the frequency multiplied current signal i.sub.2f0 lies in the millimeter wavelength range.

[0068] As exemplified in FIG. 3, the transformer load 122 comprises a primary winding Lp, Cp and a secondary winding Ls, Cs, the primary winding Lp, Cp having a primary capacitance Cp and a primary inductance Lp coupled to the frequency multiplier 120 (e.g., via the current line of a parallel arrangement of transistors M.sub.1-M.sub.4, as discussed in the following) and the secondary winding Ls, Cs having a secondary inductance Ls and a secondary capacitance Cs configured to provide the differential output signal V.sub.OUT, e.g., to power amplifier 14.

[0069] As exemplified in FIG. 3, the frequency multiplier circuitry 120 exploits a balanced push-push arrangement, e.g., including a cascode pair of transistors M.sub.1, M.sub.2, M.sub.3, M.sub.4. This may facilitate providing an improved conversion gain, for instance thanks to a higher output resistance.

[0070] As exemplified in FIG. 3, a balanced push-push frequency multiplier 12 employs two sets of transistors M.sub.1, M.sub.2 and M.sub.3, M.sub.4 including:

[0071] a first set of transistors M.sub.1, M.sub.2 having a common current path therethrough and having respective control terminals IN.sub.N, IN.sub.P configured to receive a differential input signal V.sub.f0 (e.g., voltage difference between input node IN.sub.P and input node IN.sub.N) at the input frequency f.sub.0 and to be driven in anti-phase therebetween at the input frequency f.sub.0, which is at one half the desired output frequency 2f.sub.0, and

[0072] a second set of transistors M.sub.3, M.sub.4 having a common current path therethrough and having respective control terminals, V.sub.B configured to receive a proper biasing voltage.

[0073] As exemplified in FIG. 3, first transistors M.sub.1, M.sub.3 in the first and second sets of transistors M.sub.1, M.sub.2, M.sub.3, M.sub.4 and second transistors M.sub.2, M.sub.4 in the first and second sets of transistors M.sub.1, M.sub.2, M.sub.3, M.sub.4 have respective current paths therethrough arranged in parallel in a current line from the primary winding side Lp, Cp of the transformer 122, with the common node S coupled between the second shunt resonator 124b and the parallel arrangement of the first transistors M.sub.1, M.sub.3 and the second transistors M.sub.2, M.sub.4.

[0074] For instance, as the first transistor M.sub.1 and the second transistor M.sub.2 oscillate out-of-phase (that is, with a phase difference of 180° or 2π therebetween) with respect to each other, so that the fundamental frequency f.sub.0 cancels out while an even harmonic, e.g., the second harmonic 2f.sub.0, adds in phase, providing the frequency multiplied (e.g., current) signal i.sub.2f0.

[0075] As exemplified in FIG. 3, shunt circuit portions 124a, 124b, each comprise a (e.g., second harmonic 2f.sub.0) shunt resonator 124a, 124b, including at least one parallel arrangement of an inductance L.sub.SHUNT and a capacitance C.sub.SHUNT, for instance as a tuned DC-feed.

[0076] In one or more alternative embodiments, shunt circuit portions 124a, 124b, comprise resonant networks (e.g., of order n) tuned or configured to provide a first (e.g., high) impedance value at the multiplied frequency 2fo and a second (e.g., low DC) impedance value at frequencies different from the multiplied frequency 2f0, that is operating in a DC-feed like manner (known per se).

[0077] In one or more embodiments, the bypass stage 126 comprises a network configured to provide a first (e.g., low) impedance value at a frequency equal to said second frequency value of the frequency multiplied current signal and a second (e.g., high) impedance value at a DC level.

[0078] As exemplified in FIG. 3, the bypass stage 126 comprises a (e.g., second harmonic 2f.sub.0) series arrangement of an inductance L.sub.0 and a capacitance C.sub.0 as return path for signals at nodes D, S.

[0079] In an alternative embodiment, the bypass stage 126 may consist of a capacitor C.sub.0.

[0080] In alternative embodiments, the bypass stage 126 may comprise a resonant circuit network, e.g., of order n, the network configured to provide a low impedance at the desired multiplied frequency (e.g., 2f0).

[0081] As exemplified in FIG. 4, the power supply lines VDD, GND can have respective (parasitic) impedance Zs. For instance, shunt circuitry 124a, 124b, facilitates isolating nodes D, S from the power supply rails VDD, GND, thus preventing the high frequency current signal i.sub.2f0 from flowing in the (parasitic impedance Zs of) DC supply rails VDD, GND.

[0082] As exemplified in FIG. 4, tuned bypass 126 coupled the nodes D, S and provides a current path for the high frequency current signal i.sub.2f0. For instance, the tuned bypass comprises a resonator arrangement L.sub.0, C.sub.0 which does not suffer from (parasitic) impedance Zs of the power supply rails VDD, GND, facilitating maintaining an “unspoiled” frequency multiplied signal.

[0083] For instance, the bypass stage 126 comprises a resonating series arrangement of an inductance L.sub.0 and a capacitance C.sub.0 tuned to resonate at a frequency equal to said second frequency value of the frequency multiplied current signal i.sub.2f0.

[0084] As exemplified in FIG. 5, which is a plot of output voltage (in Voltage, ordinate scale) versus frequency (in GigaHertz, abscissa scale, where 1 GigaHertz=1 GHz=10.sup.9 Hz) for various values of impedance Zs of the power supply VDD, GND, an arrangement as exemplified in FIG. 3 facilitates providing an output voltage V.sub.OUT whose amplitude is invariant with respect to the (parasitic) impedance Z.sub.S of the power supply rails VDD, GND.

[0085] As exemplified in FIG. 6, the frequency multiplier 120 comprises:

[0086] a first transistor M.sub.1 having a first (e.g., gate) control terminal IN.sub.N configured to receive the input signal V.sub.f0 and a second transistor M.sub.2 having a second (e.g., gate) control terminal IN.sub.P configured to receive the anti-phase version of the input signal V.sub.f0;

[0087] at least a third transistor M.sub.3 arranged as a (e.g., common gate) buffer stage.

[0088] As exemplified in FIG. 6, the first transistor M.sub.1, the second transistor M.sub.2 and the buffer stage M.sub.3 have respective current paths therethrough arranged (in particular, in series) in a current line from the primary inductance Lp of the transformer 122 to the second shunt resonator 124b, the first and second transistors having a common node S between the second shunt resonator 124b, and the parallel arrangement of the first transistor M.sub.1 and the second transistor M.sub.2. As exemplified in FIG. 7, the buffer stage comprises a pair of transistors M.sub.3, M.sub.4 forming a folded cascode arrangement with the first and second transistors M.sub.1, M.sub.2.

[0089] For instance, the folded cascode arrangement comprises:

[0090] a first transistor M.sub.1 having a first control terminal IN.sub.N configured to receive the input signal V.sub.f0 and a second transistor M.sub.2 having a second control terminal IN.sub.P configured to receive the anti-phase version of said input signal V.sub.f0,

[0091] a third and a fourth transistor M.sub.3 and M.sub.4 having terminal V.sub.b configured to receive a proper biasing voltage.

[0092] As exemplified in FIG. 7:

[0093] the first transistor M.sub.1 has a first current path therethrough between a first node D1 of the frequency multiplier circuit 120 and the second shunt resonator 124b, the first node D1 coupled to the first shunt resonator 124a,

[0094] the second transistor M.sub.2 has a second current path therethrough between a second node D2 of the frequency multiplier circuit 120 and the second shunt resonator 124b, the second node D2 coupled to the first shunt resonator 124a,

[0095] first and second transistors have respective current paths therethrough arranged in parallel and have a common node S between the second shunt resonator 124b and the parallel arrangement of the first transistor M.sub.1 and the second transistor M.sub.2,

[0096] the third transistor M.sub.3 has a third current path therethrough between the first node D1 of the frequency multiplier circuit 120 and the primary inductance Lp of the primary winding side Cp, Lp of the transformer circuit 122,

[0097] the fourth transistor M.sub.4 has a fourth current path therethrough between the second node D2 of the frequency multiplier circuit 120 and the primary inductance Lp of the primary winding side Cp, Lp of the transformer circuit 122,

[0098] the first transistor M.sub.1 and the third transistor M.sub.3 have respective current paths coupled therebetween and wherein said second transistor M.sub.2 and said fourth transistor M.sub.4 have respective current paths coupled therebetween.

[0099] As exemplified in FIG. 8, the frequency multiplier 120 comprises a common source frequency doubler M.sub.1, M.sub.2 with the buffer stage arranged as a folded common gate M.sub.3, which has a current path therethrough along (e.g., in series) the current path of the first and second transistors M.sub.1, M.sub.2.

[0100] In one or more embodiments as exemplified in FIGS. 7 and/or 8, the bypass path providing a return path for the frequency multiplied current signal i.sub.2f0 comprises transistors M.sub.3 or M.sub.3 and M.sub.4. For instance, transistors M.sub.3, M.sub.4 are p-channel transistors and thus offer a “natural” current path for the current signal i.sub.2f0 towards the common source node S.

[0101] As exemplified in FIG. 9, the frequency multiplier arrangement comprising a stack or cascade of frequency multiplier circuits 12, 12′, 12″.

[0102] For instance, the frequency multiplier arrangement comprising a cascaded arrangement of a plurality of circuits 12, 12′, 12″ where at least one of the circuits in the cascaded arrangement 12, 12′, 12″ has its input node (e.g., V.sub.f2 of a second circuit 12′ and/or V.sub.f4 of a third circuit 12″) coupled to an output node (e.g., V.sub.f2 of a first circuit 12 and/or V.sub.f4 of the second circuit 12′) of another one of the circuits in the cascaded arrangement 12, 12′, 12″.

[0103] As exemplified in FIG. 9, the transmitter chain 18 equipped with such a cascade arrangement, comprises:

[0104] the frequency synthesizer 11, e.g., a voltage-controlled oscillator VCO, configured to generate an input signal V.sub.f0 oscillating at an input frequency f.sub.0,

[0105] a first frequency multiplier 12 coupled to the frequency synthesizer ii and configured to receive the input signal V.sub.f0 therefrom, the first frequency multiplier 12 configured to provide a first frequency multiplied signal V.sub.f2 having first frequency f.sub.2 as an even multiple, e.g., twice, of the input frequency f.sub.0,

[0106] a second frequency multiplier 12′, coupled to the first 12 and to a third frequency multiplier 12″, the second frequency multiplier 12′ configured to receive the first frequency multiplied signal V.sub.f2 and to provide a second frequency multiplied signal V.sub.f4 having a second frequency f.sub.4 as an even harmonic of the first f.sub.2 or input f.sub.0 frequency, e.g., twice the first frequency f.sub.2 and fourfold the input frequency f.sub.0,

[0107] the third frequency multiplier 12″, coupled to the second frequency multiplier 12′ and configured to receive the second frequency multiplied signal V.sub.f4 therefrom, the third frequency multiplier 12″ configured to be further coupled to the power amplifier 14 (and/or to the mixer stage 28, as exemplified in FIG. 1) to provide thereto a third frequency multiplied signal V.sub.18 having a third frequency f.sub.8 as an even harmonic of the second f.sub.4 or input f.sub.0 frequency, e.g., twice the second frequency f.sub.4 and eightfold the input frequency f.sub.0.

[0108] For the sake of simplicity, the cascaded arrangement of circuits 12, 12′, 12″ illustrates three circuits forming such an arrangement, being otherwise understood that such a number of circuits is purely exemplary and in no way limiting. In particular, notionally any number of frequency multiplier circuits 12, 12′, 12″ may be stacked therebetween until a last N-th frequency multiplier 12 in the stack, receives a (N−1)-th frequency multiplied signal and provide (e.g., to the power amplifier 14 and/or to the mixer 28) a N-th multiplied signal having frequency 2N-fold the input frequency f.sub.0, e.g., f.sub.N=2*N*f.sub.0.

[0109] As exemplified herein, a frequency multiplier arrangement comprises a cascaded arrangement of a plurality of circuits (for instance, 12, 12′, 12″) as per the present disclosure, wherein at least one of the circuits in the cascaded arrangement has its input node (for instance, V.sub.f0, V.sub.f2, V.sub.f4) coupled to the output node (for instance, V.sub.f2, V.sub.f4, V.sub.f8) of another one of the circuits in the cascaded arrangement.

[0110] As exemplified herein, a (e.g., radar) system (for instance, 10, 18) comprises:

[0111] a circuit or a frequency multiplier arrangement as per the present disclosure, and

[0112] a power amplifier (for instance, 14) coupled to the circuit and configured to receive the frequency multiplied voltage signal therefrom, the power amplifier configured to amplify the frequency multiplied voltage signal and to provide an amplified frequency multiplied signal (for instance, TX) as a result,

[0113] a transmitter antenna (for instance, 20) coupled to the power amplifier and configured to transmit the amplified frequency multiplied signal.

[0114] As exemplified herein, the system comprises a frequency synthesizer (for instance, 11) coupled to the circuit and configured to provide thereto the input signal at the first frequency.

[0115] As exemplified herein, a radar system configured to be equipped on a vehicle (for instance, V) further includes:

[0116] a receiver antenna (for instance, 22) configured to receive an echo signal based on the transmitted amplified frequency multiplied signal (for instance, TX),

[0117] a mixer stage (for instance, 28) coupled to the circuit or the frequency multiplier arrangement, the mixer stage configured to apply frequency mixing to the frequency multiplied voltage signal and to the echo signal, producing a mixed signal as a result.

[0118] As exemplified herein, a circuit (for instance, 12), comprises:

[0119] a frequency multiplier circuit (for instance, 120) having input nodes (for instance, IN.sub.P, IN.sub.N) configured to receive an input signal (for instance, V.sub.f0) and an anti-phase version thereof, the input signal having a first frequency value, the frequency multiplier circuitry (for instance, frequency doubler circuitry) configured to produce a current signal (for instance, i.sub.2f0) at a second frequency value that is an even multiple (for instance, falling in the millimeter wave range) of said first frequency value,

[0120] a transformer (for instance, 122) comprising a primary winding (for instance, Lp, Cp) and a secondary winding (Ls, Cs), wherein the primary winding of the transformer comprises a primary inductance (for instance, Lp) coupled (for instance, 126) to the frequency multiplier circuitry to receive the current signal therefrom, wherein the secondary winding of the transformer is configured to provide a frequency multiplied voltage signal (for instance, V.sub.OUT), in particular based on the current signal at the second frequency value received from the frequency multiplier circuitry,

[0121] wherein the frequency multiplier circuit and the transformer are cascaded between at least one first node (for instance, D; D1, D2) and a second node (for instance, S), the at least one first node and the second node configured to be coupled to a supply node (for instance, VDD) and ground (for instance, GND),

[0122] a first shunt resonator (for instance, 124a) coupled between the supply node and the at least one first node,

[0123] a second shunt resonator (for instance, 124b) coupled between the second node and ground, and

[0124] a bypass current path (for instance, 126; M3, M4) coupled between the at least one first node and said second node.

[0125] As exemplified herein, the transformer is arranged:

[0126] intermediate the at least one first node and the frequency multiplier circuit, or

[0127] intermediate the frequency multiplier circuit and the second node.

[0128] As exemplified herein, the frequency multiplier circuit comprises:

[0129] a first transistor (for instance, M.sub.1) having a first control terminal (for instance, IN.sub.N) configured to receive the input signal and a second transistor (for instance, M.sub.2) having a second control terminal (for instance, IN.sub.P) configured to receive the anti-phase version of said input signal, the first transistor and the second transistor having a common source node and respective current paths therethrough arranged in parallel in a current line from the at least one node to the second node.

[0130] As exemplified herein, the frequency multiplier circuit further comprises at least one third transistor (for instance, M.sub.3) having a control terminal (for instance, V.sub.B) configured to receive a biasing voltage and the bypass current path (for instance, 126) therethrough along the current line from the at least one node to the second node.

[0131] As exemplified herein, the frequency multiplier circuit further comprises:

[0132] a third transistor (for instance, M.sub.3) having a third control terminal (for instance, V.sub.B) configured to receive a biasing voltage and a fourth transistor (for instance, M.sub.4) having a fourth control terminal (for instance, V.sub.b) configured to receive the biasing voltage; the third transistor and the fourth transistor having a common node and respective bypass current paths (for instance, 126) therethrough arranged in parallel in a current line from the at least one node to the second node, wherein the first transistor and the third transistor have respective current paths coupled therebetween and wherein said second transistor and said fourth transistor have respective current paths coupled therebetween.

[0133] As exemplified herein, the frequency multiplier circuit comprises:

[0134] a first transistor (for instance, M.sub.1) having a first control terminal (for instance, IN.sub.N) configured to receive the input signal and a second transistor (for instance, M.sub.2) having a second control terminal (for instance, IN.sub.P) configured to receive the anti-phase version of said input signal,

[0135] wherein the first transistor has a first current path therethrough between a first node (for instance, D1) of the at least one node,

[0136] wherein the second transistor has a second current path therethrough between a second node (for instance, D2) of the at least one node,

[0137] wherein the first and second transistors have a common source node and respective current paths therethrough arranged in parallel,

[0138] the frequency multiplier circuit further comprising a third transistor (for instance, M.sub.3) having a third control terminal (for instance, V.sub.B) configured to receive a biasing voltage and a fourth transistor (for instance, M.sub.4) having a fourth control terminal (for instance, V.sub.B) configured to receive a biasing voltage,

[0139] wherein the third transistor has a third current path therethrough between the first node of the at least one node and the primary inductance of the primary winding of the transformer circuit,

[0140] wherein the fourth transistor has a fourth current path therethrough between the second node of the at least one node and the primary inductance of the primary winding of the transformer circuit,

[0141] wherein the first transistor and the third transistor have respective current paths coupled therebetween and wherein said second transistor and said fourth transistor have respective current paths coupled therebetween.

[0142] As exemplified herein:

[0143] the bypass current path comprises a resonating series arrangement of an inductance (for instance, L.sub.0) and a capacitance (for instance, C.sub.0) tuned to resonate at a frequency equal to said second frequency value of the frequency multiplied current signal (i.sub.2f0), and/or

[0144] at least one of the first shunt resonator and the second shunt resonator comprises a resonant circuit network tuned to provide a first (e.g., low) impedance value at a frequency equal to said second frequency value of the frequency multiplied current signal and a second (e.g., high) impedance value at a frequency different from said second frequency value of the frequency multiplied current signal.

[0145] It will be otherwise understood that the various individual implementing options exemplified throughout the figures accompanying this description are not necessarily intended to be adopted in the same combinations exemplified in the figures. One or more embodiments may thus adopt these (otherwise non-mandatory) options individually and/or in different combinations with respect to the combination exemplified in the accompanying figures.

[0146] Without prejudice to the underlying principles, the details and embodiments may vary, even significantly, with respect to what has been described by way of example only, without departing from the extent of protection. The extent of protection is defined by the annexed claims.