SEMICONDUCTOR POWER DEVICE WITH IMPROVED RUGGEDNESS

Abstract

Aspects of the present disclosure relate to a semiconductor power device, in particular to a Silicon Carbide, SiC, Merged P-I-N Schottky (MPS) diode. The device includes an active area and a termination area adjacent the active area. The termination area includes first rings having a first polarity. By including second rings having a second polarity opposite to the first polarity, a reduced effect of interface charges on the performance of the semiconductor power device can be observed.

Claims

1. A semiconductor power device, comprising: a semiconductor body including a semiconductor substrate and an epitaxial layer formed on the semiconductor substrate; an active area and a termination area adjacent the active area arranged in the epitaxial layer; wherein the termination area comprises a plurality of first rings of a first polarity, and a plurality of second rings of a second polarity different from the first polarity; wherein the semiconductor substrate and the epitaxial layer have the second polarity; wherein the epitaxial layer has a dopant concentration associated with the second polarity that is smaller than a dopant concentration in the second rings associated with the second polarity; and wherein the termination area further comprises a junction termination extension (JTE) border of the first polarity type, and wherein the first and second rings are separately formed from and arranged inside the junction termination extension border.

2. The semiconductor power device according to claim 1, wherein the first rings associated with the first polarity have a dopant concentration that is higher than a dopant concentration of the JTE border associated with the first polarity.

3. The semiconductor power device according to claim 1, wherein the plurality of first rings extends farther towards the semiconductor substrate than the plurality of second rings; and wherein the first rings extend more than 100 nanometers beyond the second rings; and/or wherein the first rings extend more than 100 percent beyond the second rings.

4. The semiconductor power device according to claim 1, wherein the dopant concentration in the second rings associated with the second polarity is at least 100 times larger than the dopant concentration in the epitaxial layer associated with the second polarity.

5. The semiconductor power device according to claim 1, wherein the first rings and second rings are arranged alternately.

6. The semiconductor power device according to claim 1, wherein the first and second rings are configured to be electrically floating during operation.

7. The semiconductor power device according to claim 1, wherein the termination area is at least partially covered by a passivation layer; wherein the passivation layer comprises a passivation layer made of a material selected from the group consisting of Silicon Nitride, Silicon Oxynitride, Silicon Oxide, and Metallic Oxide; and/or wherein the passivation layer comprises a field oxide.

8. The semiconductor power device according to claim 1, wherein the semiconductor power device comprises a device selected from the group consisting of a Merged P-I-N Schottky (MPS) diode, a MOSFET, a JFET, a Schottky barrier, and a PN diode.

9. The semiconductor power device according to claim 1, wherein the semiconductor substrate comprises a Silicon Carbide substrate; and/or wherein the first polarity corresponds to p-type and the second polarity to n-type.

10. The semiconductor power device according to claim 2, wherein the dopant concentration of the first rings associated with the first polarity lies in a range between 1E19 and 1E20 #/cm3, and wherein the dopant concentration of the JTE border associated with the first polarity lies in a range between 1E17 and 1E20 #/cm3.

11. The semiconductor power device according to claim 2, wherein the plurality of first rings extends farther towards the semiconductor substrate than the plurality of second rings; and wherein the first rings extend more than 100 nanometers beyond the second rings; and/or wherein the first rings extend more than 100 percent beyond the second rings.

12. The semiconductor power device according to claim 2, wherein the dopant concentration in the second rings associated with the second polarity is at least 100 times larger than the dopant concentration in the epitaxial layer associated with the second polarity.

13. The semiconductor power device according to claim 2, wherein the first rings and second rings are arranged alternately.

14. The semiconductor power device according to claim 5, wherein the termination area further comprises a plurality of floating JTE rings of the first polarity arranged spaced apart from the first and second rings and spaced apart from the JTE border.

15. The semiconductor power device according to claim 7, further comprising a channel stopper arranged at or near an edge of the semiconductor power device, wherein the termination area is arranged in between the channel stopper and the active area, and wherein the channel stopper is of the second polarity.

16. The semiconductor power device according to claim 7, wherein, when the passivation layer is made of a material selected from the group consisting of Silicon Nitride, Silicon Oxynitride, Silicon Oxide and Metallic Oxide, and extends over the termination area from a region directly above the channel stopper towards the active area, a part of the plurality of first and second rings is covered.

17. The semiconductor power device according to claim 7, wherein, when the passivation layer comprises the field oxide, it extends over the termination area from a region directly above the channel stopper towards the active area thereby fully covering the plurality of first and second rings.

18. The semiconductor power device according to claim 8, wherein the semiconductor power device comprises a MPS diode, and wherein the active area comprises: a conductive layer assembly comprising one or more conductive layers; a plurality of mutually separated islands of the first polarity arranged in a current distribution layer of the second polarity; wherein the conductive layer assembly forms Schottky contacts with the current distribution layer; wherein the conductive layer assembly forms Ohmic contacts with the plurality of islands of the first polarity; wherein the conductive layer assembly forms a first contact of the MPS diode; and wherein the MPS diode comprises a second contact arranged on the semiconductor substrate.

19. The semiconductor power device according to claim 18, wherein the current distribution layer is formed by a well of the second polarity formed in the epitaxial layer, and wherein the current distribution layer associated with the second polarity has a dopant concentration that is 2 times larger than a dopant concentration of the epitaxial layer associated with the second polarity.

Description

BRIEF DESCRIPTION OF DRAWINGS

[0029] So that the manner in which the features of the present disclosure can be understood in detail, a more particular description is made with reference to embodiments, some of which are illustrated in the appended figures. It is to be noted, however, that the appended figures illustrate only typical embodiments and are therefore not to be considered limiting of its scope. The figures are for facilitating an understanding of the disclosure and thus are not necessarily drawn to scale. Advantages of the subject matter claimed will become apparent to those skilled in the art upon reading this description in conjunction with the accompanying figures, in which like reference numerals have been used to designate like elements, and in which:

[0030] FIG. 1 illustrates a general top view of a semiconductor power device.

[0031] FIG. 2 illustrates a cross section of a first embodiment of a semiconductor power device in accordance with an aspect of the present disclosure.

[0032] FIG. 3 illustrates a cross section of a second embodiment of a semiconductor power device in accordance with an aspect of the present disclosure.

DETAILED DESCRIPTION

[0033] In FIG. 1, a general top view of a semiconductor power device 100 is shown that comprises an active area 101 in which a semiconductor device is realized, a termination area 102 adjacent to active area 101, and a channel stopper 103. Typically, semiconductor power device 100 is made from a semiconductor wafer on which a plurality of devices 100 are simultaneously formed. Channel stopper 103 may, prior to separating the devices, comprise structures, such as a saw lane, that allow the devices to be separated. Another structure that is or could be present in channel stopper 103 is a part of the passivation layer.

[0034] FIGS. 2 and 3 present cross sections that correspond to the dashed line in FIG. 1. Here, it is noted that those figures present an exemplary embodiment of a semiconductor power device in the form of a SiC MPS diode. However, the present invention is not limited thereto and aspects of the present disclosure could equally be applied to other semiconductor power devices such as MOSFETs, JFETs, Schottky barriers, or PN diodes, realized on different semiconductor material technologies such as Si, GaN, AlGaN and other II-VI or III-V semiconductor materials.

[0035] Now referring to FIG. 2, MPS diode 100A comprises a semiconductor body 130 comprising an n-type SiC substrate 110 on which an n-type SiC epitaxial layer 111 has been grown. Typical dopant concentrations in these layers are 1E19 #/cm3 and 1E16 #/cm3, respectively. Inside epitaxial layer 111, a n-type current spreader 112 with a typical dopant concentration of 5E16 #cm3 has been formed using ion implantation. In turn, inside current spreader 112, a plurality of p-type wells 113 have been formed using ion implantation. Inside wells 113, highly doped p-type contact regions 114 have been formed using ion implantation to allow low Ohmic contact resistance with an NiSi conductive layer 115. Typical dopant concentrations for wells 113 and contact region 114 are 1E18 #/cm3 and 1E20 #cm3, respectively.

[0036] MPS diode 100A further comprises a Ti/TiN layer 116 covering the top surface of current spreader 112 and NiSi layer 115. At the regions where layer 116 contacts current spreader 112, i.e. in between wells 113, a Schottky contact is formed, whereas the NiSi layer 115 forms an Ohmic contact with contact region 114. Ti/TiN layer 116 is covered by a relatively thick AlCu layer 117 that forms a first contact terminal of MPS diode 100A. NiSi layer 115, Ti/TIN layer 116, and AlCu layer 117 may jointly be referred to as conductive layer assembly. Furthermore, a second contact terminal of MPS diode 100A is formed at a backside of SiC substrate 110.

[0037] Termination area 102 comprises a plurality of p-type first rings 120 having a typical dopant concentration of 1E20 #/cm3. In between p-type first rings 120, a plurality of n-type second rings 121 are arranged that have a typical dopant concentration of 5E19 #/cm3. As shown, first rings 120 extend farther towards SiC substrate 110 than rings 121. For example, a height of first rings 120 equals 0.3 micrometer, whereas a height of second rings 121 equals 0.15 micrometer.

[0038] Both first and second rings 120,121 are provided inside a p-type JTE border 122 having a typical dopant concentration of 5E17 #/cm3. Adjacent to JTE border 122, a plurality of p-type JTE rings 124 are arranged that have a typical dopant concentration of 5E17 #/cm3.

[0039] In between channel stopper 103 and active area 101, a passivation layer 123 is provided that is made of Silicon Nitride, Silicon Oxynitride, Silicon Oxide, Metallic Oxide or a suitable combination thereof. As shown, passivation layer 123 does not extend over the entire surface between channel stopper 103 and active area 101. Furthermore, as shown, an n-type second ring 121 is arranged in between p-type well 113 and the first of the p-type first rings 120.

[0040] Rings 120, 121, 124 are generally electrically floating during operation.

[0041] FIG. 2 presents several structures inside termination area 102. More in particular, MPS diode 100A comprises first rings 120, second rings 121, JTE border 122, and JTE rings 124. Among these structures, JTE border 122 and JTE rings 124 are optional. Several different embodiments are therefore possible according to aspects of the present disclosure as outlined in the list below: [0042] Embodiment 1: rings 120, rings 121, JTE border 122, JTE rings 124 (as shown in FIG. 2); [0043] Embodiment 2: rings 120, rings 121; [0044] Embodiment 3: rings 120, rings 121, JTE border 122; and [0045] Embodiment 4: rings 120, rings 121, JTE rings 124.

[0046] The list above indicates which structures are possible in the various different embodiments.

[0047] FIG. 3 illustrates a further MPS diode 100B that differs from MPS diode 100A in that a field oxide 125 made of Silicon Oxide is used as passivation layer instead of passivation layer 123 for directly contacting the top surface of semiconductor body 130. Contrary to passivation layer 123, field oxide 125 spans the entire surface between channel stopper 103 and active area 101. In addition, Ti/TiN layer 116 partially covers field oxide 125. In addition, a passivation layer 123 is arranged above part of Ti/TiN layer 116 and field oxide 125.

[0048] In the embodiments of FIGS. 2 and 3, a separate conductive layer, i.e. NiSi layer 115, was used for realizing an Ohmic contact. In other embodiments, a same conductive layer, for example comprising one or more metal layers, may be used for simultaneously forming the Ohmic contact to p-type wells 113 and the Schottky contacts to current spreader 112.

[0049] The scope of the present disclosure includes any novel feature or combination of features disclosed therein either explicitly or implicitly or any generalization thereof irrespective of whether or not it relates to the claimed invention or mitigate against any or all of the problems addressed by the present invention. The applicant hereby gives notice that new claims may be formulated to such features during prosecution of this application or of any such further application derived therefrom. In particular, with reference to the appended claims, features from dependent claims may be combined with those of the independent claims and features from respective independent claims may be combined in any appropriate manner and not merely in specific combinations enumerated in the claims.

[0050] Features which are described in the context of separate embodiments may also be provided in combination in a single embodiment. Conversely, various features which are, for brevity, described in the context of a single embodiment, may also be provided separately or in any suitable sub combination.

[0051] The term comprising does not exclude other elements or steps, the term a or an does not exclude a plurality. Reference signs in the claims shall not be construed as limiting the scope of the claims.