Abstract
A power device includes a semiconductor substrate having first and second current carrying terminals on respective first and second opposing surfaces thereof. A silicided polysilicon temperature sensor and silicided polysilicon gate electrode are provided on the first surface. A source region of first conductivity type and a shielding region of second conductivity type are provided in the semiconductor substrate. The shielding region forms a P-N rectifying junction with the source region, and extends between the silicided polysilicon temperature sensor and the second current carrying terminal. A field oxide insulating region is provided, which extends between the shielding region and the silicided polysilicon temperature sensor.
Claims
1. A power semiconductor device, comprising: a semiconductor substrate having first and second current carrying terminals on respective first and second opposing surfaces thereof; and a silicided polysilicon temperature sensor on the first surface.
2. The device of claim 1, wherein a first terminal of the silicided polysilicon temperature sensor is electrically coupled to the first current carrying terminal.
3. The device of claim 1, further comprising a silicided polysilicon gate electrode on the first surface.
4-6. (canceled)
7. The device of claim 1, further comprising: a source region of first conductivity type in the semiconductor substrate, which is electrically connected to a first terminal of the silicided polysilicon temperature sensor; and a shielding region of second conductivity type in the semiconductor substrate, which extends between the silicided polysilicon temperature sensor and the second current carrying terminal.
8. The device of claim 4, wherein a resistance of the silicided polysilicon temperature sensor monotonically increases with temperature.
9. The device of claim 8, wherein a resistance of the silicided polysilicon temperature sensor is in a range from 1 Ω/square to 5 Ω/square at 25° C.
10. The device of claim 8, wherein the silicided polysilicon temperature sensor is doped with a dopant of first conductivity type; and wherein the resistance of the silicided polysilicon temperature sensor increases at a rate within a range from 0.075%/° C. to 0.175%/° C. in an operating temperature range.
11-14. (canceled)
15. The device of claim 9, wherein a length of the silicided polysilicon temperature sensor is in a range from 5 squares to 500 squares.
16. The device of claim 1, wherein the first and second current carrying terminals are source and drain terminals of an insulated-gate field effect transistor (IGFET), respectively.
17. The device of claim 1, wherein the first and second current carrying terminals are emitter and collector terminals of an insulated-gate bipolar transistor (IGBT), respectively.
18. The device of claim 17, wherein a first terminal of the silicided polysilicon temperature sensor is electrically coupled to the emitter terminal of the IGBT.
19. The device of claim 1, further comprising a third current carrying terminal on the first surface of the semiconductor substrate; and a second silicided polysilicon temperature sensor on the first surface; and wherein the power semiconductor device is a silicon carbide (SiC) bi-directional field effect transistor (BiDFET).
20. The device of claim 19, wherein first and second terminals of the second silicided polysilicon temperature sensor are independent of the first, second and third current carrying terminals.
21. A power semiconductor device, comprising: a silicon carbide (SiC) substrate having a first source electrode of a first MOSFET and a second source electrode of a second MOSFET at spaced-apart locations on a first surface thereof; and first and second silicided polysilicon temperature sensors associated with the first and second MOSFETs, respectively, on the first surface.
22. The device of claim 21, wherein first and second terminals of each of the first and second silicided polysilicon temperature sensors are independent of the first and second source electrodes.
23. The device of claim 21, wherein a first terminal of the first silicided polysilicon temperature sensor is electrically connected to the first source electrode; and wherein a first terminal of the second silicided polysilicon temperature sensor is electrically connected to the second source electrode.
24. The device of claim 23, wherein a first gate electrode of the first MOSFET comprises silicided polysilicon derived from a silicided polysilicon layer; and wherein the first and second silicided polysilicon temperature sensors are derived from the same silicided polysilicon layer.
25. The device of claim 21, wherein a first gate electrode of the first MOSFET comprises silicided polysilicon derived from a silicided polysilicon layer; and wherein the first and second silicided polysilicon temperature sensors are derived from the same silicided polysilicon layer.
26. (canceled)
27. A power semiconductor device, comprising: a semiconductor substrate having an insulated-gate bipolar transistor (IGBT) therein; and a silicided polysilicon temperature sensor having a first current carrying terminal electrically coupled to an emitter terminal of the IGBT.
28. The device of claim 27, wherein a gate electrode of the IGBT comprises silicided polysilicon derived from a silicided polysilicon layer; and wherein the silicided polysilicon temperature sensor is derived from the same silicided polysilicon layer.
29. (canceled)
30. (canceled)
Description
BRIEF DESCRIPTION OF THE DRAWINGS
[0022] FIG. 1A is a cross-sectional view of a planar-gate MOSFET having an inversion-mode active region, according to the prior art.
[0023] FIG. 1B is a cross-sectional view of a planar-gate MOSFET having an accumulation-mode active region, according to the prior art.
[0024] FIG. 1C is a cross-sectional view of a trench-gate MOSFET having a vertical inversion-mode active region, according to the prior art.
[0025] FIG. 1D is a cross-sectional view of a trench-gate silicon (Si) insulated-gate bipolar transistor (IGBT), according to the prior art.
[0026] FIG. 2A is a simplified electrical schematic of a high power insulated-gate bipolar transistor (IGBT), which is thermally coupled to a silicided polysilicon temperature sensor, according to an embodiment of the invention.
[0027] FIG. 2B is a simplified electrical schematic of a high power metal-oxide-semiconductor field effect transistor (MOSFET), which is thermally coupled to a silicided polysilicon temperature sensor, according to an embodiment of the invention.
[0028] FIG. 3A is a cross-sectional view of a high power MOSFET half-cell with an adjacent silicided polysilicon temperature sensor, according to an embodiment of the invention.
[0029] FIG. 3B is a graph illustrating a resistance versus temperature characteristic of a silicided polysilicon temperature sensor, according to an embodiment of the invention.
[0030] FIG. 4A is a plan layout view of a silicon carbide (SiC) bidirectional field effect transistor (BiDFET), according to an embodiment of the invention.
[0031] FIG. 4B is an enlarged view of a highlighted portion of the BiDFET of FIG. 4A, which illustrates a layout configuration of a silicided polysilicon temperature sensor, according to an embodiment of the invention.
[0032] FIG. 5 is an electrical schematic of a SiC/Si Composite BiDFET with short-circuit protection, according to an embodiment of the invention.
DETAILED DESCRIPTION OF EMBODIMENTS
[0033] The present invention now will be described more fully with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like reference numerals refer to like elements throughout.
[0034] It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
[0035] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present invention. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context dearly indicates otherwise. It will be further understood that the terms “comprising”, “including”, “having” and variants thereof, when used in this specification, specify the presence of stated features, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and/or groups thereof. In contrast, the term “consisting of” when used in this specification, specifies the stated features, steps, operations, elements, and/or components, and precludes additional features, steps, operations, elements and/or components.
[0036] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
[0037] Referring now to FIG. 2A, a high power semiconductor device according to an embodiment of the invention is illustrated as including an insulated-gate bipolar transistor (IGBT) 20a, which contains a gate (G) terminal, and a pair of current carrying collector (C) and emitter (E) terminals. In some of these embodiments, the IGBT 20a may be configured as a vertical power device, with the current carrying collector terminal C and the current carrying emitter terminal E extending on (or adjacent) opposing surfaces of a semiconductor substrate, such as a silicon (Si) or silicon carbide (SiC) substrate, for example, or other III-V or II-VI semiconductor material substrate. In addition, a silicided polysilicon temperature sensor 22a, which may be configured as a silicided polysilicon resistor (R.sub.T-Sense) having two current carrying terminals T.sub.S1, T.sub.S2, is provided as integral to the semiconductor device. Advantageously, this resistor R.sub.T-Sense supports enhanced switching control/operation of the IGBT by facilitating real-time temperature measurements during device operation to thereby prevent damage resulting from thermal stress (e.g., overheating). In some embodiments, the resistor R.sub.T-Sense may be configured to be in sufficiently dose proximity to the IGBT 20a to receive thermal energy (e.g., heat) therefrom, and enable accurate measurement and/or calculation of an operating temperature within of the IGBT 20a, as explained more fully hereinbelow. In further embodiments, one of the current carrying terminals of the silicided polysilicon resistor R.sub.T-Sense may be directly electrically coupled to a current carrying terminal of the IGBT (e.g., emitter terminal), in order to reduce overall pin count when the power semiconductor device is packaged (and the current carrying terminal of the IGBT is held at a fixed voltage potential (e.g., GND)).
[0038] Similarly, as illustrated by FIG. 2B, another high power semiconductor device according to an embodiment of the invention is illustrated as including an insulated-gate field effect transistor (e.g., MOSFET) 20b, which contains a gate (G) terminal, and a pair of current carrying drain (D) and source (S) terminals. This MOSFET 20b may be configured as a vertical power device, with the source terminal S and the drain terminal D extending on (or adjacent) opposing surfaces of a semiconductor substrate (e.g., Si, SiC, etc.). A silicided polysilicon temperature sensor 22b, which is shown as a silicided polysilicon resistor (R.sub.T-Sense) having two current carrying terminals T.sub.S1, T.sub.S2, is provided as integral to the semiconductor device, to support reliable switching and control thereof by preventing thermal malfunction. In some embodiments of the invention, this silicided polysilicon temperature sensor 22b may be formed concurrently with formation of the gate terminal as a silicided polysilicon gate electrode. In addition, the resistor R.sub.T-Sense may be configured to be in sufficiently close proximity to the MOSFET 20b to receive thermal energy (e.g., heat) therefrom. In further embodiments, one of the current carrying terminals of the silicided polysilicon resistor R.sub.T-Sense may be directly electrically coupled to a current carrying terminal of the MOSFET (e.g., source terminal), in order to reduce overall pin count when the power semiconductor device is packaged (and the current carrying terminal of the MOSFET is held at a fixed voltage potential (e.g., GND)).
[0039] Referring now to FIG. 3A, an embodiment of the high power semiconductor device of FIG. 2B is shown as including a vertical power MOSFET 30 and a silicided polysilicon temperature sensing resistor 32 in close proximity to the MOSFET 30. The MOSFET 30 includes metal source and drain electrodes/terminals 34a, 34b on opposing first and second surfaces 36a, 36b of a semiconductor substrate 36. This semiconductor substrate 36 is shown as including a plurality of semiconductor regions/layers of first conductivity type (e.g., N-type) and second conductivity type (e.g., P-type). In particular, the substrate 36 includes a relatively thick, voltage-supporting, drift region 38a of first conductivity type, which is provided on, and forms a non-rectifying junction with, a highly doped substrate region/layer 38b of first conductivity type that is in ohmic contact with the drain electrode/terminal 34b on the second surface 36b. A JFET neck region 42 of first conductivity type is also provided between the drift region 38a and the first surface 36a. This JFET neck region 42 extends opposite a portion of an insulated gate electrode 44a, 44b (e.g., MOS gate), which extends on the first surface 36a, and is spaced from a source region 46 of first conductivity type by a P-base region 48 of second conductivity type. As will be understood by those skilled in the art, this P-base region 48 supports the formation of an N-type inversion-layer channel therein, in response to the application of a sufficiently positive gate bias to the gate electrode 44a.
[0040] As shown, the drift region 38a and JFET neck region 42 form corresponding P-N rectifying junctions with a P+ voltage shielding region 52 of second conductivity type. This P+ shielding region 52 extends to the first surface 36a and forms an ohmic contact with the source electrode/terminal 34a, which is also in direct ohmic contact with the source region 46. These aspects of the vertical MOSFET 30 are further illustrated and described hereinabove with respect to FIG. 1A and the aforementioned U.S. Pat. Nos. 6,791,143 and 7,041,559 to B. Jayant Baliga.
[0041] Referring still to FIG. 3A, the silicided polysilicon temperature sensing resistor 32 is provided on the first surface 36a, and is electrically isolated and shielded from the underlying substrate 36 (and drain electrode 34b) by an electrically insulating field oxide isolation region 54 having a thickness in a range from 1000 Å to 10,000 Å. In the illustrated embodiment, the temperature sensing resistor 32 includes two terminals (T.sub.S1, T.sub.S2) at opposing ends thereof, which are spaced by a distance equivalent to Lam. The first terminal T.sub.S1 may be provided in direct electrical contact with a source electrode/terminal 34a of the MOSFET 30, and the second terminal T.sub.S2 may be provided as an independent terminal, which is electrically coupled (e.g., by wire bonding, etc.) to a pin of a package (not shown) containing the MOSFET 30. Thus, the source electrode/terminal 34a of the MOSFET 30 may support a dual-function as: (i) a fixed-voltage (e.g., GND), current carrying, terminal of the MOSFET 30, and (ii) a current carrying terminal of the temperature sensing resistor 32. However, in alternative embodiments, the first terminal T.sub.S1 may be provided independently as a separate pin when the MOSFET 30 is packaged.
[0042] Advantageously, the length, L.sub.Sense, width, and film thickness of the silicided polysilicon temperature sensing resistor 32 may be defined by photolithographically patterning a blanket polysilicon layer after it has undergone metal silicidation (e.g., of its upper surface), using a conventional metal such as tungsten (W), for example. Moreover, these processing steps may be performed concurrently with the formation of the gate electrode 44a of the MOSFET 30, and without requiring any additional processing and/or masking steps during device fabrication.
[0043] In addition, a resistance of the silicided polysilicon temperature sensing resistor 32, which is based primarily on its length and width, can be easily monitored in-situ (e.g., during active operation) using conventional circuitry (not shown) located outside the package containing the power MOSFET 30, such as disdosed in the aforementioned Chang et al. article. Then, as shown by the monotonically increasing resistance versus temperature graph of FIG. 3B, a continuously measured resistance of the resistor 32 can be readily converted into a reliable measurement of temperature (° C.). This is because the resistor 32 can be sufficiently isolated from the structure of the power MOSFET 30, so its resistance is not materially influenced by the switching of the power MOSFET 30 during operation. As further shown by FIG. 3B, a resistance increase of about 15% over a temperature range from 25° C. to 150° C. (for a resistor having a length of 30 squares) is sufficient for reliable in-situ monitoring.
[0044] In particular, according to further embodiments of the invention, the silicided polysilicon temperature sensing resistor 32 may be configured so that (i) its resistivity monotonically increases in a range from 25° C. to 125° C. (and possibly across a range from −50° C. to 250° C.), and (ii) its resistance is in a range from 1 Ω/square to 5 Ω/square at 25° C. In still further embodiments, the silicided polysilicon temperature sensor 40 may be configured so that its resistivity increases at a rate within a range from 0.075%/° C. to 0.175%/° C., throughout the range from 25° C. to 125° C., and a length of the silicided polysilicon temperature sensor 40 may be in a range from 5 squares to 500 squares.
[0045] Referring now to FIG. 4A, a plan layout view of a multiple unit cell silicon carbide (SiC) bidirectional field effect transistor (BiDFET) 400 is illustrated, which includes a single semiconductor die 400c containing two back-to-back JBSFETs 400a, 400b, which correspond dosely to the JBSFET-1 and JBSFET-2 devices within the monolithic bidirectional SiC AC switch of FIG. 5B of the U.S. Patent No. 10,804,393 to Baliga, the disclosure of which is hereby incorporated herein by reference. However, as shown by FIG. 4A, each of the JBSFETs 400a, 400b includes a respective pair of gate pads G1 (2×) and G2 (2×), and with each gate pad within a pair (G1 or G2) being located on opposing sides of the semiconductor die 400c.
[0046] Moreover, each of the JBSFETs 400a, 400b within the BiDFET 400 includes a dedicated temperature sensing pad T.sub.S1, T.sub.S2 (see, e.g., T.sub.S2 in FIG. 3A), which is electrically coupled to a current carrying terminal of a corresponding temperature sensing resistor (see, e.g., resistor 32 in FIG. 3A). Moreover, as highlighted by the enlarged view of FIG. 4B, the first temperature sensing pad T.sub.S1 of the first JBSFET 400a may be electrically coupled by a nominally 100Ω silicided polysilicon resistor 410 (e.g., L.sub.Sense≈30 squares) to a corresponding source terminal/metal of the first JBSFET1 400a. Likewise, the second temperature sensing pad T.sub.S2 may be electrically coupled by a nominally 100Ω silicided polysilicon resistor (not shown) to a corresponding source terminal/metal 402 of the second JBSFET2 400b (see, e.g., T.sub.S1 in FIG. 3A). Accordingly, only one additional wire bond and pin is required, per JBSFET, to support temperature monitoring of a packaged BiDFET 400. The use of silicided polysilicon resistors on opposite sides of a packaged BiDFET 400 (i.e., opposite sides of a die) also enables independent temperature measurement of each JBSFET1 400a, JBSFET2 400b; this can be important because the respective on-off duty cycles of the dual-JBSFET devices within the BiDFET 400 may be different, and thereby lead to different thermal stresses within each JBSFET device, which require independent monitoring.
[0047] Referring now to FIG. 5, a composite, eight-terminal, packaged SiC/Si BiDFET 500 is illustrated, which includes a SiC BiDFET 400, such as disclosed by FIGS. 4A-4B, and a pair of Si enhancement-mode MOSFETs 502a, 502b, which are electrically connected in series with respective source terminals (S) of corresponding JBSFETs 400a, 400b within the SiC BiDFET 400, as shown. The six terminals of the packaged BiDFET 500 include two gate/control terminals (G.sub.1, G.sub.2), two current carrying terminals (T.sub.1, T.sub.2), two monitoring terminals (V.sub.SENSE1, V.sub.SENSE2), and two user-programmable, DC-voltage, gate terminals (G.sub.3, G.sub.4).
[0048] In addition, each paired and series combination of a Si enhancement-mode MOSFET and SiC MOSFET within the composite BiDFET 500 corresponds to the composite power device 1100a illustrated at FIG. 11A of the aforementioned U.S. application Ser. No. 17/418,309, filed Jun. 25, 2021, which is hereby incorporated herein by reference. As disclosed by the '309 application, each of the Si enhancement-mode MOSFETs 502a, 502b and corresponding monitoring terminals V.sub.SENSE1, V.sub.SENSE2 supports short-circuit protection of the composite BiDFET 500, by using the MOSFETs 502a, 502b as saturation current clamps, that improve (i.e., increase) the short-circuit withstand time characteristic of the BiDFET 500; this short-circuit withstand time characteristic may be adjusted by modifying the DC-voltages applied to the gate terminals G.sub.3, G.sub.4. Moreover, although not shown, a pair of the silicided polysilicon temperature sensors 22b of FIG. 2B may be used within the SiC BiDFET 400, as described hereinabove with respect to FIGS. 4A-4B.
[0049] In the drawings and specification, there have been disclosed typical preferred embodiments of the invention and, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being set forth in the following claims.
