Structure for radio-frequency applications

Abstract

A structure for radiofrequency applications includes: a support substrate of high-resistivity silicon comprising a lower part and an upper part having undergone a p-type doping to a depth D; a mesoporous trapping layer of silicon formed in the doped upper part of the support substrate. The depth D is less than 1 micron and the trapping layer has a porosity rate of between 20% and 60%.

Claims

1. A structure for radiofrequency applications comprising: a support substrate of high-resistivity silicon comprising a non-doped lower part and a p-type doped upper part, the .[.p-typed.]. .Iadd.p-type .Iaddend.doped upper part formed to a depth D of less than 1 .[.micro.]. .Iadd.micron .Iaddend.in the support substrate; and a mesoporous trapping layer of silicon formed in the p-type doped upper part of the support substrate, the mesoporous trapping layer having a porosity rate of between 20% and 60% such that the mesoporous trapping layer traps inversion charges susceptible to be generated in the non-doped lower part and the non-doped lower part retains a high and stable resistivity level.

2. The structure of claim 1, wherein the mesoporous trapping layer has pores with a diameter of between 2 nm and 50 nm.

3. The structure of claim 2, wherein the resistivity of the non-doped lower part of the support substrate is greater than 1000 ohm.Math.cm.

4. The structure of claim 1, wherein an active layer is disposed over the mesoporous trapping layer.

5. The structure of claim 4, wherein the active layer .[.compromises.]. .Iadd.comprises .Iaddend.a semiconductive material.

6. The structure of claim 4, wherein the active layer .[.compromises.]. .Iadd.comprises .Iaddend.a piezoelectric material.

7. The structure of claim 4, wherein the active layer comprises at least one material selected from the group consisting of: silicon, silicon carbide, silicon germanium, lithium niobate, lithium tantalate, quartz, and aluminum nitride.

8. The structure of claim 4, wherein .[.the.]. .Iadd.a .Iaddend.thickness of the active layer is between 10 nm and 50 μm.

9. The structure of claim 4, wherein a dielectric layer is disposed between the mesoporous trapping layer and the active layer.

10. The structure of claim 9, wherein the dielectric layer comprises at least one material selected from the group consisting of: silicon dioxide, silicon nitride, and aluminum oxide.

11. The structure of claim 10, wherein the dielectric layer is between 10 nm and 6 μm.

12. The structure of claim 4, wherein at least one microelectronic device is present on or in the active layer, the microelectronic device being a switching circuit or an antenna tuning circuit or a radiofrequency power amplification circuit.

13. The structure of claim 4, wherein at least one microelectronic device is present on or in the active layer, the microelectronic device comprising a plurality of active components and a plurality of passive components.

14. The structure of claim 4, wherein at least one microelectronic device is present on or in the active layer, the microelectronic device comprising at least one control element and one MEMS switching element comprising a microswitch with ohmic contact or a capacitive microswitch.

15. The structure of claim 4, wherein at least one microelectronic device is present on or in the active layer, the microelectronic device comprising a radiofrequency filter operating by bulk or surface acoustic wave propagation.

16. The structure of claim 1, wherein the resistivity of the non-doped lower part of the support substrate is greater than 1000 ohm.Math.cm.

17. The structure of claim 1, wherein an active layer is .[.arranged.]. .Iadd.disposed .Iaddend.on the mesoporous trapping layer.

18. The structure of claim 9, wherein the dielectric layer is between 10 nm and 6 μm.

.Iadd.19. A surface acoustic wave device, comprising: a support substrate of high-resistivity silicon comprising a lower portion and an upper portion, wherein silicon in the upper portion of the support substrate has been modified to form a charge trapping layer; a piezoelectric material bonded over a top surface of the support substrate, and having a thickness between 10 nm and 50 microns; and an electrode comb disposed on a surface of the piezoelectric material; wherein the charge trapping layer traps mobile charges generated in the upper portion of the support substrate in order to maintain a high and stable resistivity level in the upper portion of the support substrate. .Iaddend.

.Iadd.20. The surface acoustic wave device of claim 19, wherein the piezoelectric material comprises at least one material selected from the group consisting of: silicon, silicon carbide, silicon germanium, lithium niobate, lithium tantalate, quartz, and aluminum nitride. .Iaddend.

.Iadd.21. The surface acoustic wave device of claim 20, wherein the piezoelectric material is lithium tantalate. .Iaddend.

.Iadd.22. The surface acoustic wave device of claim 21, wherein the lithium tantalate has a thickness between 200 nm and 20 μm. .Iaddend.

.Iadd.23. The surface acoustic wave device of claim 19, wherein the charge trapping layer has a thickness below 1 μm. .Iaddend.

.Iadd.24. The surface acoustic wave device of claim 19, wherein the charge trapping layer comprises high-resistivity silicon having p-type doping. .Iaddend.

.Iadd.25. The surface acoustic wave device of claim 19, wherein the charge trapping layer comprises high-resistivity silicon having a porous layer. .Iaddend.

.Iadd.26. The surface acoustic wave device of claim 25, wherein the porous layer comprises pores having a pore diameter less than 50 nm. .Iaddend.

.Iadd.27. The surface acoustic wave device of claim 25, wherein the porous layer comprises pores having a pore diameter between 2 nm and 50 nm. .Iaddend.

.Iadd.28. The surface acoustic wave device of claim 25, wherein the porous layer comprises pores having a pore diameter greater than 2 nm. .Iaddend.

.Iadd.29. The surface acoustic wave device of claim 19, wherein at least one microelectronic device is present on or in the piezoelectric material. .Iaddend.

.Iadd.30. The surface acoustic wave device of claim 29, wherein the at least one microelectronic device comprises at least one component selected from the group consisting of: a switching circuit, an antenna tuning circuit, and a radiofrequency power amplification circuit. .Iaddend.

.Iadd.31. The surface acoustic wave device of claim 19, further comprising a dielectric disposed between the piezoelectric material and the charge trapping layer. .Iaddend.

.Iadd.32. The surface acoustic wave device of claim 31, wherein the dielectric comprises silicon oxide. .Iaddend.

.Iadd.33. The surface acoustic wave device of claim 19, wherein a resistivity of the support substrate is greater than 4000 ohm-cm. .Iaddend.

.Iadd.34. A surface acoustic wave device, comprising: a high-resistivity silicon support substrate; a charge trapping material disposed on the support substrate; a dielectric material disposed on the charge trapping material; a piezoelectric material disposed on the dielectric material and having a thickness between 10 nm and 50 microns; and electrode comb elements configured to propagate an acoustic wave between them, and disposed on a surface of the piezoelectric material; wherein the charge trapping layer is configured to trap mobile charges generated in a portion of the support substrate during operation of the surface acoustic wave device. .Iaddend.

.Iadd.35. The surface acoustic wave device of claim 34, wherein the piezoelectric material is lithium tantalate. .Iaddend.

.Iadd.36. The surface acoustic wave device of claim 34, wherein the dielectric material has a thickness between 10 nm and 6 μm. .Iaddend.

.Iadd.37. A method of manufacturing a surface acoustic wave device, comprising: providing a support substrate; modifying a top portion of the support substrate to form a charge trapping layer, the charge trapping layer configured to trap mobile charges generated in a portion of the support substrate during operation of the surface acoustic wave device; disposing a dielectric layer on the charge trapping layer; direct bonding a piezoelectric layer on the dielectric layer by disposing a donor substrate by molecular adhesion directly on the charge trapping layer, and thinning the donor substrate to a desired thickness of the piezoelectric layer of between 10 nm and 50 microns; and disposing an electrode comb on a surface of the piezoelectric material. .Iaddend.

.Iadd.38. The method of claim 37, wherein direct bonding the piezoelectric layer on the dielectric layer comprises direct bonding lithium tantalate on the dielectric layer. .Iaddend.

.Iadd.39. The method of claim 38, wherein direct bonding the lithium tantalate on the dielectric layer comprises direct bonding the lithium tantalate at a thickness between 200 nm and 20 μm on the dielectric layer. .Iaddend.

.Iadd.40. The method of claim 37, wherein modifying the top portion of the support substrate to form the charge trapping layer comprises rendering the top portion of the support substrate a porous layer. .Iaddend.

.Iadd.41. The method of claim 40, wherein rendering the top portion of the support substrate the porous layer comprises forming pores having a pore diameter between 2 nm and 50 nm. .Iaddend.

.Iadd.42. The method of claim 37, wherein the dielectric layer comprises at least one material selected from the group consisting of: silicon dioxide, silicon nitride, and aluminum oxide. .Iaddend.

.Iadd.43. The method of claim 37, wherein the dielectric layer is between 10 nm and 6 μm. .Iaddend.

.Iadd.44. The method of claim 37, further comprising disposing another dielectric layer on the piezoelectric layer before direct bonding the piezoelectric layer on the dielectric layer. .Iaddend.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Other features and advantages of the disclosure will emerge from the following detailed description with reference to the attached figures in which:

(2) FIG. 1 represents the dependency of the Young's modulus with the porosity of the silicon;

(3) FIG. 2 represents a first embodiment of the disclosure;

(4) FIGS. 3A and 3B represent a second embodiment of the disclosure; and

(5) FIG. 4 represents another embodiment of the disclosure.

DETAILED DESCRIPTION

(6) The structure 1, 1′, 11 for radiofrequency applications according to the disclosure comprises a support substrate 2 of high-resistivity (HR) silicon. High resistivity should be understood to mean a resistivity higher than 1000 ohm.Math.cm; it is advantageously between 4000 and 10,000 ohm.Math.cm.

(7) The support substrate 2 of HR silicon undergoes a p-type doping on an upper part 3 and to a predetermined depth D, less than 1 μm, in accordance with the disclosure. This doping can advantageously be performed by ion implantation followed by a bake of RTA type to activate the implanted p-type dopants, or an epitaxy of a p+ layer, or even a doping by “spin-on-glass” (the term describing a deposition of a layer of glass by centrifugation).

(8) Thus doped, the upper .[.layer.]. .Iadd.part .Iaddend.3 of the support substrate 2″ of HR silicon is subjected to a process of electrolysis, so as to transform the upper part 3 of the support substrate 2 into a porous .Iadd.trapping .Iaddend.layer 4, which will form the trapping layer 4. The depth D of the dopants introduced previously into the upper part 3 of the support substrate 2 corresponds substantially to the thickness of the trapping layer 4.

(9) The process of electrolysis can consist for example of an electrochemical anodization, in which at least the upper part 3 of the support substrate 2 is placed in a chamber comprising an electrolyte, such as hydrofluoric acid. An anode and a cathode are then dipped into the electrolyte and powered by a source of electrical current.

(10) There are three types of morphologies for porous silicon: macroporous silicon, generally obtained from weakly doped n-type silicon, and having a pore diameter greater than 50 nm; mesoporous silicon, generally obtained from strongly doped p-type silicon, and having a pore diameter of between 2 nm and 50 nm; nanoporous (also called microporous) silicon, generally obtained from weakly doped p-type silicon, and having a pore diameter of less than 2 nm.

(11) Thus, depending on the level of doping of the .Iadd.support .Iaddend.substrate 2 and the conditions of the electrolysis process, such as the adjustment of the electrical current density applied by the source of electrical current, the porosity rate will be higher or lower and controlled. To recap, the porosity Po of a layer is defined as the fraction of bulk unoccupied within the layer and is expressed as:
Po=(d−d.sub.Po)/d
where d is the density of the non-porous material and d.sub.Po is the density of the porous material.

(12) The trapping layer 4 generated has to have a porosity rate that is sufficient to obtain a high defect density, suitable for trapping the inversion charges generated in the support substrate 2, and a high resistivity level. However, this porosity rate, coupled with the thickness of the porous .Iadd.trapping .Iaddend.layer 4, also characterizes the mechanical strength of the trapping layer 4. The dependency of the Young's modulus (denoted E and expressed in GigaPascal) as a function of the porosity rate of the porous layer is represented in FIG. 1. For a given thickness, the greater the porosity rate, the lower the mechanical properties: the decrease in the Young's modulus as a function of the porosity percentage (Po) reflects this decrease in mechanical strength. Furthermore, for a given porosity rate, the thicker the porous layer, the lower the mechanical properties. The applicant has identified a process window for which the porous layer exhibits the mechanical strength required to be compatible with subsequent microelectronic steps (deposition, bakes, polishing, etc.), as well as the resistivity properties required for the radiofrequency applications.

(13) The structure 1, 1′, 11 according to the disclosure, therefore, proposes a trapping layer 4 with a porosity rate that is between 20% and 60% and with a thickness that is less than 1 μm, so as to ensure mechanical and electrical performance levels of the structure 1, 1′, 11. The mesoporous morphology, having pores with a diameter of between 2 nm and 50 nm, makes it possible to achieve the requisite porosity levels, over the thickness of 1 μm, with a significant trap density (typically greater than 10.sup.13/cm.sup.2, making it possible to trap the inversion charges) and a high resistivity.

(14) The thickness D of the trapping layer 4 (of mesoporous silicon) depends on the depth of the p-type doping of the upper part 3 of the support substrate 2. The porosity rate depends on the quantity of dopants introduced into the upper part 3 of the support substrate 2 as well as the electrolysis process performance conditions.

(15) In order to ensure that the porosification by electrolysis of the upper part 3 of the support substrate 2 does not exceed the predetermined depth D, a control of the voltage at the terminals of the electrolysis is put in place, making it possible to determine when the porosification begins in the non-doped lower part of the support substrate 2 of HR silicon and, therefore, stop the electrolysis process. The porosification of the upper part 3 of the support substrate 2 has to be stopped at the end of the diffusion tail of the dopants introduced into the upper part 3 of the .Iadd.support .Iaddend.substrate 2, substantially at the depth D.

(16) The structure 1, 1′, 11 for radiofrequency applications according to the disclosure thus comprises a trapping layer 4 of mesoporous silicon, the porosity of which is between 20% and 60% and the thickness of which is less than 1 μm, arranged on a support substrate 2 of high-resistivity silicon. The trapping layer has a typical resistivity greater than 5000 ohm.Math.cm.

(17) According to a first embodiment of the disclosure represented in FIG. 2, the structure 1 for radiofrequency applications can take the form of a wafer of dimensions compatible with microelectronic processes, for example, with a diameter of 200 nm or 300 nm, comprising the support substrate 2 and the trapping layer 4 (FIG. 2, Panel (c)).

(18) The support substrate 2 of HR silicon (FIG. 2, Panel (a)) advantageously has a resistivity greater than 4000 ohm.Math.cm. It first of all undergoes a boron ion implantation, for example, with a dose of 1.sup.e13/cm.sup.2 and with an energy of 50 keV, followed by a heat treatment at 1000° C. for 5 minutes; a p-doped upper part 3, to a depth of approximately 200 nm, is thus created (FIG. 2, Panel (b)). The support substrate 2 then undergoes an electrolysis: the current density will, for example, be between 10 and 20 mA/cm.sup.2 and the electrolysis solution will have an HF concentration of between 10% and 30%. The mesoporous trapping layer 4 of silicon is formed in the doped upper part 3 of the support substrate 2 (FIG. 2, Panel (c)). The porosity obtained, dependent on the quantity of dopants and on the current density applied during the electrolysis, is of the order of 50%; the pores having a size of between 2 and 50 nm. This fabrication process, simple and inexpensive, makes it possible to obtain a structure 1 that exhibits mechanical and electrical properties compatible with the specifications of radiofrequency applications: a good mechanical strength making it possible to withstand the various stressful steps of creation of microelectronic components; stable insulation properties linked to the high resistivity of the support substrate 2 and to the charge-trapping qualities of the mesoporous trapping layer 4, even after application of the high-temperature heat treatments for the creation of microelectronic components.

(19) A second embodiment of the disclosure is represented in FIG. 3. According to a first variant of this second embodiment, illustrated in FIG. 3, Panel (a), the structure 1′ for radiofrequency applications can take the form of a wafer and further comprise an active layer 5, arranged on the trapping layer 4, in and on which RF components will be able to be created. The active layer 5 will advantageously be able to consist of semiconductive materials and/or piezoelectric materials. Advantageously, but without this being limiting, the active layer 5 comprises at least one of the materials out of: silicon, silicon carbide, germanium silicon, lithium niobate, lithium tantalate, quartz, aluminum nitride, etc. The thickness of the active layer 5 can vary from a few nanometers (for example, 10 nm) to several tens of microns (for example, 50 μm) depending on the components to be fabricated.

(20) By way of example, the active layer 5 is transferred onto the support substrate 2 comprising the trapping layer 4, by one of the thin layer transfer processes well known to those skilled in the art, including: The SMART CUT® process, based on an implantation of light hydrogen and/or helium ions in a donor substrate and a bonding, for example, by molecular adhesion, of this donor substrate directly onto the trapping layer 4, itself arranged on the support substrate 2; a detachment step then makes it possible to separate a thin surface layer from the donor substrate (the active layer), at the level of the embrittlement plane defined by the depth of implantation of the ions. Finishing steps, that can include high-temperature heat treatments, finally confer the crystalline and surface quality required of the active layer 5. The process is particularly suited to the fabrication of thin active layers, with a thickness of between a few nanometers and approximately 1.5 μm, for example, for layers of silicon. The SMART CUT® process is followed by an epitaxy step, making it possible, in particular, to obtain thicker active layers, for example, from a few tens of nm to 20 μm. The direct bonding and mechanical, chemical and/or mechanical-chemical thinning processes involve assembling a donor substrate by molecular adhesion directly on the trapping layer 4, itself arranged on the support substrate 2, then in thinning the donor substrate to the desired thickness of active layer 5, for example, by grinding and by polishing (CMP, “chemical mechanical polishing”). These processes are particularly suited to the transfer of thick layers, for example, from a few microns to several tens of microns, and up to a few hundreds of microns.

(21) According to another variant of the second embodiment, represented in FIG. 3, Panel (b), the structure 1′ for radiofrequency applications will also be able to include a dielectric layer 6, arranged between the active layer 5 and the trapping layer 4. Advantageously, but without this being limiting, the dielectric layer 6 will comprise at least one of the materials out of: silicon dioxide, silicon nitride, aluminum oxide, etc. Its thickness will be able to vary between 10 nm and 3 μm.

(22) The dielectric layer 6 is obtained by thermal oxidation or by LPCVD or PECVD or HDP deposition, on the trapping layer 4 or on the donor substrate prior to the transfer of the active layer 5 onto the trapping layer 4.

(23) As is well known in the field of SOI (silicon-on-insulator) substrates for radiofrequency applications, such a dielectric layer, for example, formed by an oxide of silicon on a support substrate of silicon, comprises positive charges. These charges are compensated by negative charges coming from the support substrate at the interface with the dielectric layer. These charges generate a conduction layer in the support substrate, under the dielectric layer, with a resistivity that drops around 10-100 ohm.Math.cm. The electrical performance levels sensitive to the resistivity of the support substrate (such as the linearity of the signal, the level of insertion losses, the quality factors of the passive components, etc.) are, therefore, greatly degraded by the presence of this conduction layer.

(24) The role of the trapping layer 4 is then to trap all the mobile charges generated in the support substrate 2 in order for it to retain a high and stable resistivity level.

(25) FIG. 4 presents a third embodiment according to the disclosure. According to a first variant of this third embodiment, represented in FIG. 4, Panel (a), the structure 11 for radiofrequency applications can also comprise or consist of a microelectronic device 7 on or in the active layer 5, which is arranged on a dielectric layer 6 or directly on the trapping layer 4. The microelectronic device 7 can be a switching circuit (called “switch”) or an antenna tuning or synchronization circuit (called “tuner”) or even a power amplification circuit (called “power amplifier”), created according to silicon microelectronic technologies. The active layer 5 of silicon typically has a thickness of between 50 nm and 180 nm, for example, 145 nm, and the underlying dielectric layer 6 has a thickness of between 50 nm and 400 nm, for example, 200 nm; the trapping layer 4 is arranged between the dielectric layer 6 and the support substrate 2. The microelectronic device 7 created in and on the active layer 5 comprises a plurality of active components (MOS or bipolar type, or the like) and a plurality of passive components (of capacitor, inductor, resistor, resonator, filter type, or the like).

(26) The fabrication of the microelectronic components entails carrying out several steps including high-temperature heat treatments, typically at 950° C.-1100° C., or even higher. The trapping layer 4 of mesoporous silicon described previously retains its physical and electrical properties after such heat treatments.

(27) According to another variant of this embodiment, represented in FIG. 4, Panel (b), the microelectronic device 7 can first of all be created on a substrate of SOI (silicon-on-insulator) type, then transferred by a layer transfer technique known to those skilled in the art onto a structure 1 according to the disclosure comprising the trapping layer 4 arranged on the support substrate 2.

(28) In this particular case, the structure 11 comprises, on the one hand, the support substrate 2 on which the trapping layer 4 is arranged; above the latter, there is the layer of components of the microelectronic device 7: the so-called “back end” part of metal interconnect and dielectric layers is arranged above the trapping layer 4, the so-called “front end” part (silicon), generated partly in the active layer 5, being itself above the “back end” part. Finally, above, there is the active layer 5 and, optionally, a dielectric layer 6′.

(29) In these two particular cases, the electromagnetic fields, deriving from the high-frequency signals intended to be propagated in the .Iadd.microelectronic .Iaddend.devices 7, and which will penetrate into the trapping layer 4 and into the support substrate 2, will undergo only low losses (insertion losses) and disturbances (cross-talk, harmonics), because of the high and stable resistivity of the support substrate 2 and of the trapping layer 4. Advantageously, the structure 11 according to the disclosure benefits from a process of fabrication of the trapping layer 4 that is simple and economical compared to the prior art; and it offers at least equivalent performance levels.

(30) According to a fourth embodiment, the structure 11 for radiofrequency applications can comprise or consist of a microelectronic device 7 comprising at least one control element and one MEMS (microelectromechanical system) switching element consisting of a microswitch with ohmic contact or of a capacitive microswitch.

(31) The MEMS fabrication can be facilitated by the presence of a dielectric layer under an active layer of silicon. The structure 11 according to the disclosure will, therefore, be able to include, by way of example, an active layer 5 of silicon with a thickness of between 20 nm and 2 microns, advantageously 145 nm, and an underlying dielectric layer 6 with a thickness of between 20 nm and 1 micron, advantageously 400 nm; the trapping layer 4 is arranged between the dielectric layer 6 and the support substrate 2. The fabrication of the MEMS part is then based on surface micromachining techniques, making it possible, in particular, to free beams or mobile membranes in the active layer of silicon.

(32) Alternatively, the MEMS part can be created directly on the trapping layer 4, by successive deposition of a plurality of layers (including an electrode, a dielectric, a sacrificial layer, and an active layer) and by the production of patterns on these different layers.

(33) The microelectronic processes for the fabrication of the control element(s) (CMOS, for example), usually performed before the MEMS part, require, as in the preceding embodiment, the application of high-temperature heat treatments. The mechanical strength of the trapping layer 4 to this type of treatment and its capacity to retain its electrical properties (high resistivity and trap density suitable for trapping the mobile charges) are, therefore, key advantages.

(34) In the same way as for the third embodiment, the high-frequency signals propagated in this .Iadd.microelectronic .Iaddend.device 7 generate electromagnetic fields that penetrate into the trapping layer 4 and into the support substrate 2. The losses (insertion losses), distortions (harmonics) and disturbances (cross-talk, etc.) will be lesser because of the high and stable resistivity of the support substrate 2 provided with the trapping layer 4.

(35) According to a fifth embodiment, the structure 11 for radiofrequency applications can comprise or consist of a microelectronic device 7 comprising a radiofrequency filter operating by bulk acoustic wave (BAW) propagation.

(36) The fabrication of a BAW filter of FBAR (thin-film bulk acoustic resonator) type necessitates an active layer 5 consisting of a piezoelectric material, in which the acoustic wave will be contained between the two electrodes that surround it. The structure 11 according to the disclosure will, therefore, be able to include, by way of example, an active layer 5 of aluminum nitride with a thickness of between 50 nm and 1 μm, advantageously 100 nm, and a dielectric layer 6 (for example, of silicon oxide) with a thickness of between 1 and 6 μm; the trapping layer 4 is arranged between the dielectric layer 6 and the support substrate 2. Insulation cavities are formed under the active layers of the filter, that is to say, the areas in which the acoustic waves will be required to be propagated.

(37) The fabrication of the BAW filter then entails steps of depositions of electrodes to which the RF signal will be applied.

(38) The structure 11 according to the disclosure makes it possible on the one hand to limit the depth of the insulation cavities whose insulation function relative to the substrate is made less critical by the high and stable resistivity of the support substrate and of the trapping layer; this is an advantage in terms of simplification, flexibility and robustness in the process of fabrication of these devices. Also, the structure 11 according to the disclosure makes it possible to obtain better performance levels in the filters, notably in terms of linearity.

(39) According to a variant of this fifth embodiment, the microelectronic device 7 comprises a radiofrequency filter operating by surface acoustic wave (SAW) propagation.

(40) The fabrication of an SAW filter requires an active layer 5 consisting of a piezoelectric material, on the surface of which will be created an electrode comb: the acoustic wave is intended to be propagated between these electrodes. The structure 11 according to the disclosure will, therefore, be able to include, by way of example, an active layer 5 of lithium tantalate with a thickness of between 200 nm and 20 μm, advantageously 0.6 μm; the trapping layer 4 is arranged between the active layer 5 and the support substrate 2. A dielectric layer 6 can optionally be added between the active layer 5 and the trapping layer 4.

(41) The structure 11 according to the disclosure makes it possible to obtain better filter performance levels, notably in terms of insertion losses and of linearity.

(42) The structure 1, 1′, 11 for radiofrequency applications according to the disclosure is not limited to the embodiments cited above. It is suited to any application for which high-frequency signals propagate and are likely to undergo undesirable losses or disturbances in a support substrate, because the physical and electrical characteristics of the trapping layer 4 arranged on the support substrate 2 confer good RF properties on the assembly (limiting the losses, nonlinearities and other disturbances).