DUAL-OPERATION DEPLETION/ENHANCEMENT MODE HIGH ELECTRON MOBILITY TRANSISTOR

Abstract

The present invention is a FET having a p-doped or acceptor-doped layer underneath a FET channel to enable E/D Mode operation. A FET threshold voltage is tunable through a voltage applied to the p-doped layer via a metal contact such as a threshold-control terminal (TCT). The present invention has a dual E/D mode operation of a single FET device, and also a dual E/D mode operation with a single-polarity positive power supply voltage. The FET of the present invention is fabricated to enable dual enhancement-mode/depletion-mode (E-Mode/D-Mode) high electron mobility transistors (HEMTs), to enable dual E/D Mode operation by incorporating a p-doped or acceptor doped region underneath the channel, to achieve a tunable threshold voltage by varying the bias voltage on a fourth terminal called the threshold-control terminal (TCT) that contacts the p-doped layer, and to enable Dual E/D-Mode operation of a HEMT with a single-polarity positive power supply voltage.

Claims

1. A field-effect transistor (FET) comprising: a substrate; a back barrier disposed on the substrate; a middle barrier disposed above the back barrier, wherein at least one pulse-doping layer is disposed within the middle barrier; a channel disposed on the middle barrier; and a front barrier disposed on the channel.

2. The FET of claim 1, further comprising: a threshold-control terminal (TCT) access layer disposed between the middle barrier and the back barrier, wherein a voltage applied to the TCT access layer tunes a threshold voltage of the FET.

3. The FET of claim 2, further comprising: a front hole-blocker layer disposed between the middle barrier and the TCT access layer.

4. The FET of claim 2, further comprising: a spacer layer disposed between the middle barrier and the TCT access layer.

5. The FET of claim 1, further comprising: a back hole-blocker layer disposed between the back barrier and the TCT access layer.

6. The FET of claim 1, further comprising: a spacer layer disposed between the back barrier and the TCT access layer.

7. The FET of claim 1, wherein the front barrier includes at least one pulse-doping layer disposed therein.

8. The FET of claim 1, further comprising: a substrate contact upon which the substrate is disposed.

9. The FET of claim 1, further comprising: at least one counter-doped layer disposed between the channel and the middle barrier for modifying a threshold voltage of the FET.

10. The FET of claim 9, wherein the carriers of electrical current are electron holes.

11. The FET of claim 9, further comprising: an n-doped threshold-control terminal (TCT) access layer disposed between the middle barrier and the back barrier, wherein a voltage applied to the TCT access layer tunes the threshold voltage of the FET.

12. The FET of claim 1, wherein the channel is a doped channel which is depleted.

13. The FET of claim 12, further comprising: a source terminal; and a drain terminal; wherein the channel is depleted by applying a voltage opposite in polarity to the ionized impurities serving as the dopants of the doped channel.

14. The FET of claim 13, wherein the FET is selected from a hetero-junction FET (HFET), a junction gate FET (JFET), and a metal-semiconductor FET (MESFET).

15. The FET of claim 1, further comprising: a p-doped threshold-control terminal (TCT) access layer; a spacer layer; and a hole-blocking layer; wherein at least one of the p-doped TCT access layer, the spacer layer, the hole-blocking layer, the channel, the front barrier, the middle barrier, and the back barrier is composed of a compound selected from (In)GaAs, (In)GaP, (Ga)AlAs, (Al)InAs, (In)GaN or (Ga)AlN.

16. The FET of claim 1, wherein the substrate is composed of a compound selected from GaAs, InP, GaN, Si, SiC or Al.sub.2O.sub.3.

17. A field-effect transistor (FET) comprising: a substrate; a back barrier disposed on the substrate; a threshold-control terminal (TCT) access layer disposed above the back barrier, wherein a voltage applied to the TCT access layer tunes a threshold voltage of the FET; a middle barrier disposed above the TCT access layer, wherein at least one pulse-doping layer is disposed within the middle barrier; a channel disposed on the middle barrier; a front barrier disposed on the channel; and a gate disposed on the front barrier.

18. The FET of claim 17, wherein the TCT access layer is p-doped.

19. The FET of claim 17, further comprising: a TCT contact disposed on the TCT access layer.

20. A method for fabricating a field-effect transistor (FET) comprising: providing a substrate; disposing a back barrier on the substrate; disposing a threshold-control terminal (TCT) access layer above the back barrier; disposing a middle barrier above the TCT access layer; disposing at least one pulse-doping layer within the middle barrier; disposing a channel on the middle barrier; disposing a front barrier on the channel; disposing the FET on a mesa; disposing a TCT contact on the TCT access layer; and applying a voltage to the TCT access layer, thereby tuning a threshold voltage of the FET.

21. The method of fabrication of the FET of claim 20, wherein the FET is composed of a plurality of FETs served by the same TCT contact.

Description

BRIEF DESCRIPTION OF DRAWINGS

[0024] The foregoing summary, as well as the following detailed description of presently preferred embodiments of the invention, will be better understood when read in conjunction with the appended drawings. For the purpose of illustrating the invention, there are shown in the drawings embodiments which are presently preferred. It should be understood, however, that the invention is not limited to the precise arrangements and instrumentalities shown. In addition, some of the figures are provided further details including exemplary dimensions which are in units of inches.

[0025] In the drawings:

[0026] FIG. 1a illustrates a FET in the prior art;

[0027] FIGS. 1b-1c illustrate conduction band profiles across the FET of FIG. 1a;

[0028] FIG. 1d illustrates a conduction band profile through the center of the FET of FIG. 1a;

[0029] FIG. 1e illustrates a material composition profile through the center of the FET of FIG. 1a;

[0030] FIG. 2 illustrates a FET with front and back barriers with pulse doping;

[0031] FIG. 3a illustrates an I.sub.D vs. V.sub.GS chart for a depletion-mode HEMT;

[0032] FIG. 3c illustrates an I.sub.D vs. V.sub.GS chart for an enhancement-mode HEMT;

[0033] FIG. 4 illustrates an FET of the present invention having a middle barrier;

[0034] FIG. 5a illustrates an HEMT of the present invention with a mesa;

[0035] FIG. 5b illustrates a variant of the HEMT of FIG. 5a;

[0036] FIG. 6a illustrates an energy band diagram of the FET of FIG. 4; and

[0037] FIG. 6b illustrates a chart of a dual D/E-Mode operation of the FET of FIG. 4.

[0038] To facilitate an understanding of the invention, identical reference numerals have been used, when appropriate, to designate the same or similar elements that are common to the figures. Further, unless stated otherwise, the features shown in the figures are not drawn to scale, but are shown for illustrative purposes only.

DETAILED DESCRIPTION

[0039] Certain terminology is used in the following description for convenience only and is not limiting. The article a is intended to include one or more items, and where only one item is intended the term one or similar language is used. Additionally, to assist in the description of the present invention, words such as top, bottom, side, upper, lower, front, rear, inner, outer, right and left are used to describe the accompanying figures. The terminology includes the words above specifically mentioned, derivatives thereof, and words of similar import.

[0040] As illustrated in FIG. 4, the present invention is a HEMT 40 with a TCT-contacting p-doped layer 42. Referring to FIG. 4, a gate 44 is disposed on a front barrier 46, which in turn is disposed on a channel 48. The channel 48 is disposed on a middle barrier 50, which is disposed on the p-doped layer 42. The p-doped layer 42 is disposed on a back barrier 52, which in turn is disposed on a substrate 54. The middle barrier 50 includes at least one pulse doping layer 56, 58. The front barrier 46 may optionally include a pulse doping layer 60. An optional front hole-blocker 62 and/or an optional first undoped spacer 64 may be included between the middle barrier 50 and the TCT-contacting p-doped layer 42. Similarly, an optional back hole-blocker 66 and/or an optional second undoped spacer 68 may be included between the TCT-contacting p-doped layer 42 and the back barrier 52. In addition, a substrate contact 70 may optionally be included under the substrate 54.

[0041] In an alternative embodiment, the back barrier 52 may optionally be pulse-doped, which will further reduce hole injection into the substrate 54. If the TCT-access layer 42 is p-doped, then the pulse-doped back barrier 52 is n-doped. Alternatively, if the TCT-access layer 42 is n-doped, then the pulse-doped back barrier 52 is p-doped.

[0042] In an example embodiment, the front barrier 46 is composed of AlGaAs, the channel 48 is composed of (In)GaAs, the middle barrier 50 is composed of AlGaAs, the optional front hole-blocker 62 is composed of AlAs, the optional first undoped spacer 64 is composed of (In)GaAs, the TCT-access p-doped layer 42 is also composed of (In)GaAs, the optional second spacer 68 is also composed of (In)GaAs, the optional back hole-blocker 66 is composed of AlAs, the back barrier 52 is composed of AlGaAs, and the substrate 54 is composed of GaAs. However, other alternative embodiments may use different materials, instead of (In)(Al)GaAs layers on GaAs substrates as described herein. The FETs of the present invention do not depend on any special properties of (In)(Al)GaAs not present in other compound semiconductors or alloys, nor on any specific properties of GaAs as a substrate.

[0043] FIG. 6a shows the conduction band energy diagram with 1 volt on the TCT in the top diagram, and 0 volt on the TCT in the bottom diagram for the HEMT 40 in FIG. 4. In both cases in FIG. 6a, the channel 48 is kept at 0 volt. In many cases, the p-doped layer 42 would be between about 20 nm and about 2 microns in thickness, and is disposed on the substrate 54. With 0 volt on the TCT, it is seen that the p-doped layer 42 (which is depleted of holes resulting in a net fixed, immobile negative charge) pulls the conduction band in the channel up and away from the Fermi level of the TCT, as in the bottom diagram in FIG. 6a. This causes the electron concentration in the channel to fall too low for the channel 48 to serve as a conductive path from source to drain. It can also be thought of as the immobile negative charges repelling electrons away from the channel 48. Thus with 0 volt on the TCT, applying zero volts on the gate, turns the device OFF; in other words, the FET 40 operates in E-Mode.

[0044] Referring again to FIG. 6a, with 1 volt on the TCT, the p-doped layer 42 gets less depleted of holes, resulting in too few negative immobile charges to sustain sufficient repulsion of channel electrons. In the alternative band diagram view in the top diagram of FIG. 6a, the conduction band-edge in the channel 48 gets pulled down towards and below the Fermi level. This causes the electron concentration in the channel 48 to increase, thus enabling the channel 48 to serve as a conductive path from source to drain. Thus with 1 volt on the TCT, just 0 volt on the gate is enough to turn the device ON; in other words, the FET 40 operates in D-Mode.

[0045] FIG. 6b shows the I.sub.D vs V.sub.GS characteristics of the FET 40 at 0 volt and 1 volt on the TCT, showing a clear transition from E-Mode to D-Mode operation. The operation of the TCT is not discrete, or digital, and so the TCT voltage can be continuously tuned to achieve the desired threshold voltage of the FET 40, be it strongly E-Mode, be it strongly D-Mode, or be it somewhere in-between, as dictated by the needs of the application circuit.

[0046] One issue with biasing a p-type region with a positive voltage is that such biasing would inject holes into the surrounding layers, either into the channel or into the substrate, causing parasitic drain current, noise, and back-gating by modulation of any interface trap charges. Referring to FIG. 4, the example FET 40 is fabricated in order to prevent hole injection from the p-doped layer 42, by surrounding the layer 42 on both sides by AlGaAs barriers as the middle barrier 50 and the back barrier 52. Even higher TCT voltages may be achieved by using a wide band-gap material such as AlAs on either side of the p-doped channel 48, which offers an even larger barrier, for example, up to about 2 eV, for holes to surmount if the holes are to cross over into the valence bands of adjacent layers. These hole-blocking layers 62, 66 shown in FIG. 4 on either side of the p-doped layer 42 would range in thickness from about 2 nm to about 20 nm.

[0047] Additional undoped spacers 64, 68 around the p-doped region, as shown in FIG. 4, may be used to further tailor the threshold voltage as a function of TCT voltage, and to provide etch-stops for easier fabrication of TCT contacts.

[0048] The present invention is also directed to a method of fabrication of a TCT-FET. FIGS. 5a-5b shows schematics of alternative devices 80, 90, respectively, fabricated based on the structure of FIG. 4, with the p-doped region 42 contacted by a metal to form TCT contacts 82, 92, respectively. Standard photolithography, wet or dry chemical etching, and/or metallization processes may be used to form these TCT contacts 82, 92. FIG. 5a illustrates a FET 80 which features a TCT contact 82 fabricated on a separate mesa 84 for each individual device 86. As described herein, an optional pulse doping layer 88 is disposed in a front barrier of the device 86. FIG. 5b illustrates a FET 90 which features a universal TCT contact 92 for all devices 94, 96, 98 combined.

[0049] With an appropriate choice of materials, dimensions and fabrication processes, the inventive devices 80, 90 in FIGS. 5a-5b, respectively, may be expected to yield a threshold voltage tunable between about 2 to about +2 volt, using about 0 to about +10 volt applied to the TCT contacts 82, 92, respectively.

[0050] In the preferred embodiment, the threshold voltage is tunable between a lower value ranging from about 0.5 to about 0.1 volt, and an upper value ranging from about +0.1 to about +0.7 volt, using about 0 to about +1 volt applied to the TCT contacts 82, 92. This would enable dual E/D Mode operation on a single FET with a single-polarity (positive-only) power supply.

[0051] In alternative embodiments, the present invention includes different flavors of FETs apart from HEMTs. In one alternative embodiment, counter-doped layers are disposed underneath the channel that modify the threshold voltage in hole-channel (p-channel) FETs when the carriers of electrical current are holes rather than electrons. The TCT access layer would then be n-doped.

[0052] In another alternative embodiment, doped TCT-access layers are disposed underneath the channel that enable tunability of the threshold voltage in FETs that deplete a doped channel, i.e. a pre-existing bridge between the source and drain, by applying a voltage opposite in polarity to the ionized impurities (dopants). These include Hetero-Junction FETs (HFET), a junction gate FET (JFET) and Metal-Semiconductor FETs (MESFETs).

[0053] Further alternative embodiments include FETs in which the various layers, including the p-doped layer, the spacers, the hole-blocking layers, the channel, the barriers are composed of (In)GaAs, (In)GaP, (Ga)AlAs, (Al)InAs, (In)GaN or (Ga)AlN compounds or alloy materials disposed on GaAs, InP, GaN, Si, SiC or Al.sub.2O.sub.3 substrates.

[0054] Other alternative embodiments may have a uniformly doped layer in the place of any pulse-doping layer, with the uniformly doped layer having the same polarity as the pulse-doping layer which is replaced. For example, if the front barrier 46 includes an n-doped pulse-doping layer, such an n-doped pulse-doping layer 60, then the pulse-doping layer 60 may be replaced with an n-doped uniformly doped layer.

[0055] The present invention may be embodied in other specific forms without departing from its spirit or essential characteristics. The described embodiments are to be considered in all respects only as illustrative and not restrictive. The scope of the invention, therefore, will be indicated by claims rather than by the foregoing description. All changes, which come within the meaning and range of equivalency of the claims, are to be embraced within their scope.