Power module substrate

Abstract

A power module substrate of the present invention includes a ceramic substrate and a circuit layer having a circuit pattern. In an interface between the circuit layer and the ceramic substrate, a CuSn layer and a Ti-containing layer are laminated in this order from the ceramic substrate side. In a cross-sectional shape of an end portion of the circuit pattern of the circuit layer, an angle formed between a surface of the ceramic substrate and an end face of the CuSn layer is set in a range equal to or greater than 80 and equal to or smaller than 100, and a maximum protrusion length L of the CuSn layer or the Ti-containing layer from an end face of the circuit layer is set in a range equal to or greater than 2m and equal to or smaller than 15 m.

Claims

1. A power module substrate comprising: a ceramic substrate; and a circuit layer which is formed on one surface of the ceramic substrate and has a circuit pattern, wherein the circuit layer is made of Cu or a Cu alloy, in an interface between the circuit layer and the ceramic substrate, a CuSn layer in which Sn forms a solid solution in Cu and a Ti-containing layer containing Ti are laminated in this order from the ceramic substrate side, and in a cross-sectional shape of an end portion of the circuit pattern of the circuit layer, an angle formed between a surface of the ceramic substrate and an end face of the CuSn layer is set in a range equal to or greater than 80 and equal to or smaller than 100, and a maximum protrusion length L of the CuSn layer or the Ti-containing layer from an end face of the circuit layer is set in a range equal to or greater than 2 m and equal to or smaller than 15 m.

2. The power module substrate according to claim 1, wherein in the cross-sectional shape of the end portion of the circuit pattern of the circuit layer, an end face of the Ti-containing layer is positioned on an extended plane of the end face of the CuSn layer.

Description

BRIEF DESCRIPTION OF DRAWINGS

(1) FIG. 1 is a view schematically describing a power module in which a power module substrate according to an embodiment of the present invention is used.

(2) FIG. 2 is a cross-sectional view schematically describing a bonded interface between a circuit layer and a ceramic substrate in the power module substrate shown in FIG. 1.

(3) FIG. 3 shows views schematically describing specific examples of a cross-sectional shape of an end portion of a circuit pattern formed in the circuit layer of the power module substrate shown in FIG. 1, and shows images obtained by SEM observation.

(4) FIG. 4 shows views schematically describing specific examples of the cross-sectional shape of the end portion of the circuit pattern formed in the circuit layer of the power module substrate shown in FIG. 1.

(5) FIG. 5 is a flowchart of a method for manufacturing a power module substrate according to an embodiment of the present invention and a method for manufacturing a power module.

(6) FIG. 6 is a view schematically describing a method for manufacturing a power module substrate according to an embodiment of the present invention.

(7) FIG. 7 is a view schematically describing a method for manufacturing a power module according to an embodiment of the present invention.

(8) FIG. 8 is a view schematically describing a power module in which a power module substrate according to another embodiment of the present invention is used.

DESCRIPTION OF EMBODIMENTS

(9) Hereinafter, embodiments of the present invention will be described with reference to the attached drawings. In the following description, brazing filler material is not limited to materials containing lead.

(10) FIG. 1 shows a power module 1 including a power module substrate 10 according to the present embodiment.

(11) The power module 1 includes the power module substrate 10 provided with a circuit layer 12 and a metal layer 13, a semiconductor element 3 bonded to one surface (upper surface in FIG. 1) of the circuit layer 12 through a bonding layer 2, and a heat sink 30 bonded to the other side (lower side in FIG. 1) of the power module substrate 10 through a bonding layer 32.

(12) As shown in FIG. 1, the power module substrate 10 includes a ceramic substrate 11, the circuit layer 12 provided on one surface (upper surface in FIG. 1) of the ceramic substrate 11, and the metal layer 13 provided on the other surface (lower surface in FIG. 1) of the ceramic substrate 11.

(13) The ceramic substrate 11 is constituted with ceramics such as aluminum nitride (AlN), silicon nitride (Si.sub.3N.sub.4), and alumina (Al.sub.2O.sub.3) having high insulating properties. In the present embodiment, the ceramic substrate 11 is constituted with aluminum nitride (AlN) having excellent heat radiation properties. The thickness of the ceramic substrate 11 is set within a range of 0.2 to 1.5 mm. In the present embodiment, the thickness of the ceramic substrate 11 is set to be 0.635 mm.

(14) The circuit layer 12 is formed by bonding a Cu foil 22 formed of Cu or a Cu alloy having conductivity to one surface of the ceramic substrate 11.

(15) In the present embodiment, as shown in FIG. 6, the circuit layer 12 is formed by laminating a CuPSn-based brazing filler material 24, a Ti material 25, and the Cu foil 22 formed of oxygen-free copper on one surface of the ceramic substrate 11 and performing heating such that the Cu foil 22 is bonded to the ceramic substrate 11. In the present embodiment, as the CuPSn-based brazing filler material 24, a CuPSnNi brazing filler material is used.

(16) The thickness of the circuit layer 12 is set within a range equal to or greater than 0.1 mm and equal to or smaller than 1.0 mm. In the present embodiment, the thickness of the circuit layer 12 is set to be 0.3 mm.

(17) The metal layer 13 is formed by bonding a Cu foil 23 formed of Cu or a Cu alloy to the other surface of the ceramic substrate 11 through the CuPSn-based brazing filler material 24. In the present embodiment, as shown in FIG. 6, the metal layer 13 is formed by laminating the CuPSn-based brazing filler material 24, the Ti material 25, and the Cu foil 23 formed of oxygen-free copper on the other surface of the ceramic substrate 11 and performing a heat treatment such that the Cu foil 23 is bonded to the ceramic substrate 11. In the present embodiment, as the CuPSn-based brazing filler material 24, a CuPSnNi brazing filler material is used.

(18) The thickness of the metal layer 13 is set within a range equal to or greater than 0.1 mm and equal to or smaller than 1.0 mm. In the present embodiment, the thickness of the metal layer 13 is set to be 0.3 mm.

(19) FIG. 2 is a view schematically describing a bonded interface between the ceramic substrate 11 and the circuit layer 12 (metal layer 13). As shown in FIG. 2, in the bonded interface between the ceramic substrate 11 and the circuit layer 12 (metal layer 13), a structure is established in which a CuSn layer 14 positioned on the ceramic substrate 11 side and a Ti-containing layer 15 containing Ti are laminated. In the present embodiment, the Ti-containing layer 15 has a structure in which a first intermetallic compound layer 16 which contains Ti and P, a Ti layer 18, and a second intermetallic compound layer 17 which contains Cu and Ti are laminated. In the CuSn layer 14, Sn forms a solid solution in Cu. The first intermetallic compound layer 16 is mainly constituted with Ti and P, the Ti layer 18 is mainly constituted with Ti, and the second intermetallic compound layer 17 is mainly constituted with Cu and Ti. However, these layers may also contain other elements.

(20) The semiconductor element 3 is constituted with a semiconductor material such as Si. The semiconductor element 3 and the circuit layer 12 are bonded to each other through a bonding layer 2.

(21) The bonding layer 2 is formed of a solder material based on SnAg, SnIn, or SnAgCu, for example.

(22) The heat sink 30 dissipates the heat from the aforementioned power module substrate 10. The heat sink 30 is constituted with Cu or a Cu alloy. In the present embodiment, the heat sink 30 is constituted with phosphorus deoxidized copper. The heat sink 30 is provided with passages 31 for a cooling fluid to flow through the passages. In the present embodiment, the heat sink 30 and the metal layer 13 are bonded to each other through the bonding layer 32 formed of a solder material.

(23) In the circuit layer 12 of the power module substrate 10 as the present embodiment, a circuit pattern is formed by performing an etching treatment.

(24) In the cross-sectional shape of an end portion of the circuit pattern of the circuit layer 12, an angle formed between a surface of the ceramic substrate 11 and an end face of the CuSn layer 14 is set in a range equal to or greater than 80 and equal to or smaller than 100. Furthermore, a maximum protrusion length L of the CuSn layer 14 or the Ti-containing layer 15 from an end face of the circuit layer 12 (maximum length of the CuSn layer 14 and the Ti-containing layer 15 protruding from an end face of the circuit layer 12) is set in a range equal to or greater than 2 m and equal to or smaller than 15 m.

(25) The end portion of the circuit pattern is one end portion of wiring included in the circuit pattern. The cross-sectional shape of the end portion of the circuit pattern is the shape of the end portion of the circuit pattern in a cross section which is perpendicular to the surface of the ceramic substrate 11 and is parallel to the direction along which the wiring in the end portion of the circuit pattern extends. For determining the angle , a straight line, which connects the bonding end of the ceramic substrate 11 and the CuSn layer 14 in the cross section to a midpoint between the highest point and the lowest point of surface asperities of the ceramic substrate 11 that are within a range of 20 nm from the bonding end in a horizontal direction, is defined as the surface of the ceramic substrate 11. The maximum protrusion length L is a maximum length between the end of the end face of the circuit layer 12 on the Ti-containing layer 15 side in the cross section and end faces of the CuSn layer 14 and the Ti-containing layer 15 protruding from the end face of the circuit layer 12, in a direction parallel to the surface of the ceramic substrate 11. In order to obtain the effects, which will be described later, obtained by setting the angle and the maximum protrusion length L within the range described above, the angle and the maximum protrusion length L preferably fall into the aforementioned range in one end portion of at least one wiring included in the circuit pattern, more preferably fall into the aforementioned range in both end portions of at least one wiring included in the circuit pattern, and even more preferably fall into the aforementioned range in both end portions of all wiring of the circuit pattern.

(26) Specific examples of the cross-sectional shape of the end portion of the circuit pattern of the circuit layer 12 will be described with reference to FIG. 3 and FIG. 4.

(27) In FIG. 3(a), the angle formed between the surface of the ceramic substrate 11 and the end face of the CuSn layer 14 is approximately 90 in the end portion of the circuit pattern (8892), and the maximum protrusion length L of the CuSn layer 14 or the Ti-containing layer 15 from the end face of the circuit layer 12 is equal to or smaller than 15 m. Note that FIG. 3(b-1) is an image obtained by SEM observation, and FIG. 3(b-2) is a view obtained by magnifying the vicinity of the end portion of the circuit pattern in FIG. 3(b-1). As is evident from FIG. 3(b-2), the Ti-containing layer 15 is also observed in the portion protruding from the end face of the circuit layer 12.

(28) In FIG. 3(c), the angle formed between the surface of the ceramic substrate 11 and the end face of the CuSn layer 14 is within a range greater than 90 and equal to or smaller than 100 in the end portion of the circuit pattern, and the maximum protrusion length L of the CuSn layer 14 or the Ti-containing layer 15 from the end face of the circuit layer 12 is equal to or smaller than 15 m. Furthermore, the end face of the Ti-containing layer 15 is positioned on an extended plane of the end face of the CuSn layer 14.

(29) In FIG. 4(a), the angle formed between the surface of the ceramic substrate 11 and the end face of the CuSn layer 14 is within a range equal to or greater than 90 and equal to or smaller than 100 in the end portion of the circuit pattern, and the maximum protrusion length L of the CuSn layer 14 or the Ti-containing layer 15 from the end face of the circuit layer 12 is equal to or smaller than 15 m. Furthermore, the end face of the Ti-containing layer 15 protrudes further toward the outside (direction separating from the end face of the circuit layer 12) compared to the end face of the CuSn layer 14.

(30) In FIG. 4(b), the angle formed between the surface of the ceramic substrate 11 and the end face of the CuSn layer 14 is within a range greater than 80 and less than 90 in the end portion of the circuit pattern, and the maximum protrusion length L of the CuSn layer 14 or the Ti-containing layer 15 from the end face of the circuit layer 12 is equal to or smaller than 15 m. Furthermore, the end face of the Ti-containing layer 15 protrudes further toward the outside compared to the end face of the CuSn layer 14.

(31) In FIG. 4(c), the angle formed between the surface of the ceramic substrate 11 and the end face of the CuSn layer 14 is within a range greater than 90 and equal to or smaller than 100 in the end portion of the circuit pattern, and the maximum protrusion length L of the CuSn layer 14 or the Ti-containing layer 15 from the end face of the circuit layer 12 is equal to or smaller than 15 m. Furthermore, the end face of the CuSn layer 14 protrudes further toward the outside compared to the end face of the Ti-containing layer 15.

(32) In the shapes shown in FIG. 3(a) and FIG. 3(c), the end face of the Ti-containing layer 15 is positioned on an extended plane of the end face of the CuSn layer 14. It is difficult for charges to be concentrated on the interface between the Ti-containing layer 15 and the CuSn layer 14, and the deterioration of partial discharge characteristics and voltage endurance characteristics can be sufficiently inhibited.

(33) Note that in the shapes shown in FIG. 4(a), FIG. 4(b), and FIG. 4(c), in a case where the angle formed between the surface of the ceramic substrate 11 and the end face of the CuSn layer 14 is set within a range equal to or greater than 80 and equal to or smaller than 100, and the maximum protrusion length L of the CuSn layer 14 or the Ti-containing layer 15 from the end face of the circuit layer 12 is set within a range equal to or greater than 2 m and equal to or smaller than 15 m, it is possible to obtain an effect of inhibiting the deterioration of partial discharge characteristics and voltage endurance characteristics.

(34) The angle is preferably equal to or greater than 85 and equal to or smaller than 95 and more preferably equal to or greater than 88 and equal to or smaller than 92, but is not limited to these. Furthermore, the maximum protrusion length L is preferably equal to or smaller than 10 m and more preferably equal to or smaller than 5 m, but is not limited to these.

(35) Next, a method for manufacturing the power module substrate 10 as the present embodiment will be described with reference to FIG. 5 and FIG. 6.

(36) (Lamination Step S01)

(37) First, as shown in FIG. 6, the CuPSn-based brazing filler material 24, the Ti material 25, and the Cu foil 22 which becomes the circuit layer 12 are laminated in this order on one surface (upper surface in FIG. 6) of the ceramic substrate 11, and the CuPSn-based brazing filler material 24, the Ti material 25, and the Cu foil 23 which becomes the metal layer 13 are laminated in this order on the other surface (lower surface in FIG. 6) of the ceramic substrate 11 (FIG. 6(a)). That is, between the ceramic substrate 11 and the Cu foil 22 and between the ceramic substrate 11 and the Cu foil 23, the CuPSn-based brazing filler material 24 is disposed on the ceramic substrate 11 side, and the Ti material 25 is disposed on the Cu foil 22 side and the Cu foil 23 side. The bonding surface between the Ti material 25 and the Cu foil 22 or 23 is a surface that is made smooth in advance.

(38) In the present embodiment, the composition of the CuPSn-based brazing filler material 24 is Cu-6.3 mass % P-9.3 mass % Sn-7 mass % Ni. The solidus temperature (melting start temperature) of the CuPSn-based brazing filler material 24 is 600 C. Furthermore, in the present embodiment, as the CuPSn-based brazing filler material 24, a foil material is used, and the thickness thereof is within a range equal to or greater than 5 m and equal to or smaller than 150 m.

(39) The thickness of the Ti material 25 is within a range equal to or greater than 0.4 m and equal to or smaller than 5 m. In a case where the thickness of the Ti material 25 is equal to or greater than 0.4 m and less than 1 m, it is preferable to deposit the Ti material 25 by vapor deposition or sputtering. In a case where the thickness of the Ti material 25 is equal to or greater than 1 m and equal to or smaller than 5 m, it is preferable to use a foil material. The lower limit of the thickness of the Ti material 25 is preferably equal to or greater than 0.4 m, and more preferably equal to or greater than 0.5 m. The upper limit of the thickness of the Ti material 25 is preferably equal to or smaller than 1.5 m, and more preferably equal to or smaller than 0.7 m In the present embodiment, as the Ti material 25, a Ti foil having a thickness of 1 m and a purity of 99.8 mass % is used.

(40) (Heat Treatment Step S02)

(41) Then, the Cu foil 22, the Ti material 25, the CuPSn-based brazing filler material 24, the ceramic substrate 11, the CuPSn-based brazing filler material 24, the Ti material 25, and the Cu foil 23 are put into a vacuum heating furnace in a state where pressure (equal to or higher than 1 kgf/cm.sup.2 and equal to or lower than 35 kgf/cm.sup.2 (equal to or higher than 0.10 MPa and equal to or lower than 3.43 MPa)) is applied thereto in the lamination direction, and heated (FIG. 6(b)). In the present embodiment, the internal pressure of the vacuum heating furnace is set within a range equal to or higher than 10.sup.6 Pa and equal to or lower than 10.sup.3 Pa, the heating temperature is set within a range equal to or higher than 560 C. and equal to or lower than 650 C., and the heating time is set within a range equal to or longer than 30 minutes and equal to or shorter than 360 minutes.

(42) In the heat treatment step S02, the Ti material 25 and the Cu foils 22 and 23 are bonded to each other by diffusion in solids, and the CuPSn-based brazing filler material 24 is melted and forms a liquid phase. By the solidification of the liquid phase, through the CuPSn-based brazing filler material 24, the ceramic substrate 11 and the Ti material 25 are bonded to each other. At this time, in the bonded interface between the circuit layer 12 and the ceramic substrate 11 and between the metal layer 13 and the ceramic substrate 11, the CuSn layer 14 and the Ti-containing layer 15 are formed.

(43) Accordingly, the circuit layer 12 is formed on one surface of the ceramic substrate 11, and the metal layer 13 is formed on the other surface of the ceramic substrate 11.

(44) (Circuit Pattern Forming Step S03)

(45) Then, by performing an etching treatment on the circuit layer 12, a circuit pattern is formed.

(46) In the present embodiment, first, a resist film is deposited on the circuit layer, and the circuit layer 12 formed of Cu or a Cu alloy is etched (Cu etching step S31). In the Cu etching step S31, it is preferable to use an etching agent containing, for example, ferric chloride, cupric chloride, sulfuric acid, and the like. In the present embodiment, in the Cu etching step S31, a spray etching method is used (FIG. 6(c)).

(47) After the Cu etching step S31, the Ti-containing layer 15 is etched (Ti etching step S32). In the Ti etching step S32, it is preferable to use an etching agent obtained by, for example, adding organic acid ammonium to aqueous hydrogen peroxide. As the etching agent, for example, SOLFINE (SE-TW-10) manufactured by SHOWA DENKO K.K. can be used.

(48) The etching may be performed under the conditions of a temperature of 70 C. to 80 C. and an etching time of 5 minutes to 20 minutes. Note that in the present embodiment, an immersion etching method is used in the Ti etching step S32 (FIG. 6(d)).

(49) After the Ti etching step S32, the CuSn layer 14 is etched (CuSn etching step S33). In the CuSn etching step S33, for example, an aqueous ammonium peroxydisulfate solution can be used. The etching may be performed under the conditions of a liquid temperature of 25 C. (room temperature) and an etching time of 10 minutes to 20 minutes. Note that in the present embodiment, an immersion etching method is used in the CuSn etching step S33 (FIG. 6(e)).

(50) By the circuit pattern forming step S03, a circuit pattern is formed on the circuit layer 12. Furthermore in the cross-sectional shape of the end portion of the circuit pattern, the angle formed between the surface of the ceramic substrate 11 and the end face of the CuSn layer 14 is set in a range equal to or greater than 80 and equal to or smaller than 100, and the maximum protrusion length L of the CuSn layer 14 or the Ti-containing layer 15 from the end face of the circuit layer 12 is set in a range equal to or greater than 2 m and equal to or smaller than 15 m. Note that by etching, it is difficult to make the maximum protrusion length L become less than 2 m.

(51) Through the steps described above, the power module substrate 10 as the present embodiment is manufactured.

(52) (Heat Sink Bonding Step S04)

(53) Then, as shown in FIG. 7, through a solder material as the bonding layer 32, the heat sink 30 is bonded to the lower surface of the metal layer 13 of the power module substrate 10 (FIG. 7(a)).

(54) (Semiconductor Element Bonding Step S05)

(55) Thereafter, as shown in FIG. 7, through a solder material, the semiconductor element 3 is bonded to the upper surface of the circuit layer 12 of the power module substrate 10 (FIGS. 7(b) and 7(c)).

(56) In this way, the power module 1 shown in FIG. 1 is manufactured.

(57) According to the power module substrate 10 as the present embodiment that is manufactured as described above, a circuit pattern is formed in the circuit layer 12 formed of Cu or a Cu alloy, and in the cross-sectional shape of the end portion of the circuit pattern of the circuit layer 12, the angle formed between the surface of the ceramic substrate 11 and the end face of the CuSn layer 14 is set in a range equal to or greater than 80 and equal to or smaller than 100. Therefore, in the end portion of the circuit pattern, a site having an acute-angled shape is not formed, and hence charge concentration can be inhibited. As a result, it is possible to inhibit the deterioration of partial discharge characteristics and voltage endurance characteristics.

(58) Furthermore, the maximum protrusion length L of the CuSn layer 14 or the Ti-containing layer 15 from the end face of the circuit layer 12 is set in a range equal to or greater than 2 m and equal to or smaller than 15 m. Therefore, it is possible to inhibit charges from being concentrated on the tip of the protruding portion and to inhibit the deterioration of partial discharge characteristics and voltage endurance characteristics.

(59) In addition, in the present embodiment, as shown in FIG. 3(c), in a case where the end face of the Ti-containing layer 15 is positioned on an extended plane of the end face of the CuSn layer 14 in the cross-sectional shape of the end portion of the circuit pattern of the circuit layer 12, the CuSn layer 14 and the Ti-containing layer 15 are smoothly connected to each other. Accordingly, it is possible to inhibit charges from being concentrated on the interface between the CuSn layer 14 and the Ti-containing layer 15 and to further inhibit the deterioration of partial discharge characteristics and voltage endurance characteristics.

(60) Hitherto, an embodiment of the present invention has been described. However, the present invention is not limited thereto and can be appropriately modified within a scope that does not depart from the technical idea of the present invention.

(61) In the present embodiment, a case where a metal layer formed of Cu or a Cu alloy is formed on the other surface of a ceramic substrate has been described, but the present invention is not limited thereto. The metal layer may not be formed, or a metal layer formed of Al or an Al alloy may be formed.

(62) Specifically, as shown in FIG. 8, a power module substrate 110 may be adopted in which the circuit layer 12 formed of Cu or a Cu alloy is formed on one surface of the ceramic substrate 11, and a metal layer 113 formed of Al or an Al alloy is formed on the other surface of the ceramic substrate 11. By bonding a heat sink 130 including passages 131 and the semiconductor element 3 to the power module substrate 110, a power module 101 shown in FIG. 8 is constituted.

(63) In the power module substrate 110, it is possible to simultaneously perform a step of forming the circuit layer 12 by bonding a copper foil to one surface of the ceramic substrate 11 by using a CuPSn-based brazing filler material and a Ti material and a step of bonding an Al foil formed of Al or an Al alloy to the other surface of the ceramic substrate 11 by using a brazing filler material. Furthermore, in a case where the heat sink 130 made of Al is used, a step of brazing the metal layer 113 and the heat sink 130 can also be simultaneously performed.

(64) The material or the structure of the heat sink is not limited to the present embodiment, and a design change may be appropriately carried out. Alternatively, the power module substrate may not have a heat sink.

(65) Furthermore, in the present embodiment, a constitution has been described in which the power module substrate and the heat sink are bonded to each other by using a solder material. However, a constitution may be adopted in which the power module substrate and the heat sink are fastened to each other by a screw and the like through grease provided therebetween.

(66) In addition, the etching agent used in each of the Cu etching step S31, the Ti etching step S32, and the CuSn etching step S33 is not limited to those exemplified in the present embodiment. It is preferable to select and use etching agents suitable for each of these steps, according to the material and the structure of the circuit layer, the material and the structure of the Ti-containing layer, the material and the structure of the CuSn layer, and the like.

(67) In the above embodiments, a case where a foil material of a CuPSn-based brazing filler material is used was described for example. However, the present invention is not limited thereto, and powder or paste can also be used.

(68) Furthermore, in the above embodiments, a case where a CuPSnNi brazing filler material or a CuPSn brazing filler material is used as the CuPSn-based brazing filler material was described. However, other CuPSn-based brazing filler materials may also be used.

(69) Herein, the content of P in the CuPSn-based brazing filler material is preferably equal to or greater than 3 mass % and equal to or smaller than 10 mass %.

(70) P is an element having an operation and effect of reducing the melting start temperature of the brazing filler material. In a case where P is oxidized, P oxide occurs. P is an element having an operation and effect of coating the surface of the brazing filler material with the P oxide so as to prevent the oxidation of the brazing filler material, and coating the surface of the molten brazing filler material with the P oxide having excellent fluidity so as to improve the wettability of the brazing filler material.

(71) In a case where the content of P is less than 3 mass %, the effect of reducing the melting start temperature of the brazing filler material may not be sufficiently obtained. Accordingly, the melting start temperature of the brazing filler material may be increased or the fluidity of the brazing filler material may become insufficient. As a result, the bonding properties between the ceramic substrate and the circuit layer may be reduced. Furthermore, in a case where the content of P is greater than 10 mass %, a large amount of brittle intermetallic compound may be formed. As a result, the bonding properties and the bonding reliability between the ceramic substrate and the circuit layer may be reduced.

(72) For these reasons, the content of P in the CuPSn-based brazing filler material is preferably within a range equal to or greater than 3 mass % and equal to or smaller than 10 mass %.

(73) The content of Sn in the CuPSn-based brazing filler material is preferably equal to or greater than 0.5 mass % and equal to or smaller than 25 mass %.

(74) Sn is an element having an operation and effect of reducing the melting start temperature of the brazing filler material. In a case where the content of Sn is equal to or greater than 0.5 mass %, the melting start temperature of the brazing filler material can be reliably reduced.

(75) In a case where the content of Sn is equal to or smaller than 25 mass %, it is possible to inhibit the brazing filler material from becoming brittle at a low temperature and to improve the bonding reliability between the ceramic substrate and the circuit layer.

(76) For these reasons, the content of Sn in the CuPSn-based brazing filler material is preferably within a range equal to or greater than 0.5 mass % and equal to or smaller than 25 mass %.

(77) The CuPSn-based brazing filler material may contain one kind of element or two or more kinds of elements among Ni, Cr, Fe, and Mn in an amount equal to or greater than 2 mass % and equal to or smaller than 20 mass %.

(78) Ni, Cr, Fe, and Mn are elements having an operation and effect of inhibiting the formation of an intermetallic compound containing P in the interface between the ceramic substrate and the brazing filler material.

(79) In a case where the content of one kind of element or two or more kinds of elements among Ni, Cr, Fe, and Mn is equal to or greater than 2 mass %, the formation of an intermetallic compound containing P in the bonded interface between the ceramic substrate and the brazing filler material can be inhibited, and the bonding reliability between the ceramic substrate and the circuit layer can be improved. Furthermore, in a case where the content of one kind of element or two or more kinds of elements among Ni, Cr, Fe, and Mn is equal to or smaller than 20 mass %, it is possible to inhibit the increase of the melting start temperature of the brazing filler material, to inhibit the decrease of the fluidity of the brazing filler material, and to improve the bonding properties between the ceramic substrate and the circuit layer.

(80) For these reasons, in a case where the CuPSn-based brazing filler material contains one kind of element or two or more kinds of elements among Ni, Cr, Fe, and Mn, the content of the element is preferably within a range equal to or greater than 2 mass % and equal to or smaller than 20 mass %.

EXAMPLES

Examples

(81) Hereinafter, the results of experiments performed to check the effects of the present invention will be described.

(82) According to the procedure described in the embodiment described above, each of the Cu foils (46 mm56 mm0.3 mm (thickness)) shown in Table 1 and Table 2 was bonded to one surface and the other surface of each of the ceramic substrates (50 mm60 mm0.635 mm (thickness) (AlN), 50 mm60 mm0.32 mm (thickness) (Si.sub.3N.sub.4)) shown in Table 1 and Table 2, thereby forming a circuit layer and a metal layer. As the Cu foil, oxygen-free copper (OFC in Tables 1 and 2) or tough pitch copper (Tough pitch in Tables 1 and 2) was used. A CuPSn-based brazing filler material having a thickness of 25 m was used.

(83) Then, the etching treatment described in the embodiment described above was performed on the circuit layer, thereby forming a circuit pattern having an interwiring distance of 500 m. Specifically, in the Cu etching step S31, by using iron chloride as an etching agent, spray etching was performed for 5 to 15 minutes at a liquid temperature of 50 C. to 70 C. In the Ti etching step S32, by using SOLFINE (SE-TW-10) manufactured by SHOWA DENKO K.K. as an etching agent, immersion etching was performed for 5 to 20 minutes by setting the liquid temperature of the etching agent to be 70 C. to 80 C. In the CuSn etching step S33, by using an aqueous ammonium peroxydisulfate solution having a concentration of 1 mol/dm.sup.3 as an etching agent, immersion etching was performed for 10 to 20 minutes by setting the liquid temperature of the etching agent to be 25 C.

(84) Thereafter, a cross section of an end portion of the circuit pattern in the obtained power module substrate was observed, and the angle formed between the surface of the ceramic substrate and the end face of the CuSn layer and the maximum protrusion length L of the CuSn layer or the Ti-containing layer from the end face of the circuit layer were measured. Note that the Form described in Table 1 and Table 2 shows to which form the example belongs among the drawings.

(85) During the observation of the cross section, by using a cross section polisher (SM-09010 manufactured by JEOL Ltd.), ion etching was performed on a cross section of the circuit layer (cross section which is perpendicular to the surface of the ceramic substrate and is parallel to the direction along which wiring extends in the end portion of the circuit pattern) under the conditions of an ion accelerating voltage: 5 kV, a processing time: 14 hours, and a protrusion amount from a masking shield: 100 m, and then the end portion of the circuit pattern was observed using a scanning electron microscope (SEM).

(86) For evaluating the voltage endurance characteristics of the obtained power module substrates, a cycle was repeated in which each of the power module substrates was immersed in insulating oil (FLUORINERT FC-770 manufactured by 3M), voltage was increased to 0.5 kV for 5 seconds, and then the power module substrate was kept as it was for 30 seconds. A voltage at a point in time when the amount of discharged charges exceeded 10 pC while the power module substrate was being kept as it was taken as a partial discharge start voltage, and partial discharge characteristics were evaluated. The evaluation results are shown in Table 1 and Table 2.

(87) TABLE-US-00001 TABLE 1 Cross-sectional shape of end portion of circuit pattern Evaluation Ceramic Maximum protrusion Partial discharge start substrate Cu foil Angle () length L (m) Form voltage (kV) Example 1 AlN OFC 88 2.3 FIG. 3(a) 11.0 Example 2 AlN OFC 91 14.7 FIG. 3(a) 8.5 Example 3 AlN OFC 85 2.3 FIG. 3(c) 11.0 Example 4 AlN OFC 95 14.7 FIG. 3(c) 8.5 Example 5 AlN OFC 81 9.8 FIG. 3(c) 9.0 Example 6 AlN OFC 98 8.6 FIG. 3(c) 10.0 Example 7 AlN OFC 93 2.2 FIG. 4(d) 10.5 Example 8 AlN OFC 87 14.8 FIG. 4(d) 8.5 Example 9 AlN OFC 82 9.8 FIG. 4(d) 9.0 Example 10 AlN OFC 99 8.6 FIG. 4(d) 9.5 Example 11 AlN OFC 94 8.8 FIG. 4(e) 9.5 Example 12 AlN OFC 86 9.2 FIG. 4(f) 9.0 Example 13 AlN TOUGH PITCH 87 5.3 FIG. 3(c) 9.5 Comparative Example 1 AlN OFC 87 30.0 FIG. 3(c) 7.0 Comparative Example 2 AlN OFC 65 8.6 FIG. 3(c) 7.0 Comparative Example 3 AlN OFC 112 9.4 FIG. 3(c) 7.5

(88) TABLE-US-00002 TABLE 2 Cross-sectional shape of end portion of circuit pattern Evaluation Ceramic Maximum protrusion Partial discharge start substrate Cu foil Angle () length L (m) Form voltage (kV) Example 14 Si.sub.3N.sub.4 OFC 89 2.2 FIG. 3(a) 9.5 Example 15 Si.sub.3N.sub.4 OFC 91 14.5 FIG. 3(a) 7.0 Example 16 Si.sub.3N.sub.4 OFC 87 2.3 FIG. 3(c) 9.5 Example 17 Si.sub.3N.sub.4 OFC 94 14.8 FIG. 3(c) 7.0 Example 18 Si.sub.3N.sub.4 OFC 80 9.5 FIG. 3(c) 7.0 Example 19 Si.sub.3N.sub.4 OFC 99 7.9 FIG. 3(c) 8.5 Example 20 Si.sub.3N.sub.4 OFC 92 2.3 FIG. 4(d) 9.0 Example 21 Si.sub.3N.sub.4 OFC 85 14.6 FIG. 4(d) 7.0 Example 22 Si.sub.3N.sub.4 OFC 82 8.6 FIG. 4(d) 7.5 Example 23 Si.sub.3N.sub.4 OFC 99 8.8 FIG. 4(d) 7.5 Example 24 Si.sub.3N.sub.4 OFC 93 8.6 FIG. 4(e) 8.0 Example 25 Si.sub.3N.sub.4 OFC 86 8.7 FIG. 4(f) 7.5 Example 26 Si.sub.3N.sub.4 TOUGH PITCH 88 4.9 FIG. 3(c) 8.0 Comparative Example 4 Si.sub.3N.sub.4 OFC 87 30.0 FIG. 3(c) 5.0 Comparative Example 5 Si.sub.3N.sub.4 OFC 67 8.7 FIG. 3(c) 5.5 Comparative Example 6 Si.sub.3N.sub.4 OFC 115 8.2 FIG. 3(c) 5.5

(89) Regarding the results shown in Table 1 obtained by using AlN as a ceramic substrate, it was understood that in the examples of the present invention, in which the angle formed between the surface of the ceramic substrate and the end face of the CuSn layer is set in a range equal to or greater than 80 and equal to or smaller than 100 and the maximum protrusion length L of the CuSn layer or the Ti-containing layer from the end face of the circuit layer is set in a range equal to or greater than 2 m and equal to or smaller than 15 m, a power module substrate is obtained which has a high partial discharge start voltage and is excellent in partial discharge characteristics and voltage endurance characteristics.

(90) The results shown in Table 2 obtained using Si.sub.3N.sub.4 as a ceramic substrate were the same as the results obtained using AlN.

INDUSTRIAL APPLICABILITY

(91) According to the present invention, it is possible to inhibit the occurrence of partial discharge in a circuit layer formed on one surface of the ceramic substrate and to inhibit the occurrence of short-circuit even though a fine circuit pattern is formed. Therefore, the present invention is suitable for power semiconductor elements for high power control that are used for controlling wind power generation and electric vehicles such as electric cars.

REFERENCE SIGNS LIST

(92) 10, 110 power module substrate

(93) 11 ceramic substrate

(94) 12 circuit layer

(95) 14 CuSn layer

(96) 15 Ti-containing layer