Self-aligned gate and drift design for high-critical field strength semiconductor power transistors with ion implantation

Abstract

Methods of forming a self-aligned gate (SAG) and self-aligned source (SAD) device for high E.sub.crit semiconductors are presented. A dielectric layer is deposited on a high E.sub.crit substrate. The dielectric layer is etched to form a drift region. A refractory material is deposited on the substrate and dielectric layer. The refractory material is etched to form a gate length. Implant ionization is applied to form high-conductivity and high-critical field strength source with SAG and SAD features. The device is annealed to activate the contact regions. Alternately, a refractory material may be deposited on a high E.sub.crit substrate. The refractory material is etched to form a channel region. Implant ionization is applied to form high-conductivity and high E.sub.crit source and drain contact regions with SAG and SAD features. The refractory material is selectively removed to form the gate length and drift regions. The device is annealed to activate the contact regions.

Claims

1. A method of forming a self-aligned gate (SAG) and self-aligned source (SAD) device for high E.sub.crit semiconductors, the method comprising: depositing a refractory material on a high E.sub.crit substrate; etching the refractory material to form a channel region; applying an implant ionization to form a high-conductivity source region and a high-conductivity drain contact region in the high E.sub.crit substrate creating a self-aligned gate plus self-aligned drift feature; and annealing to activate the source and drain contact regions, wherein the substrate comprises an n-type Ga.sub.2O.sub.3 grown on semi-insulating Ga.sub.2O.sub.3.

2. The method of claim 1, the method further comprising: depositing a first dielectric layer on the substrate prior to depositing the refractory material.

3. The method of claim 2, further comprising: selectively removing the first dielectric layer after the implant ionization to expose the high-conductivity source and high-conductivity drain contact regions.

4. The method of claim 2, wherein the first dielectric layer comprises more than one material.

5. The method of claim 4, wherein the first dielectric layer comprises an alternating stack.

6. The method of claim 4, wherein the first dielectric layer comprises a bi/tri layer dielectric.

7. The method of claim 2, wherein the first dielectric is selected from a group consisting of SiO.sub.2, Al.sub.2O.sub.3, AlN, and combinations thereof.

8. The method of claim 1, wherein etching the refractory material comprises: patterning the refractory material with one of optical lithography and nanolithography; and removing material with one of wet or dry etching.

9. The method of claim 1, wherein the refractory material comprises tungsten.

10. The method of claim 1, further comprising: depositing a second dielectric layer after etching the refractory material and prior to implant ionization.

11. The method of claim 10, further comprising: selectively removing the second dielectric layer after the implant ionization to expose the source and drain contact regions.

12. A method of forming a self-aligned gate (SAG) and self-aligned source (SAD) device for high E.sub.crit semiconductors, the method comprising: depositing a refractory material on a high E.sub.crit substrate; etching the refractory material to form a channel region; applying an implant ionization to form a high-conductivity source region and a high-conductivity drain contact region in the high E.sub.crit substrate creating a self-aligned gate plus self-aligned drift feature; and annealing to activate the source and drain contact regions, wherein the substrate comprises an n-type Ga.sub.2O.sub.3 bonded to a high thermal conductivity wafer.

13. The method of claim 12, the method further comprising: depositing a first dielectric layer on the substrate prior to depositing the refractory material.

14. The method of claim 13, further comprising: selectively removing the first dielectric layer after the implant ionization to expose the high-conductivity source and high-conductivity drain contact regions.

15. The method of claim 13, wherein the first dielectric layer comprises more than one material.

16. The method of claim 15, wherein the first dielectric layer comprises an alternating stack.

17. The method of claim 1, wherein the first dielectric layer comprises a bi/tri layer dielectric.

18. The method of claim 1, wherein the first dielectric is selected from a group consisting of SiO.sub.2, Al.sub.2O.sub.3, AlN, and combinations thereof.

19. The method of claim 12, wherein etching the refractory material comprises: patterning the refractory material with one of optical lithography and nanolithography; and removing material with one of wet or dry etching.

20. The method of claim 12, wherein the refractory material comprises tungsten.

21. The method of claim 12, further comprising: depositing a second dielectric layer after etching the refractory material and prior to implant ionization.

22. The method of claim 21, further comprising: selectively removing the second dielectric layer after the implant ionization to expose the source and drain contact regions.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and, together with a general description of the invention given above, and the detailed description given below, serve to explain the invention.

(2) FIGS. 1-9 illustrate a series of steps consistent with an exemplary embodiment of the invention for fabricating high E.sub.crit transistors;

(3) FIGS. 10-17 illustrate a series of steps consistent with an alternate exemplary embodiment of the invention for fabricating high E.sub.crit transistors;

(4) FIG. 18 is a schematic cross section for an exemplary self-aligned gamma-gate (SAGG) MOSFET consistent with embodiments of the process illustrated in FIGS. 1-9;

(5) FIG. 19 is a graph of I.sub.DS-V.sub.DS output family of curves with inset of V.sub.BK vs. log I.sub.DS for the exemplary SAGG MOSFET of FIG. 18;

(6) FIG. 20 is a R.sub.ON.Math.Q.sub.G figure of merit benchmark comparing the SAGG MOSFET of FIG. 18 with other contemporary devices;

(7) FIG. 21 is a schematic cross-section for an exemplary beta-phase gallium oxide (BGO) self-aligned gate (SAG) MOSFET consistent with embodiments of the process illustrated in FIGS. 10-17;

(8) FIG. 22 is a graph of I.sub.DS-V.sub.DS output family of curves pulsed from a V.sub.GS=0, V.sub.DS=0 quiescent point with transducer gain contours superimposed on the I-V plane of the SAG MOSFET of FIG. 21; and

(9) FIG. 23 is a graph of pulsed output power performance at 1 GHz for the SAG MOSFET of FIG. 21 at V.sub.DS=15 V.

(10) It should be understood that the appended drawings are not necessarily to scale, presenting a somewhat simplified representation of various features illustrative of the basic principles of the invention. The specific design features of the sequence of operations as disclosed herein, including, for example, specific dimensions, orientations, locations, and shapes of various illustrated components, will be determined in part by the particular intended application and use environment. Certain features of the illustrated embodiments have been enlarged or distorted relative to others to facilitate visualization and clear understanding. In particular, thin features may be thickened, for example, for clarity or illustration.

DETAILED DESCRIPTION OF THE INVENTION

(11) Embodiments of the invention provide methodology allowing for a self-aligned gate-to-source and self-aligned drift (SAG+SAD) regions for high E.sub.crit semiconductors (greater than 3.4 eV), such as gallium oxide (Ga.sub.2O.sub.3), using a combination of refractory material, subtractive etch technology, and dielectric masking layers fabricated with nanolithography.

(12) Embodiments of the invention include steps such as depositing one or more high E.sub.crit insulators to function as the gate insulator, implant cap, and electric-field management layers on high E.sub.crit substrate with high E.sub.crit epitaxial layer(s) grown on the substrate surface. These insulating materials may be defined by a combination of optical and nanolithography, which form the self-aligned gate and drift regions (SAG+SAD). A refractory material layer may then be subsequently deposited by standard lift-off or defined subtractively by one or more etching steps to form the SAG+SAD feature in some embodiments. A combination of insulating layers and/or the refractory material layer may serve as a hard mask for ion-implantation in some embodiments. In these and other embodiments, an optional high E.sub.crit insulator sidewall spacer layer may be deposited conformally with optional etch back process. This layer may then act as an ion-implantation spacer layer to enhance gate-to-source electrical isolation. The ion-implanted donors require a high-temperature activation step and may include the oxide and metal layers defined prior to ion-implantation. The implant screen may then be removed using one or more etch processes before or after the high-temperature to allow ohmic contact metal deposition. Additional metal interconnect layers may then be deposited to reduce transistor electrode resistance.

(13) Turning now to the drawings and FIG. 1, a process 10 for an exemplary embodiment begins with high E.sub.crit epitaxial layer(s) deposited on a lattice-matched substrate and/or alternately bonded onto a mechanical and/or high thermal conductivity carrier wafer (substrate 12) in some embodiments. The substrate could include materials such as n-type Ga.sub.2O.sub.3 grown on semi-insulating bulk Ga.sub.2O.sub.3 or these same materials bonded to a wafer with high thermal conductivity such as SiC and diamond. As illustrated in FIG. 2, an optional dielectric layer 14 may be deposited on the substrate 12 to function as an etch stop, implant ionization (I/I) cap, and/or gate dielectric. In other embodiments, dielectric layer 14 may be comprised of more than one material like an alternating stack or bi/try-layer dielectric, for example. A second dielectric layer 16 with high E.sub.crit is then deposited on top of dielectric layer 14 as illustrated in FIG. 3. In other embodiments, dielectric layer 16 may also be comprised of more than one material like an alternating stack or bi/try-layer dielectric, for example. The dielectric layers 14, 16 may be SiO.sub.2, Al.sub.2O.sub.3 and AlN as examples of those with insulating properties and high E.sub.crit. Dielectric layer 16 may then be patterned by one or a combination of wet and dry etching with an optical lithography step and/or nanolithography such as electron beam lithography. The remaining material defines an initial drift region dimension 18.

(14) In this illustrated embodiment, an optional dielectric 20, such as Al.sub.2O.sub.3, may be deposited for one or a combination of etch stop, implant ionization cap, implant spacer, or a gate dielectric, or an implant ionization mask as illustrated in FIG. 5, expanding the drift region dimension 22. Next, a refractory material 24, such as Tungsten (W), with low resistance may be deposited on the optional dielectric 20 as illustrated in FIG. 6. This refractory material layer 24 may be patterned and material removed by wet or dry etching to form the gate length 26 as illustrated in FIG. 7. An optional gate-connected field plate (GC-FP) 28 may be formed on top of dielectric layer 16 with length not to exceed the drift region dimension 22.

(15) The structure may then be subjected to an implant ionization (I/I) step 30 to form high-conductivity and high E.sub.crit source and drain contact regions 32 in the high E.sub.crit substrate 12 as seen in FIGS. 7 and 8. Refractory material 24 and dielectric layers 16, 20 are a hard mask, which protects the channel region from I/I 30 and forms the self-aligned gate 36 plus the self-aligned drift 38 feature as illustrated in FIG. 8. The channel region is equal to the sum of the gate-length 26 and the calculated drift region 22. Dielectric layers 14, 20 may then be selectively removed on top of the source and drain contact regions 32 to allow for subsequent ohmic contact metal electrodes by a combination of wet and/or dry etching as illustrated in FIG. 9. Finally, the structure may be annealed at high temperature (>800 C) to activate the source and drain contact regions 32 in high E.sub.crit substrate 12. Conventional electrical isolation, metal interconnects and surface passivation layers may be used after the high-temperature anneal step.

(16) In an alternate process 40, high E.sub.crit epitaxial layer(s) may be deposited on a lattice-matched substrate and/or alternately may be bonded onto a mechanical and/or high thermal conductivity carrier wafer (substrate 42 in FIG. 10) in some embodiments. The substrate could include materials such as n-type Ga.sub.2O.sub.3 grown on semi-insulating bulk Ga.sub.2O.sub.3 or these same materials bonded to a wafer with high thermal conductivity such as SiC and diamond. As illustrated in FIG. 11, an optional single or composite dielectric layer 44 may be deposited on the substrate 42 to function as a gate oxide, etch stop, implant ionization (I/I) cap and/or surface passivation layer. The dielectric layer 44 may be SiO.sub.2, Al.sub.2O.sub.3, and AlN as examples of those with insulating properties and high E.sub.crit. A refractory material 46, such as Tungsten, with low resistance may then be deposited on the dielectric layer 44 as illustrated in FIG. 12. Refractory material 46 may then be patterned by an optical lithography step and/or nanolithography such as electron beam lithography to precisely form the channel region 48 as illustrated in FIG. 13. In this illustrated embodiment, an optional dielectric 50 such as Al.sub.2O.sub.3, may be deposited for one or a combination of etch stop, implant ionization cap, implant spacer, gate dielectric, or an implant ionization mask as illustrated in FIG. 14 expanding the drift region dimension 52.

(17) The structure may then be subjected to an I/I step 54 to form high-conductivity source and drain contact regions 56 in the high E.sub.crit substrate 42 as illustrated in FIGS. 14 and 15. Refractory material 46 and sidewall spacer 50 acts as a hard mask material, which protects the channel region from I/I step 50 and forms the self-aligned gate 58 plus the self-aligned drift 60 feature as illustrated in FIG. 15. Then refractory material 46 may be patterned by an optical lithography step and/or nanolithography such as electron beam lithography and a portion removed by wet or dry etching to form the gate contact 62 and drift region 64 as illustrated in FIG. 16. Dielectric layers 44, 50 may then be selectively removed on top of the source and drain contact regions 56 to allow for subsequent ohmic contact metal electrodes by a combination of wet and/or dry etching as illustrated in FIG. 17. Finally, the sample may be annealed at high temperature (>800 C) to activate the I/I species in the source and drain contact regions 56. Conventional electrical isolation, metal interconnects and surface passivation layers can be used after the high-temperature anneal step.

(18) Turning to FIG. 18, an exemplary self-aligned gamma gate (SAGG) device 70 may use the embodiments of the invention presented above in relation to FIGS. 1-9. This exemplary transistor is a single homoepitaxial Si-doped beta-phase gallium oxide (BGO) channel grown by MOVPE. A SiO.sub.2 mask forms the drift region then both a conformal ALD Al.sub.2O.sub.3 gate dielectric and sputtered W layer are deposited. The W is selectively etched forming a gamma-shaped gate electrode followed by an n+Si ion implantation step to form the SAGG feature. The device has standard mesa, ohmic contacts with 470° C. rapid thermal anneal, and Ti/Au interconnect metallization prior to characterization.

(19) FIGS. 19 and 20 show the dynamic switch loss performance of SAGG MOSFETs. In FIG. 19, the SAGG MOSFET dc performance is shown with V.sub.BK=321 V for a 2.5 μm source-drain distance. Several SAGG MOSFETs were characterized by C−V to conservatively estimate the total Q.sub.G and determine the R.sub.ON.Math.Q.sub.G Figure of Merit as illustrated in FIG. 20. The SAGG MOSFETs compare well to an E-mode BGO MOSFET and may be significantly improved with materials and device engineering to limit the gate swing while scaling the device to remove additional parasitic resistance.

(20) FIG. 21 illustrates an alternate exemplary SAG device 80 that may use the embodiments of the invention presented above in relation to FIGS. 10-17. This exemplary SAG device material is a single homoepitaxial Si-doped BGO channel grown by oxygen plasma MBE. The device process consists of depositing an ALD Al.sub.2O.sub.3 gate dielectric and patterning a Tungsten (W) layer to protect the transistor channel during an n+Si ion implantation process. The W mask is etched back to form the SAG electrode and drift region followed by a 900° C. implant activation process. Lastly, the device has standard mesa, ohmic contacts with 470° C. rapid thermal anneal, and Ti/Au interconnect metallization prior to characterization.

(21) FIGS. 22 and 23 show the RF performance of the SAG MOSFET 80. The f.sub.T(f.sub.max) (not shown) is approximately 4 (13) GHz which is sufficient for 1 GHz load-pull characterization. In FIG. 22, the transducer gain (G.sub.T) of the SAG MOSFET is shown in the pulsed IDS-VDS plane with V.sub.GS=0, V.sub.DS=0 quiescent point. The device delivers>20% PAE and >0.7 W/mm using 10 μs pulses at 1 GHz. The variation in output power at 1 GHz as a function of pulse width is illustrated in FIG. 23.

(22) High E.sub.crit transistors with the SAG+SAD feature will have dynamic power switching losses substantially less than contemporary state-of-the-art power transistors rated for the same voltage. For a given power loss target, high E.sub.crit transistors with SAG and/or SAD can accept much higher dynamic switch losses, or switch speed, since the conduction losses are orders of magnitude less. Higher switching speed 10×-100× faster than contemporary state-of-the-art has additional benefits of smaller passive component design that shrinks the size of power modules. Further, the high voltage capability of high E.sub.crit transistors allow integration of point-of-load power conversion directly from a high-voltage source for simplified power distribution with reduced cabling size and weight coupled with more compact power modules.

(23) High E.sub.crit transistors fabricated with SAG+SAD technology may also assist in offering low on-resistance for a given V.sub.bk compared to other contemporary state-of-the-art semiconductor technology. These devices may be used in numerous applications such as dc-to-dc power conversion, pulsed power, and high-efficiency radio frequency switch-mode amplifiers.

(24) While the present invention has been illustrated by a description of one or more embodiments thereof and while these embodiments have been described in considerable detail, they are not intended to restrict or in any way limit the scope of the appended claims to such detail. Additional advantages and modifications will readily appear to those skilled in the art. The invention in its broader aspects is therefore not limited to the specific details, representative apparatus and method, and illustrative examples shown and described. Accordingly, departures may be made from such details without departing from the scope of the general inventive concept.