A semiconductor device includes: a semiconductor substrate having opposing first and second main surfaces; a plurality of transistor cells each including a source region, a drift zone, a body region separating the source region from the drift zone, a field plate trench extending into the drift zone and including a field plate, and a planar gate on the first main surface and configured to control current through a channel of the body region; a drain region at the second main surface; and a diffusion barrier structure including alternating layers of Si and oxygen-doped Si and a Si capping layer on the alternating layers of Si and oxygen-doped Si. The diffusion barrier structure may be interposed between body regions of adjacent transistor cells and/or extend along the channel of each transistor cell and/or vertically extend in the semiconductor substrate between adjacent field plate trenches.

A semiconductor device includes a source/drain diffusion area, a first doped region and a gate. The source/drain diffusion area, defined between a first isolation structure and a second isolation structure, includes a source region, a drain region and a device channel. The first doped region, disposed along a first junction between the device channel and the first isolation structure, is separated from at least one of the source region and the drain region. The first doped region has a dopant concentration higher than that of the device channel. The gate is disposed over the source/drain diffusion area. The first doped region is located within a projected area of the gate onto the source/drain diffusion area, the first isolation structure and the second isolation structure. A length of the first doped region is shorter than a length of the gate in a direction from the source region to the drain region.

A multi-transistor device includes first and second lateral double-diffused metal-oxide-semiconductor field effect (LDMOS) transistors sharing a first p-type reduced surface field (RESURF) layer and a first drain n+ region. In certain embodiments, the first LDMOS transistor includes a first drift region, the second LDMOS transistor includes a second drift region, and the first and second drift regions are at least partially separated by the first p-type RESURF layer in a thickness direction.

Methods of forming a self-aligned gate (SAG) and self-aligned source (SAD) device for high E.sub.crit semiconductors are presented. A dielectric layer is deposited on a high E.sub.crit substrate. The dielectric layer is etched to form a drift region. A refractory material is deposited on the substrate and dielectric layer. The refractory material is etched to form a gate length. Implant ionization is applied to form high-conductivity and high-critical field strength source with SAG and SAD features. The device is annealed to activate the contact regions. Alternately, a refractory material may be deposited on a high E.sub.crit substrate. The refractory material is etched to form a channel region. Implant ionization is applied to form high-conductivity and high E.sub.crit source and drain contact regions with SAG and SAD features. The refractory material is selectively removed to form the gate length and drift regions. The device is annealed to activate the contact regions.

A semiconductor device (300) comprising: a doped semiconductor substrate (302); an epitaxial layer (304), disposed on top of the substrate, the epitaxial layer having a lower concentration of dopant than the substrate; a switching region disposed on top of the epitaxial layer; and a contact diffusion (350) disposed on top of the epitaxial layer, the contact diffusion having a higher concentration of dopant than the epitaxial layer; wherein the epitaxial layer forms a barrier between the contact diffusion and the substrate.

Disclosed is a high voltage semiconductor device and a method of manufacturing the same and, more particularly, to a high voltage semiconductor device and a method of manufacturing the same that enables an improvement in the breakdown voltage relative to the on-resistance by forming a top region in or at the surface of the substrate when the device includes a field plate adjacent to a gate electrode.

A method for manufacturing a semiconductor device, includes: applying a laser beam to a plane extending at a predetermined depth in a semiconductor substrate from a second main surface side of the semiconductor substrate opposite to a first main surface side on which a device structure including a channel is formed; and peeling off a device layer including the device structure from the semiconductor substrate along the plane applied with the laser beam. In the applying of the laser beam, the laser beam is applied so that a power density is lower in a region corresponding to the channel in a thickness direction of the semiconductor substrate than in the other region, in the plane extending at the predetermined depth in the semiconductor substrate.

A semiconductor device including a substrate, a source region, a drain region, a first gate structure and a second gate structure is provided. The source region and a drain region are formed in the substrate. The first gate structure is formed on the substrate and adjacent to the source region. The second gate structure is formed on the substrate and adjacent to the drain region. The second gate structure is electrically coupled to the drain region.

Power semiconductor devices, and related methods, where majority carrier flow is divided into paralleled flows through two drift regions of opposite conductivity types.

Power devices using refilled trenches with permanent charge at or near their sidewalls. These trenches extend vertically into a drift region.