Abstract
The disclosed technology generally relates to a method of forming a nanoscale opening in a semiconductor structure, and more particularly to forming a nanoscale opening that can be used for sensing the presence of polymers, e.g., the individual bases of deoxyribonucleic acid (DNA) or ribonucleic acid (RNA). In one aspect, a method of forming a nanopore in a semiconductor fin includes providing a fin structure comprising a bottom layer and a top layer, pattering the top layer to form a pillar, and laterally embedding the pillar in a filler material. The method additionally includes forming an aperture in the filler material by removing the pillar, and forming the nanopore in the bottom layer by etching through the aperture. In another aspect, a semiconductor fin is fabricated using the method.
Claims
1. A method of forming a nanopore, the method comprising: providing a fin structure comprising a bottom layer and a top layer; pattering the top layer to form a pillar; laterally embedding the pillar in a filler material; forming an aperture in the filler material by removing the pillar; and forming the nanopore in the bottom layer by etching through the aperture.
2. The method of claim 1, wherein patterning the top layer comprises self-aligning the pillar on the bottom layer using a line mask intersecting the fin structure.
3. The method of claim 1, wherein forming the aperture further comprises lining the aperture with a spacer material, thereby reducing a size of the aperture.
4. The method of claim 1, wherein the top layer comprises a first mask material and a second mask material arranged on top of the first mask material, and wherein the first mask material serves as an etch stop material protecting the bottom layer during etching of the second mask material.
5. The method of claim 4, wherein the first mask material is selected from the group consisting of silicon dioxide (SiO.sub.2), silicon nitride (Si.sub.3N.sub.4), silicon oxycarbide (SiOC) and silicon oxynitride (SiON), and wherein the second mask material is selected from the group consisting of amorphous silicon (a-Si), titanium nitride (TiN), silicon dioxide (SiO.sub.2), silicon nitride (Si.sub.3N.sub.4), silicon oxycarbide (SiOC) and silicon oxynitride (SiON).
6. The method of claim 1, wherein the filler material is selected from the group consisting of silicon dioxide (SiO.sub.2) and silicon nitride (Si.sub.3N.sub.4).
7. The method of claim 1, wherein the spacer material is selected from the group consisting of silicon dioxide (SiO.sub.2), silicon nitride (Si.sub.3N.sub.4), silicon oxycarbide (SiOC) and a metal.
8. The method of claim 1, wherein forming the nanopore comprises forming a tapered nanopore.
9. The method of claim 1, wherein the bottom layer comprises silicon.
10. The method of claim 1, wherein forming the nanopore comprises lining the nanopore with a spacer material, thereby reducing a size of the nanopore.
11. A semiconductor structure with at least one nanopore, comprising: a semiconductor fin extending in a lateral length direction over a substrate; a dielectric filler material formed over the semiconductor fin; and a nanopore formed in a vertical direction through the filler material and further through the semiconductor fin, such that the nanoscale pore exposes a top surface of the substrate.
12. The semiconductor structure of claim 11, wherein the semiconductor fin has a width less than about 10 nm.
13. The semiconductor structure of claim 12, wherein a lateral dimension of the nanopore in a lateral width direction of the semiconductor fin is smaller than the width of the fin such that the nanopore is laterally confined within the semiconductor fin.
14. The semiconductor structure of claim 13, wherein a portion of the nanopore formed through the dielectric filler material is lined with a spacer material different from the dielectric filler material, wherein the spacer material does not extend into a portion of the nanopore formed through the semiconductor fin.
15. The semiconductor structure of claim 14, further comprising an etch stop layer vertically interposed between the semiconductor fin and the dielectric filler material, wherein the etch stop layer is formed of a material different from the dielectric filler material and the spacer material.
16. A transistor device with at least one nanopore, comprising: a semiconductor fin extending in a lateral length direction over on a substrate; a dielectric filler material formed over the semiconductor fin; a nanopore formed in a vertical direction through the filler material and further through the semiconductor fin, such that the nanoscale pore exposes a top surface of the substrate; and a source and a drain on formed on opposite sides of the nanopore in the semiconductor fin, such that the transistor device is configured for DNA sensing.
17. The semiconductor structure of claim 16, wherein a lateral dimension of the nanopore in a lateral width direction of the semiconductor fin is smaller than the width of the fin such that the nanopore is laterally confined within the semiconductor fin.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
[0029] The above, as well as additional objects, features and advantages of the disclosed technology, will be better understood through the following illustrative and non-limiting detailed description, with reference to the appended drawings. In the drawings like reference numerals will be used for like elements unless stated otherwise.
[0030] FIGS. 1A-1E illustrate intermediate structures at various stages of a method of forming a nanopore in a semiconductor fin, according to embodiments.
[0031] FIGS. 2A-2E illustrate intermediate structures at various stages of a variation of a method of forming a nanopore in a semiconductor fin, according to embodiments.
[0032] FIG. 3 illustrate a device comprising a semiconductor fin and a nanopore, according to embodiments.
[0033] FIG. 4 is a flowchart schematically illustrating a method of forming a nanopore in a semiconductor fin, according to embodiments.
DETAILED DESCRIPTION OF CERTAIN ILLUSTRATIVE EMBODIMENTS
[0034] A method of forming a nanopore in a semiconductor fin will now be described with reference to FIGS. 1A-1E, illustrating intermediate structures at various stages of forming a nanopore in a fin structure according to embodiments, using vertical cross sections taken along the length direction of the fin structure.
[0035] FIG. 1A shows a fin structure 100 comprising a bottom layer 110 and a top layer 120 arranged on a substrate 180. The bottom layer 110 may, for example, be formed of Si, such as of a SOI wafer, and the top layer 120 of, for example, SiO.sub.2, Si.sub.3N.sub.4 or other materials which, preferably, provides an etch selectivity relative the material of the bottom layer 110. The bottom layer 110 and the top layer 120 may be provided in the form of a stack, which may be patterned into one or several fin structures 100 using a suitable fin patterning process, which may include a lithography process and an etch process.
[0036] In a subsequent step, the top layer 120 may be patterned into a pillar structure 122 as shown in the intermediate structure illustrated in FIG. 1B. This may, for example, be achieved by forming a line mask (not shown) over the fin structure 100 (FIG. 1A) across the fin structure 100 and a following etch process, leaving a pillar or dot shaped mask structure 122 on top of the fin 20 formed by the bottom layer 110. The position of the line mask in the length direction of the fin structure 100 determines the alignment of the pillar structure 122 along the fin 20, whereas the pillar structure 122 is self-aligned in the lateral direction (e.g., the width direction) of the fin 20.
[0037] In the intermediate structure illustrated in FIG. 1C, the pillar 122 has been embedded in a filler layer 130, which, for example, may be formed of a dielectric filling material such as Si.sub.3N.sub.4 of SiO.sub.3. In the present example, the top surface of the structure has been planarized, for example by means of a chemical-mechanical planarization (CMP) process.
[0038] FIG. 1D shows an intermediate structure after the pillar 122 has been removed, leaving an aperture 140 that can be used as an etch mask for the resulting nanopore 10. The pillar 122 may hence be referred to as a sacrificial pillar 122. The material of the pillar 122 may, for example, be etched in a suitable wet etch process, such as tetramethylammonium hydroxide (TMAH) in case the pillar 122 is formed of, for example, amorphous Si. Advantageously, the TMAH etch is used in combination with an etch stop layer separating the pillar 122 and the underlying fin material.
[0039] The pattern defined by the aperture 140 in the filler material layer 130 may then be transferred into the fin 20 to form the nanopore 10. An example of the resulting device is illustrated in FIG. 1E, depicting the semiconductor fin 20 when provided with the nanopore 10 extending in a top-bottom direction of the fin 20. The nanopore 10 is self-aligned in the width direction of the fin 20. The self-alignment is achieved due to the use of the sacrificial pillar 122 which is formed of the top layer 120 of the fin structure 100. The resulting fin 20 has a filler material formed thereover, and the nanopore 10 is formed in a vertical direction through the filler layer 130 and further through the semiconductor fin, such that the nanopore 10 exposes a surface of the underlying substrate 180. The illustration in FIG. 1E may also represent a final device.
[0040] The above-described example method of forming the nanopore may be varied in several ways, using different material combinations, material layers and processing steps. An example of such variation will now be discussed with reference to FIGS. 2A-2E. It will be appreciated that the depicted examples may be similarly configured as the embodiments described above in connection with FIGS. 1A-1E.
[0041] FIG. 2A shows a cross-sectional side view of an intermediate structure including a fin structure 200. The fin structure 200 comprises a bottom layer 210 formed of. for example Si, arranged on a substrate comprising a dielectric layer 284, such as for example SiO.sub.2, and a Si layer 286. The bottom layer 210, the dielectric layer 286 and the Si layer 282 may in some examples be formed from a silicon-on-insulator (SOI) wafer.
[0042] The fin structure 200 may further comprise a first mask material 224 and a second mask material 226, which together may form the top layer 220 of the fin structure 200. The first mask material 224 may be arranged between the bottom layer 210 and the second mask material 226 so as to form an interface between the top layer 220 and the bottom layer 210. In this way, the top layer 210 may be referred to as a dual mask. The first mask material 224 may in some examples be or comprise a dielectric such as SiO.sub.2, Si.sub.3N.sub.4, SiOC or SiON. The second mask material 226 may be or comprises amorphous Si, TiN, Si.sub.3N.sub.4, SiO.sub.2, SiOC or SiON, depending on the type of material used in the first mask 224. Preferably, the first and second mask materials 224, 226 are selected such that the combination allows for an etch selectivity between the materials, which advantageously allows for the first mask material 224 to serve as an etch stop layer during the formation of the pillar 222. In the present example, the first mask material is or comprises SiO.sub.2 and the second mask material is or comprises amorphous Si.
[0043] The the pillar 222 (FIG. 2C) is formed using the top layer, and in this example the second mask material 226, to be patterned into the desired structure. The patterning may, for example, be performed by means of a lithography and etching. For this purpose, a hard mask formed of, for example, spin-on-carbon (SoC) and spin-on-glass (SoG) may be used (not shown). Alternatively, a dielectric anti-reflective coating (DARC, e.g., SiOC) may be provided on an advanced patterning film (APF, e.g., a carbon film) stack. Photoresist may be employed to pattern the SoC and SoG layers into a line mask 250 that can be used when cutting the second mask material 226 of the fin structure 200 into a self-aligned pillar or dot structure, using the first mask material 224 as an etch stop.
[0044] FIG. 2B shows a top view of an intermediate structure including the fin structure 200 of FIG. 2A, in which the line mask 250 crosses the fin structure 200 in a substantially orthogonal manner.
[0045] A perspective view an intermediate structure including the fin structure 200 is shown in FIG. 2C. The fin structure 200 comprises a fin 20 formed of the bottom layer 210, a pillar 222 arranged on top of the fin 20, and the etch stop layer 224 arranged in between. FIG. 2C indicates that the etch stop layer 224 has been slightly etched back during the forming of the pillar 222. It will be appreciated that in some implementations, the pillar 222 may be formed without the intermediate etch stop layer 224, e.g., formed from a stack comprising the bottom layer 210 and the top layer (e.g., the second mask material 226 or the top layer 120 (FIG. 1A)). In that case, it might be advantageous to use a slightly thicker bottom layer so as to compensate for possible etch back effects.
[0046] FIG. 2D is a cross sectional side view of an intermediate structure or a final device including the fin shown in FIG. 2C, after the pillar 222 has been embedded in the filler material 230 and replaced by the aperture 240. As also shown in FIG. 2D, the aperture 240 may be lined with a spacer material 260 provided by for example oxidation or ALD. The spacer material 260 may be added so as to reduce the diameter of the aperture 260 and thereby enable a smaller nanopore 10 to be formed in the fin 20. Even though not shown in the present cross section, the spacer material 260 may be provided on all sidewalls of the aperture 240, which hence may have a width or diameter that is smaller than the width of the fin 20. This allows for the nanopore 10 to be etched through the fin material without breaking through the sidewalls of the fin 20. The spacer material 260 may for example be a dielectric such as SiO.sub.2, Si.sub.3N.sub.4, SiOC, TiO.sub.2, ZrO.sub.2 or HfO.sub.2 or a metal such as TiN, TaN or AlN.
[0047] FIG. 2E is a cross sectional top view of an intermediate structure or a final device including the fin 20 shown in FIG. 2D, taken along the section A-A. As shown in FIG. 2E, the nanopore may be centrally located in the width direction of the fin 20, allowing a polymer such as, e.g., a DNA or RNA strand to pass through the fin and thereby form a channel between the drain region 22 and the source region 24 of the fin 20. In the present example, the fin 20 may have a width of about 10 nm and a height of about 10 nm to about 20 nm. The nanopore 10 may in the present example have a width of about 5 nm. Thus, in the illustrated embodiment, a lateral dimension of the nanopore in a width direction of the semiconductor fin is smaller than the width of the fin, such that the nanopore is laterally confined within the semiconductor fin. The resulting nanopore 10 in the illustrated embodiment is arranged such that a portion of the nanopore formed through the filler material 230 is lined with a spacer material 260, while the spacer 260 material does not extend into a portion of the nanopore 10 formed through the fin 20.
[0048] FIG. 3 illustrates a semiconductor fin 20 according to another example. The semiconductor fin 20 may be similarly configured as the previously described embodiments, but differ in that the nanopore 10 is provided with a tapered or funnel shaped profile. As shown in FIG. 3, the opening 10 may decrease towards the base of the fin 20. This tapered profile may for example be achieved by a reactive ion etch (RIE) process, in which etching is cycled with sidewall passivation. Alternatively, or additionally an anisotropic wet etch, such as, e.g., orientation dependent potassium hydroxide (KOH) etch of Si, may be employed to provide a V-shaped profile of the opening 10.
[0049] Further, the nanopore 10 may be provided with a spacer material 270 lining, e.g., conformally lining, the sidewalls of the nanopore 10. The spacer material 270 may be similar to the one used for the aperture 140, and allows for the diameter of the pore 10 to be even further decreased.
[0050] FIG. 4 is a flowchart illustrating a method according to embodiments described above. The method may comprise the steps of providing S10 a fin structure comprising at least a bottom layer and a top layer, patterning S20 the top layer to form a pillar, laterally embedding S30 the pillar in a filler material, forming S40 an aperture in the filler material by removing the pillar, and forming S50 the nanopore in the bottom layer by etching through the aperture. The patterning S20 the top layer to form a pillar may include a self-aligning S22 of the pillar using a line mask. Further, the aperture may be lied S42 with a spacer material to reduce the size of the aperture and hence the nanopore. This also applies to the nanopore itself, which may be lined S54 with the same or a similar material. In some embodiments, the nanopore additionally, or alternatively, may be provided with a tapered S52 profile so as to allow for an even smaller pore diameter to be achieved.
[0051] In the above the inventive concept has mainly been described with reference to a limited number of examples. However, as is readily appreciated by a person skilled in the art, other examples than the ones disclosed above are equally possible within the scope of the inventive concept, as defined by the appended claims.
