Field-Effect Transistors (FETs)

Abstract

The present invention improves the linearity characteristics of a transistor, namely the input/output intercept points (IIP3/OIP3) and intermodulation distortion (IM3), while maintaining a high transconductance and high electron velocity in the conducting channel. The present invention also improves the manufacturability, yield, and immunity to bias-point drift, of a linear transistor. In one embodiment, the present invention implements triple pulse doping or even higher pulse doping for immunity to process variation as well as low parasitic leakage. In an alternative embodiment, the present invention implements a bilinear V-shaped composition grading for engineering the I.sub.D-V.sub.GS curve for high OIP3. In another alternative embodiment, the present invention implements a quadratic or U-shaped composition grading for engineering the I.sub.D-V.sub.GS curve for high OIP3.

Claims

1. A field-effect transistor (FET) comprising: a substrate; a back barrier disposed on the substrate; a channel disposed on the back barrier, the channel composed of an alloy and having a non-uniform gradation in an alloy composition profile; and a front barrier disposed on the channel.

2. The FET of claim 1, wherein the channel is composed of the alloy having a plurality of constituent elements whereby a composition in the alloy of at least one of the constituent elements is alloy-compositionally graded to cause a plot of the composition as a function of depth to have a V-shape.

3. The FET of claim 1, wherein the channel is composed of the alloy having a plurality of constituent elements whereby a composition in the alloy of at least one of the constituent elements is alloy-compositionally graded to cause a plot of the composition as a function of depth to have a piecewise-linear shape, with the piecewise-linear shape having different slopes in different segments of the plot.

4. The FET of claim 1, wherein the channel is composed of the alloy having a plurality of constituent elements whereby a composition in the alloy of at least one of the constituent elements is alloy-compositionally graded to cause a plot of the composition as a function of depth to have a U-shape.

5. The FET of claim 1, wherein the channel is composed of the alloy having a plurality of constituent elements whereby a composition in the alloy of at least one of the constituent elements is alloy-compositionally graded to cause a plot of the composition as a function of depth to have a plurality of piecewise-curved shapes.

6. The FET of claim 1, wherein the channel is composed of the alloy having a plurality of constituent elements whereby a composition in the alloy of at least one of the constituent elements is alloy-compositionally graded to cause a plot of the composition as a function of depth to have a parabola shape.

7. The FET of claim 1, wherein the channel is composed of the alloy having a plurality of constituent elements whereby a composition in the alloy of at least one of the constituent elements is alloy-compositionally graded to cause a plot of the composition as a function of depth to have a hyperbolic-cosine shape.

8. (canceled)

9. The FET of claim 1, wherein the FET has a non-constant linear g.sub.m1 as a function of gate voltage.

10. The FET of claim 1, wherein the substrate includes growth buffers for clean, dislocation-free growth.

11-12. (canceled)

13. The FET of claim 1, wherein at least one of the front barrier and the back barrier is composed of a semiconducting material.

14. The FET of claim 1, wherein at least one of the front barrier and the back barrier is composed of an insulating oxide.

15. The FET of claim 1, wherein the FET is an enhancement-mode device having a positive threshold voltage.

16. The FET of claim 15, wherein the FET is a high-electron mobility transistor (HEMT).

17. The FET of claim 1, wherein the FET is a depletion-mode device having a negative threshold voltage.

18. The FET of claim 1, wherein carriers of electric current in the channel are selected from electrons and electron holes.

19. The FET of claim 1, wherein the channel is doped, and the channel is depleted by applying a voltage opposite in polarity to ionized impurities in the FET.

20. The FET of claim 19, wherein the FET is selected from a hetero-junction device, a metal-semiconductor FET (MESFET), and a heterostructure FET (HFET).

21. A field-effect transistor (FET) comprising: a substrate; a back barrier disposed on the substrate; a channel disposed on the back barrier, the channel composed of an alloy and having a non-uniform gradation in an alloy composition profile; a front barrier disposed on the channel; a first transistor terminal disposed on the front barrier; a first conducting member and a second conducting member disposed on the front barrier with each of the first and second conducting members spaced from the first transistor terminal and spaced from each other; a second transistor terminal disposed on the first conducting member; a third transistor terminal disposed on the second conducting member; a first pulse-doping layer disposed within the front barrier; and a second pulse-doping layer disposed within the back barrier.

22. The FET of claim 21, wherein the substrate includes growth buffers for clean, dislocation-free growth.

23. A method of fabricating a field-effect transistor (FET), the method comprising: disposing a back barrier on a substrate; disposing a channel on the back barrier, the channel composed of an alloy and having a non-uniform gradation in an alloy composition profile; and disposing a front barrier on the channel.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The foregoing summary, as well as the following detailed description of presently preferred embodiments of the invention, will be better understood when read in conjunction with the appended drawings. For the purpose of illustrating the invention, there are shown in the drawings embodiments which are presently preferred. It should be understood, however, that the invention is not limited to the precise arrangements and instrumentalities shown.

[0031] In the drawings:

[0032] FIG. 1A is a cross-sectional view of a field-effect transistor implementing an HEMT in the prior art;

[0033] FIG. 1B is a conduction band profile taken horizontally across the device in FIG. 1A for a low gate voltage;

[0034] FIG. 1C is a conduction band profile taken horizontally across the device in FIG. 1A for a high gate voltage;

[0035] FIG. 1D is a conduction band profile taken vertically through the center of the device in FIG. 1A;

[0036] FIG. 1E is a material composition profile taken vertically through the center of the device in FIG. 1A;

[0037] FIG. 2A is a graph of I.sub.D vs. V.sub.GS of the device in FIG. 1A;

[0038] FIG. 2B is a graph of g.sub.m1 and g.sub.m3 vs. V.sub.GS of the device in FIG. 1A;

[0039] FIG. 2C is a graph of OIP3 vs. V.sub.GS of the device in FIG. 1A;

[0040] FIG. 3 is a FET with back barrier pulse doping in the prior art;

[0041] FIG. 4A is a FET with a heavily doped spacer in the prior art;

[0042] FIG. 4B is a conduction band energy diagram of the FET in FIG. 4A;

[0043] FIG. 5A is FET having a double-delta doped structure in the prior art;

[0044] FIG. 5B is a FET having a uniformly doped channel in the prior art;

[0045] FIG. 5C is a FET having a uniformly doped barrier in the prior art;

[0046] FIG. 6 is a FET having a triple-pulse doped structure of the present invention;

[0047] FIG. 7A is a graph of I.sub.D vs. V.sub.GS for the FET in FIG. 6;

[0048] FIG. 7B is a graph of g.sub.m1 and g.sub.m3 vs. V.sub.GS for the FET in FIG. 6;

[0049] FIG. 7C is a graph of OIP3 vs. V.sub.GS for the FET in FIG. 6;

[0050] FIG. 7D is a material composition profile for the FET in FIG. 6;

[0051] FIG. 7E is a CB energy profile for the FET in FIG. 6;

[0052] FIG. 8A is a material composition profile for an inventive V-graded structure;

[0053] FIG. 8B is a CB energy profile for the inventive V-graded structure of FIG. 8A;

[0054] FIG. 8C is a graph of I.sub.D vs. V.sub.GS for the inventive V-graded structure of FIG. 8A;

[0055] FIG. 8D is a graph of OIP3 vs. V.sub.GS for the inventive V-graded structure of FIG. 8A;

[0056] FIG. 9A is a material composition profile for an inventive U-graded structure;

[0057] FIG. 9B is a CB energy profile for the inventive U-graded structure of FIG. 9A;

[0058] FIG. 9C is a graph of I.sub.D vs. V.sub.GS for the inventive U-graded structure of FIG. 9A; and

[0059] FIG. 9D is a graph of OIP3 vs. V.sub.GS for the inventive U-graded structure of FIG. 9A.

[0060] To facilitate an understanding of the invention, identical reference numerals have been used, when appropriate, to designate the same or similar elements that are common to the figures. Further, unless stated otherwise, the features shown in the figures are not drawn to scale, but are shown for illustrative purposes only.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0061] Certain terminology is used in the following description for convenience only and is not limiting. The article a is intended to include one or more items, and where only one item is intended the term one or similar language is used. Additionally, to assist in the description of the present invention, words such as top, bottom, upper, lower, front, rear, inner, outer, right and left may be used to describe the accompanying figures. The terminology includes the words above specifically mentioned, derivatives thereof, and words of similar import.

[0062] The present application focuses on compound/alloy semiconductors (e.g. group-III arsenides/phosphides, silicon-germanium etc.) that do not exhibit any/significant polarization-induced charge upon grading the elemental composition. In such semiconductors, the simple artifice of linearly grading the composition over the channel depth, as done in the prior art such as in Park et al., does not affect linearity.

[0063] The present application also focuses on bias points much closer to the threshold voltage, as shown in FIG. 7A-B where g.sub.m1 is not necessarily constant, but where g.sub.m3 is low so that OIP3 increases above 35 dBm. As mentioned herein, biasing where g.sub.m is constant results in noise, power efficiency and thermal issues. Large peaks in OIP3 can be expected if the FET is designed for g.sub.m1 linear with V.sub.GS and (hence) zero g.sub.m3, even if g.sub.m1 is not constant or especially large, and this will be a strategy for improving OIP3.

[0064] In a first embodiment, the present invention implements triple-pulse doping for increased yield of linear HEMTs. FIG. 6 shows the inventive structure with three delta-doped (pulse doped) layers, two in the back-barrier and one in the front. As shown in FIG. 6, the HEMT 60 has a source 62, a gate 64, a drain 66, conducting caps 68, a front barrier 70, a first pulse-doping layer 72, a channel 74, and a back barrier 76 formed on a substrate 78. The substrate may optionally include growth buffers for clean, dislocation-free growth. Two delta-doped layers 80, 82 are incorporated within the back barrier 76.

[0065] The concentration of intentional impurities (dopants) in the three pulses can be chosen so as to give a pronounced peak in OIP3 vs V.sub.GS. FIG. 7A and FIG. 7B show an I.sub.D vs V.sub.GS profile and an OIP3 peak for an instance of the inventive structure. The OIP3 peak, although tall, is rather narrow; for example, the width over which OIP3>40 dBm is about 50 millivolts.

[0066] The triple-pulse doping of the present invention may be implemented either by metalorganic chemical vapor deposition (MOCVD), or by molecular beam epitaxy (MBE). Any growth technique capable of achieving monatomic resolution will work, with MOCVD and MBE providing high resolution.

[0067] Ideally, the characteristics of the triple-pulse-doped structure could theoretically be exactly replicated with the prior art double-pulse doped structure of FIG. 3, with one pulse in each barrier, and with distance from the channel and impurity concentration chosen appropriately. In reality, however, fabrication methods cannot manufacture large numbers of HEMTs all having precisely the same areal concentration of impurities. Manufacturing process variation on the areal delta-doping concentration can be modelled as a Gaussian distribution with standard deviation a fixed factor f (e.g. f=10%) times the expected (nominal, average, mean) value :

{square root over (.sup.2)}=f(6)

[0068] The inventive triple-pulse doped structure of the present invention provides immunity against statistical fluctuations in impurity concentrations, resulting in higher manufacturing yield, as demonstrated herein. For many material growth techniques, such as MOCVD, f=0.2 is a typical stringent specification, meaning the statistical variation is +/10% of the average concentration.

[0069] It can be shown by the Poisson's equation of electrostatics that the FET electrical characteristics depend, not on the detailed distribution of impurities in the back-barrier, but instead on a lumped quantity: the so-called dipole moment P of the distribution

P=.sub.0.sup.d.sup.Bdx(d.sub.Bx)N(x)(7)

[0070] Here, N(x) is the volume concentration of charged impurities at a distance x from the channel-to-back-barrier interface, and d.sub.B is the back-barrier thickness. For two Gaussian pulses in the back barrier of net areal concentration .sub.1 and .sub.2, with respective peaks at a distance d.sub.1 and d.sub.2 from the interface:

P=(d.sub.Bd.sub.1).sub.1+(d.sub.Bd.sub.2).sub.2(8)

[0071] Assuming the statistics of .sub.1 and .sub.2 are described by Gaussian distributions, assuming equal factors f={square root over (.sup.2)}/ for each, it is well known that the standard deviation in the dipole moment P is given by:

[00004]$\begin{array}{cc}\sqrt{P^2}=f.Math.\sqrt{{\left(d_B-d_1\right)}^2.Math.{}_1^2+{\left(d_B-d_2\right)}^2.Math.{}_2^2+2.Math.{}_1.Math.{}_2\left(d_B-d_1\right).Math.\left(d_B-d_2\right).Math.{}_{12}}& \left(9\right)\end{array}$

where .sub.12 is the correlation coefficient between the two delta-doping concentrations, with 1.sub.12+1. The lower the correlation coefficient, the lower the standard deviation in the dipole moment. It may be shown that:

[00005]$\begin{array}{cc}\sqrt{{\left(d_B-d_1\right)}^2.Math.{}_1^2+{\left(d_B-d_2\right)}^2.Math.{}_2^2+2.Math.{}_1.Math.{}_2\left(d_B-d_1\right).Math.\left(d_B-d_2\right).Math.{}_{12}}P& \left(10\right)\end{array}$

[0072] This yields the central result for the triple delta doped structure of the present invention:

{square root over (P.sup.2)}fP(11)

[0073] For a double-pulse-doped HEMT, with single doping layer in the back-barrier, the standard deviation {square root over (P.sup.2)} is by definition exactly the factor f times the mean value <P>. Thus, for the same nominal value of the dipole moment P, and hence the same nominal electrical characteristics, the triple-pulse doped structure always shows less statistical variation, and therefore higher manufacturing yield, than the two-pulse doped structure.

[0074] By modeling or measuring the statistical correlation between the concentration of the pulses, the standard deviation {square root over (P.sup.2)} can be minimized, either numerically or analytically using, for example, the method of the Lagrange multiplier. This would help to design the triple-pulse doped structure with design variables .sub.1, .sub.2, d.sub.1 and d.sub.2, that for given nominal electrical characteristics, represented by a fixed (P), has the highest yield mathematically possible.

[0075] An important feature of the triple delta doped barrier is that high linearity devices may be achieved with high manufacturing yield without the risk of current leakage through the back barrier. This risk is carried by uniformly doped barriers (front or back) as in the prior art, such as shown in FIG. 5C, where the uniform doping is in the front-barrier. By contrast, in the inventive triple-pulse doped device of the present invention, the two pulses can be placed far enough apart from each other that their profiles do not overlap, thus eliminating leakage paths from forming between the pulses.

[0076] In an alternative embodiment, the present invention includes an alloy-composition graded channel for FET devices with broad and tall OIP3 peaks. Upon examination of the respective g.sub.m3 and OIP3 profiles shown in the present invention in FIGS. 7B and 7C, as well as for prior art structures such as shown in FIG. 2B-2C, it is observed that the triple-pulse doped structure exhibits a zero-crossing of g.sub.m3, while the prior-art HEMT has no zero-crossings apart from at the threshold gate voltage. It is this zero-crossing that results in high OIP3 for the triple-pulse device, according to the basic equations disclosed herein. Alloy composition-graded channels may be used to even further refine the position and enlarge the width of the OIP3 peaks through engineering of these zero-crossings, as described later.

[0077] The alloy-compositional grading may be implemented either by MOCVD or by Molecular Beam Epitaxy (MBE). Any growth technique capable of achieving monatomic resolution will work, with MOCVD and MBE providing high resolution.

[0078] In order to grade the alloy composition during MOCVD growth, the flow rates of the source gases, such as trimethyl indium or TMI, are varied with time by computerized control of the mass-flow controller valves. The computer varies the gas flow rates according to a previously established calibration curve for composition vs. flow rate.

[0079] Alternatively, during MBE growth, sources containing constituent elements, such as indium, gallium, etc., are contained in separate cells that are heated to the boiling point of the respective source. The alloy composition is varied during growth by computerized control of the heater temperature, and hence the vapor pressure, of each source according to a previously established calibration curve for alloy composition vs temperature. Another method available to the computer controlling the growth is to open and close a shutter in front of each source leading to the growth chamber. A sequence of steps for opening and closing the source shutters maybe programmed into the controller, in a manner known in the art, for precise monatomic layer control over the alloy composition.

[0080] Conduction band profiles for the prior art in FIG. 1D, and the triple-pulse doped HEMT of the present invention in FIG. 7E, respectively, show the point in the channel where the CB edge energy is closest to the chemical potential reference. As discussed earlier, this is the point where electrons tend to pool and are at their highest concentration. When conduction begins, the prior art devices described in FIG. 1A have the highest electron concentration near the front of the channel, while the triple-pulse doped device of the present invention, or the nominally equivalent double-doped device of the prior art of FIG. 3, shows peak electron concentration towards the back of the channel.

[0081] By spreading out the onset of conduction amongst various points in the channel, rather than restricting conduction to the front of the channel, the device linearity improves. In the inventive device described herein, this insight for improving linearity is used to sculpt the I.sub.D-V.sub.GS curve in such a manner as to exhibit the desired derivatives g.sub.m1 and g.sub.m3.

[0082] One way to alter the depth profile of electron concentration in the channel is by altering the elemental composition profile either gradually, such as by alloy-compositional grading, or abruptly such as by forming heterojunctions. The following inventive non-uniform-alloy-compositional structures increase the width of the OIP3 peak, thus rendering the HEMT linear over a larger input voltage swing.

[0083] In one embodiment, a bi-linear V-graded channel is formed, as shown in FIGS. 8A-8B, which illustrate the composition vs. depth and CB energy profile vs, depth, respectively, of an exemplary inventive device, an Al.sub.0.3Ga.sub.0.7As barrier/InGaAs channel/Al.sub.0.3Ga.sub.0.7As back-barrier/GaAs substrate HEMT. The indium content of the InGaAs channel is alloy-compositionally graded linearly up from about 20% to about 35% indium over the first half of the channel, and then down from about 35% back to about 20% indium over the second half.

[0084] As shown in FIG. 8B, a notch in the conduction band profile is formed near the center of the channel. Here the band energy is minimum, and electrons tend to accumulate here at the onset of a threshold gate voltage. As the gate voltage increases, the back of the channel also begins contributing to the drain current, followed eventually by a rapid and uniform increase of current as the front of the channel becomes involved. FIGS. 8C-8D show that, by thus spreading the onset of conduction, the OIP3 peak broadens considerably, so that the width over which OIP3 is >40 dBm is now about 85 millivolts.

[0085] In an alternative embodiment, a bi-quadratic U-graded channel is formed. FIGS. 9A-9B show the composition and CB energy profile vs position, that is, depth, of an exemplary inventive device, an Al.sub.0.27Ga.sub.0.73As barrier/InGaAs channel/Al.sub.0.27Ga.sub.0.73As back-barrier/GaAs substrate HEMT. The indium content of the InGaAs channel is alloy-compositionally graded quadratically, to form a parabolic or U-shape, as a function of position up from about 10% to about 20% indium over the first half of the channel, and then quadratically down from about 20% back to about 10% indium over the second half.

[0086] A minimum in CB energy is formed within the channel, as illustrated in FIG. 9B, where electrons tend to accumulate at the onset of a threshold gate voltage. As the gate voltage increases, the remainder of the channel, between the CB minimum point within the channel and the back surface of the channel, progressively begins contributing to the drain current, followed eventually by a rapid increase of current as the front of the channel becomes involved.

[0087] FIGS. 9C-9D show that, by thus spreading the onset of conduction, the OIP3 peak broadens even more pronouncedly, such that the width over which OIP3 is >40 dBm is about 0.12 Volts. The smooth grading scheme of this inventive device results in the drain current turning on more smoothly with increasing V.sub.GS, which translates to values of g.sub.m3 close to zero, and high OIP3, over a wide range of gate voltages V.sub.GS.

[0088] The broadening of the OIP3 peak in these inventive devices means that the device performance is more immune to manufacturing process variations that might wash out narrower peaks. The broad peaks also mean that the HEMT remains linear under any drift in bias point caused, for example, by changing device temperature. The use of compositional grading within the channel instead of doping preserves high electron velocity v.sub.sat.

[0089] Thus, the present invention improves the linearity characteristics of a transistor, namely the input/output intercept points (IIP3/OIP3) and intermodulation distortion (IM3), while maintaining a high transconductance (g.sub.m1) and high electron velocity (v.sub.sat) in the conducting channel. The present invention also improves the manufacturability, yield, and immunity to bias-point drift, of a linear transistor.

[0090] In one embodiment, the present invention implements a bilinear V-shaped composition grading for engineering the I.sub.D-V.sub.GS curve for high OIP3. In an alternative embodiment, the present invention implements a quadratic U-shaped composition grading for engineering the I.sub.D-V.sub.GS curve for high OIP3. In another alternative embodiment, the present invention implements triple pulse doping or even higher pulse doping for immunity to process variation as well as low parasitic leakage.

[0091] The present invention has a broader OIP3 peak with graded channels than uniform, for larger signal operation. The present invention has broader OIP3 peak with graded channels than uniform, for more room for process variation, bias-point temperature drift. The present invention has less variation of linearity with doping, hence higher yield, in triple-pulse doping over 2-pulse doping. The present invention has no leakage through barrier with 2 back pulses in a barrier, unlike a uniformly doped barrier as in the prior art. The present invention has U and V grading schemes which work even with non-polar III-Vs and even with SiGe, unlike linearly graded AlGaN as in the prior art. The present invention has high electron mobility preserved by grading, unlike heavily doped GaN spacer/uniformly doped channel as in the prior art.

[0092] In alternative embodiments, the present invention also includes piecewise linear or curved grading, such as quadratic grading or generally any arbitrary non-uniform piecewise linear or curved grading scheme, in which linearity of the operation of a FET is improved by spreading charge into spatially successive potential wells. In the alternative embodiments, the present invention includes several possible variants on the idea of composition grading for linearity, including but not limited to symmetric V-shaped and U-shaped grading profiles. For example, the present invention also includes asymmetrical V-shaped and U-shaped grading by having asymmetric piecewise curves, and grading according to any arbitrary curve, such as the hyperbolic cosine function, cos h(x). In addition, the present invention includes having more than two grades back-to-back, that is, piecewise linear and/or piecewise-quadratic grading, or combinations thereof.

[0093] Since there is an infinity of ways in which one can spatially vary the channel composition, with linear, quadratic, and hyperbolic cosine being merely three examples, the present invention includes any scheme for grading the channel that bestows linearity by spreading the channel charges spatially into one or more successive notches or wells formed by the compositional grading of the channel.

[0094] In further alternative embodiments, other types or flavors of FETs are fabricated using the linear or quadratic compositional grading as described herein. Bilinear and biquadratic compositional grading schemes are versatile and may be used to improve linearity in a large number of flavors of transistors other than HEMTs that operate based on the same physical principle, namely the field effect. These include but are not limited to: HEMT variants where the barrier semiconductor is replaced with an insulating oxide; enhancement-mode HEMTs that have a positive threshold voltage rather than the depletion-mode negative threshold devices used for illustrating the concept in this application; hole-channel FETs where the carriers of electrical current are holes rather than electrons, with grading of the valence band in which holes reside may be accomplished completely analogously to CB grading; and types or flavors of FETs that deplete a doped channel, i.e. a pre-existing bridge between the source and drain by applying a voltage opposite in polarity to the ionized impurities (dopants), which include Hetero-Junction (HFET/JFET) and Metal-Semiconductor (MESFETs), which have a good linearity to begin with, although the mobility and speed are lower than, for example, HEMTs. The grading schemes of the present invention work with doped channels as well as undoped, so the inventive grading schemes may be used to further improve the linearity figures of merit, without further impacting electron/hole mobility. This is especially true of operational bias levels where g.sub.m1 is not yet constant with V.sub.GS.

[0095] The present invention may be embodied in other specific forms without departing from its spirit or essential characteristics. The described embodiments are to be considered in all respects only as illustrative and not restrictive. The scope of the invention is, therefore, indicated by the appended claims rather than by the foregoing description. All changes which come within the meaning and range of equivalency of the claims are to be embraced within their scope.