Technique for improving efficiency of on-chip antennas

Abstract

Technique for improving efficiency of on-chip antennas, comprising placing each antenna on an individual area on the chip, defined by channels provided in the chip before or after placing the antenna(s). The channels may be metallized. Frequency of a radiating antenna element may be locked by wireless injection locking using a locked subharmonic frequency.

Claims

1. An antenna chip, comprising one or more antenna elements placed on an insulating board and capable of radiating and/or receiving frequency, wherein each of said antenna elements is positioned on its individual area on the board, wherein each said individual area is defined by channels provided in the insulating board, wherein the channels are separate from the antenna element, and wherein said insulating board is a silicon substrate.

2. An antenna chip, comprising one or more antenna elements placed on an insulating board and capable of radiating and/or receiving frequency, wherein each of said antenna elements is positioned on its individual area on the board, wherein each said individual area is defined by channels provided in the insulating board, and wherein said frequency is around the THz gap.

3. The antenna chip according to claim 2, wherein said antenna elements are placed on a front surface of the substrate, and wherein said channels are diced in the back surface of the board and filled with a conductive material.

4. The antenna chip according to claim 2, wherein said channels are formed using Through Substrate Vias (TSV) provided in the substrate.

5. The antenna chip according to claim 2, wherein said individual area is an optimal area being such that for an antenna element being provided with said optimal area in said array, gain remains non-degraded in operation.

6. The antenna chip of claim 2, wherein said channels are metallized.

7. The antenna chip according to claim 2, wherein said antenna element on the board is manufactured by 65 nm CMOS technology.

8. The antenna chip according to claim 3, wherein said channels are metallized by a conductive glue.

9. The antenna chip according to claim 2, comprising a 2D, 23 array of said antenna elements capable of radiating 0.3 THz frequency and provided by 65 nm CMOS on a front surface of a chip, wherein said area being divided into individual areas, for each of said antenna elements, by trenches provided on a back surface of the board and filled by a conductive material.

10. The antenna chip according to claim 2, said antenna elements comprise an antenna element being a transmitter with a THz antenna adapted to receive an external subharmonic frequency from an external source, wherein dimensions of the individual area of said transmitter approximately correspond to cross-section of a beam radiated by said external source, while received at the individual area.

11. A method of manufacturing the antenna chip according to claim 2, the method comprising a step of providing, on the insulating board, one or more said antenna elements capable of radiating and/or receiving frequency, and a step of providing the channels in the insulating board so as to define by said channels said respective individual area on the insulating board for each of said antenna elements.

12. A system for locking a signal of THz transmitting frequency, said system comprising: an antenna element being a transmitter with a THz antenna adapted to receive an external subharmonic frequency, wherein said system is configured to perform wireless injection locking in said transmitter by said external frequency being locked and being subharmonic in respect of the transmitting THz frequency of the transmitter; and wherein the system thereby ensures locking of said transmitting THz frequency of said transmitter.

13. The system according to claim 12, wherein said system is configured for locking the transmitting THz frequency of the transmitter, being THz gap frequency.

14. The system according to claim 12, further comprising an external source of the locked subharmonic frequency.

15. The system according to claim 12, comprising: the antenna element being the transmitter provided with the THz antenna and being configured for: producing at least a first frequency of N THz, and receiving a second, subharmonic frequency of N/n THz, wherein n is natural; transmitting a third frequency being equal to or higher than the first frequency, wherein the external source is configured for emitting a locked frequency of N/n THz being equal to the second frequency of the transmitter; wherein the transmitter and the source are arranged in space so that whenever being initiated, the transmitter is exposed to radiation of the source, and thus is subjected to wireless injection locking at its second frequency of N/n THz, thereby one or more frequencies of the transmitter become locked due to the locked second frequency; the first transmitter is thereby enabled to output at least said third locked frequency being said transmitting THz frequency.

16. The system according to claim 12, wherein the transmitter is a CMOS VCO, and the THz antenna is an on-chip ring antenna directly connected to the VCO.

17. The system according to claim 12, comprising an array of two or more of said antenna elements.

18. The system according to claim 17, wherein a distance between adjacent antenna elements in said array is in the range of about (0.5-2.0) of the subharmonic or fundamental frequency wavelength.

19. A method for locking signals of THz frequency using the system according to claim 12, the method comprising: providing said system comprising the antenna element being a transmitter with the THz antenna adapted both to transmit a THz transmitting frequency, and to receive an external frequency being subharmonic in respect of said THz transmitting frequency; providing said external locked frequency, and performing the wireless injection locking of the transmitter by subjecting said THz antenna to said external locked frequency, thereby obtaining said THz transmission frequency locked.

20. A THz frequency antenna element configured for transmitting and receiving THz gap frequencies, and manufactured by a CMOS technology, comprising a transmitter having a VCO topology and being directly connected to an antenna.

21. The antenna element according to claim 20, wherein the antenna is configured for at least a two-fold function comprising: receiving a subharmonic frequency for performing wireless injection locking of the transmitter; and transmitting a working frequency being a superharmonic working frequency with respect to said subharmonic locked frequency.

22. The antenna element according to claim 20, wherein the antenna is configured to operate in the following two regimes depending on the frequency: at the subharmonic frequency, the antenna is an inductor and acts as an RF-choke; at the transmitting frequency, the antenna works as a matched resistive antenna.

23. The antenna chip according to claim 2, wherein the antenna element is a THz frequency antenna element manufactured by a CMOS technology and comprising an antenna directly connected to a transmitter having a VCO topology.

24. The antenna chip according to claim 2, wherein said antenna element comprises a transmitter connected to an antenna, and wherein said antenna element is adapted to perform a wireless injection locking of its transmitter by using an external locked frequency being subharmonic of a desired THz transmitting frequency of the transmitter, thereby obtaining said THz transmitting frequency locked.

25. The system for locking a signal of THz transmitting frequency according to claim 12, wherein said antenna element being placed within its individual area defined on an insulating board by channels provided in the insulating board.

26. The system according to claim 25, wherein said antenna element is part of an array of similar antenna elements each positioned on its individual area defined by said channels provided in the insulating board and metallized.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The invention will be explained and illustrated below, with the aid of the following non-limiting drawings in which:

(2) FIG. 1a shows an insulation board that carries a net of channels (such as trenches or dices) provided in the board and separating it into individual areas for antennas of a 2D array.

(3) FIG. 1b shows an example of implementation of a radiating source as an antenna element comprising a transmitter, which may be used as a pixel of a radiating array.

(4) FIG. 1c shows an exemplary implementation of a low cost 2D scalable THz Array, where antenna elements are separated by the trenches/dices provided in the silicon substrate. FIG. 1c also depicts that antennas of the array are wirelessly lockable according to the invention.

(5) FIGS. 2a, 2b illustrate how metal plated trenches may be provided in a silicone substrate around an antenna element, and how it changes Gain of the antenna.

(6) FIGS. 3a-c show a specific implementation of the antennas array (23), with corresponding parameters achieved by using the proposed trench/dicing technology.

(7) FIGS. 4a, b present scans showing Power of a single antenna, and Power of an array of 23 antennas.

(8) FIGS. 4c, shows a graph of EIRP as a function of frequency for a single antenna and an array of 23 antennas.

(9) FIG. 4d shows a graph of EIRP/TRP as a function of number of antennas in the array.

(10) FIGS. 5a and 5b are micrographs of an exemplary chip with an array of 23 sources, provided with diced trenches isolating the sources. FIGS. 5a and 5b give exemplary dimensions of the array and the trenches.

(11) FIGS. 6 a, b, c, present schematic block diagrams illustrating:

(12) an exemplary implementation of the proposed subharmonic wireless injection locking (FIG. 6b) in comparison with a known approach (FIG. 6a), and an example of performing mutual subharmonic locking in an array (FIG. 6c).

(13) FIG. 7 shows the measurement results of the EIRP and of tuning range against the control Gate bias voltage in the proposed THz transmitter.

DETAILED DESCRIPTION OF SPECIFIC EMBODIMENTS

(14) The proposed new approach comprises mechanical/electrical isolation of any antenna elements in an array and locking transmitting frequencies of antenna elements comprising transmitters, performed separately or together. While being useful for any technologies and frequencies, the approach is especially advantageous for technologies such as CD, SIGE, for all CMOS process nodes (for example, 65 nm CMOS). The approach achieves significant increase of radiated power for an on-chip array of antennas. For example, impressive results are obtained for arrays working in a frequency window around the THz gap, i.e. within and around the range of 300 GHz-3 THz.

(15) For the detailed description, we will remind on the following terminology: W-band frequency: 67 GHz to 110 GHz J-band frequency: 220-325 GHz D-band frequency110 GHz to 170 GHz THz Gap frequencyapproximately between 0.3 THz and 3 THz. EIRPEquivalent Isotopically Radiated Power TRPTotal Radiated Power directivity of arraydirectivity of combined beam of an array, measured at far-field DC consumption: DC power, measured as DC voltage to transistors' drains multiplied by DC current through transistors' drains. Locking rangethe frequency range, in which a VCO is jitter-free, meaning it is directly influenced by injection signal. In this range, the VCO's frequency can be adjusted (i.e. the frequency of the VCO will track, or equal to that of the injecting signal) Q of the tankquality factor of the resonant tank of the oscillator (VCO) ESD protectionElectrostatic Discharge protection against ESD shock; An antenna element comprises at least an antenna (for example, a receiving antenna). Transmitter/transceiver being provided with a suitable antenna forms a radiating antenna element. Source for radiation frequency (radiating source) may comprise one or more antenna elements comprising transmitter(s). Two or more antenna elements, placed on an insulating board (for example, on a silicon substrate), form an array. Antenna element, especially as part of an array, may be called pixel, transmitter or antenna VCOVoltage Controlled Oscillator Antenna chipan insulating board carrying one or more antennas Trenchchannel/dice/slot provided in an insulating board/silicone substrate

(16) FIGS. 1a-c illustrate a combined concept demonstrated by a Low cost 2D scalable wirelessly locked THz antennas' array.

(17) FIG. 1a shows an exemplary implementation of an insulating board/silicon substrate/die 10 intended for a low cost 2D scalable antennas' array. On the board 10, individual areas 14 for the antennas (antenna elements, transmitters, sources, pixels) 16 (shown in FIGS. 1b, 1c) are separated by channels/trenches 12 provided at the back surface of the substrate 10. In practice, the backside of the insulating board can be diced (as shown), after manufacturing of the array on the front surface of the board (so-called post manufacturing process). Alternatively, the channels 12 can be made on the front-side of the substrate, and in advance. As has been shown by the Inventors, any channels within the antenna substrate (CMOS or else) will serve the purpose of conserving antenna gain. Channels can be either diced after antenna printing, or trenched prior to the antenna printing on CMOS or board by a process called Through-Silicon-Via (for CMOS/silicon substrates) or Through-Metal-Via (for boards/packages like BT, FR4 etc).

(18) FIG. 1b is a schematic illustration and a model of one proposed topology of a single radiating source (antenna element, pixel) 16. In this example, it is based on a THz transmitter VCO 16a coupled with a THz antenna 16b, both manufactured by CMOS The antenna is for example a loop antenna which already proved its excellent properties according to the previous work [14] of the Inventors. VCO in FIG. 1b is of the Colpitts configuration. The Inventors proposed to connect the transmitter directly to the antenna, to separate VCOs in the array and to perform wireless injection locking (see FIG. 1c, and also FIGS. 6b, 6c). In the antennas' model (dotted contour marked 17), the upper branch comprising a virtual resistance Rant corresponds to frequency 300-345 GHz (3.sup.rd Harmonic), while the branch with two virtual inductivities Ld corresponds to the 100-115 GHz (Fundamental harmonic), both harmonics being generated by the VCO. The transistors isolate the tank of their L.sub.g and C.sub.gs from the antenna that loads the drains. Tuning is achieved by gate biasing that controls C.sub.gs without adding a low Q varactor. The relatively high Q of the effective tank and the absence of a tail current enables fundamental voltage amplitudes exceeding 2V.sub.dd. These exemplary amplitudes enable very efficient 3.sup.rd harmonic current generation in the transistors, driving the loop antenna connected directly to the drains. Other amplitudes may bring efficient generation of another (for example, of 5.sup.th) harmonic. The special design of the loop antenna comes again into play: it is an RF inductive choke at the fundamental frequency but resistive, for example, at the radiated 3.sup.rd harmonic. Therefore, there is hardly any power generated at the fundamental frequency, let alone radiated, and very efficient generation and radiation at the 3.sup.rd harmonic. It has been found by the Inventors, that it is a) possible and b) advantageous to use a sub-harmonic external radiating source, in order to wirelessly lock the radiated output frequency of a THz transmitter. The locking phenomenon in VCO takes place due to a sufficiently large open-circuit voltage at the antenna node (in receiving mode) connected to the transistors Drains of first transmitter (i.e., directly). In operation, the parasitic capacitances of capacitors connected between gate and drain (Cgd) and drain and source (Cds) provide current path to a so-called resonant/oscillation tank between the Gate and the Source at the fundamental frequency of the VCO. Computer simulations take into account specific parameters and for example, show that the open-circuit voltage of the antenna, radiated with incident power of 20 dBm is around 3 mV rms around 110 GHz. This corresponds to a locking range of 0.3 GHz at the fundamental frequency, as observed in simulation, as well as predicted by Adler's equation of the locking range .sub.L, taking into account the simulated oscillation and injected amplitudes in the tank:

(19) ${}_L=\frac{{}_0}{2Q}\frac{V_{\mathrm{inj}}}{V_{\mathrm{osc}}}$
where V.sub.inj is the injected voltage (at 110 GHz), V.sub.osc is the oscillation voltage, Q is taken as 25, .sub.0 is the oscillation frequency taken at 110 GHz and the resulting locking range is 0.2 GHz.

(20) FIG. 1b, inter alia, schematically shows one proposed way of locking of a single on-chip J-band radiating source 16. The source is based on a fundamental W-band VCO that radiates its J-band 3-rd harmonic 3f.sub.osc (21) using an on-chip loop antenna, connected directly to the differential VCO without a buffer. Radiating the chip with a W-band signal 22 f.sub.lock=f.sub.osc (for example, using a horn antenna located 50 cm away), enables wireless injection locking of the radiating source 16. The source can be tuned in a wide frequency range between of about 280 and of about 294 GHz with peak total radiated power of about 0.6 mW, EIRP of about +7 dBm and DC to THz radiated power efficiency of about 3%.

(21) With a free-running phase noise of better than 95 dBc/Hz at 10 MHz offset, the locked signal follows the phase noise of the external reference up to a locking range around 80 MHz with 25 dBm of radiated W-band power. In a slightly different example of the radiating source (transmitter) of FIG. 1b, the circuit may be designed in a TSMC (Taiwan Semiconductor Manufacturing Co) CMOS 65 nm process, on a 230 m thickness bulk (without channels) bearing resistivity of 10 .Math.cm. The VCO 16a is based on a differential Colpitts voltage controlled oscillator (VCO).

(22) The VCO tank is composed of a nested loop LS and a MOM capacitor CS at the source of the transistors, the frequency tuning is achieved by controlling the transistor Gate bias (modifying the transistor Gate-Source capacitance and therefore the oscillation frequency). The loop (ring) antenna 16b is connected directly to the transistor drain and is designed so that its ring is an inductor and plays the role of an RF-choke at the VCO fundamental oscillation frequency (say 100-115 GHz) and at the 3rd harmonic (300-345 GHz) of the oscillation frequency the loop/ring becomes an almost purely resistive element, acting therefore as a J-band, matched resistive loop antenna. Decoupling capacitors and ESD protection formed by N-type diodes were added at each bias node in the circuit. A 1 K resistor was added in series to the transistor gate as an additional ESD protection.

(23) The maximum simulated injected power into the antenna is about 0 dBm and the VCO simulated tuning range is about 5%. The antenna, simulated by a computer simulation program, has a 10 dB bandwidth of 21% (260-320 GHz) and directivity and total efficiency above +8 dBi and 50% respectively, from 270 GHz to 320 GHz.

(24) VCO operation. As mentioned, the VCO tank is composed of a nested loop LS and a MOM capacitor CS at the Source of the transistors. However, the main capacitor and inductor which determine the oscillation frequency of the VCO are the CGS Gate-Source capacitor and the Gate nested loop inductor LG. Therefore, the frequency tuning is achieved by controlling the transistor Gate bias (modifying the transistor Gate-Source capacitance and therefore the oscillation frequency). The inductor Ls merely needs to be large enough to ensure the oscillation stability, while a proper ratio between the transistor dimensions, Gate inductor LG and Source capacitor CS will maximize the tuning range. The passive elements (inductors and source capacitor) are fixed in value and are determined in the design. Same goes to the dimensions of the transistor. However, the DC value of Vg, changes effectively the transistor's gate-source capacitance, which, in turn, changes the free-running oscillation frequency.

(25) The VCO was designed in simulation to have its fundamental oscillation frequency centered at 110 GHz. The simulated maximum differential output power at the transistors drains is 0 dBm at 330 GHz and the simulated tuning range is 1%. Decoupling capacitors and ESD protection (formed by N-type diodes) were added at each bias input of the circuit. A 1 K resistor was added in series to the transistor Gate as an additional ESD protection.

(26) The fact that the VCO is directly connected to the antenna is novel and fruitful, alongside with the multi-functionality of the antenna and, of course, with the use of an external locking source for injection locking.

(27) FIG. 1c schematically shows an exemplary antennas' array formed from elements 16 shown in FIG. 1b, placed on the substrate 10 shown in FIG. 1a. In other words, pixels of the array may be THz CMOS radiating sources. Further, FIG. 1c schematically illustrates that trenches 12 formed in the substrate to isolate elements of the array, can be metal filled. For example, it can be performed by placing the back side of the substrate 10 onto a layer of conductive glue 18 on a board (PCB) 20. FIG. 1c also shows that so-called wireless injection locking can be performed on the antenna's array (using for example a 100 GHz external reference, symbolically marked 22). It should be noted, however, that the antenna's array may be placed on an insulating board not having the above-mentioned channels.

(28) If such an array is subjected to a locking frequency using 22, the wireless injection locking will anyway take place, but will be less efficient due to interference of non-isolated antennas of the array. In any configuration of the insulating board, the injection-locking process may be two-fold: first, neighboring elements in the array injection lock each other (arrows 24); then, an external 100 GHz source 22 (not shown in FIG. 1c) locks the entire array to a reference. We use a value of 100 GHz in this example, though it may actually be 115 GHz or the like. Loop antennas may play an important role here as well. Even though the fundamental 100 GHz is not radiated by the antennas, it generates a magnetic field in the loop, which is inductive at 100 GHz. This signal is magnetically coupled into the neighboring loop antennas and injected into the VCO tank through the transistor r.sub.ds and C.sub.gd The external 100 GHz locking source has no impact on the 300 GHz (three-fold 100 GHz) radiated power and could easily be implemented in CMOS as well with an output power of just 15 dBm.

(29) It has been successfully demonstrated by the Inventors that the high gain property of antennas in arrays can be achieved for frequencies around 270-350 GHz. However, a similar effect can be realized over a much larger frequency spectrum (at least 200-700 GHz, according to first results of the current research). Below, there is presented a more detailed description of an antennas array intended for injection locking and created on a substrate with or without dividing it into individual areas by the above-described channels. Numerous VCOs may be combined and coupled into an array on the same chip, may run in parallel and employ mutual locking. The proposed new way of locking a radiating J-band source may be used in the array. To check it, a VCO with a free-space running radiating THz source was realized and its free-running signal was successfully observed and measured. The measured output signal of one THz source demonstrated a maximum EIRP of +3.8 dBm at 345 GHz, with a tuning range of 1.2% between 343 and 347 GHz. By using a reference signal from an external D-band source and radiating it in the direction of the free-running THz radiating chip array at a frequency close to its fundamental oscillation frequency, the 3rd harmonic radiating source array signal was successfully locked at THz frequencies.

(30) Arrays of 12 and 14 sources were realized and EIRP improvements of 5 and 10 dB, respectively, were measured, resulting in a +8.6 dBm/+13.8 dBm EIRP for the 12/14 arrays. The TRP (total radiated power) of the 14 array is +1 dBm, resulting in a DC-to-THz efficiency of 1.2%.

(31) The above-mentioned parameters of the proposed transmitter are much better (by around an order of magnitude), compared to other CMOS nodes (e.g. 45 nm etc.). Also, they beat other approaches for THz radiation production than VCO+Antenna, e.g. multiplying chains and VCO+PLL+Antenna. A circuit similar to that of FIG. 1c (but without channels 12) was designed in a TSMC CMOS 65 nm process, with a 230 m thick silicon bulk, bearing a resistivity of 12 .Math.cm. In the example, each element of the array is based on a differential Colpitts voltage controlled oscillator (VCO).

(32) The on-chip ring antenna of each VCO of FIG. 1c can be similar to the antenna in FIG. 1b. It should be noted that the mutual injection locking is not mandatory for the proposed solution (though helpful). The closeness of the elements gives three things: i) the beam of the external locker can be narrow, and still encompass all elements. ii) beam steering can be done more easily, since close elements interact easily at free-space. iii) the directivity of the entire radiated beam is increased as the elements are closer.

(33) Still, dividing the silicon area of the array into individual areas 14 of the array pixels brings additional advantages, like stabilizing Gain of one transmitter/pixel of an array, and stabilizing & increasing Gain of the array with reference to the Gain achieved without the separated individual areas To summarize, FIGS. 1a-1c schematically present and illustrate two inter-related concepts of the present invention: isolating antenna elements in an array and wirelessly locking thereof for more effective operation. It is shown by an exemplary implementation comprising wirelessly-locked 0.3 THz 23 radiating source array in 65 nm CMOS. As mentioned, the wireless injection locking of the array can be achieved at a usual insulating board/die (without the mentioned channels). However, by using post-processing metallized (metal plated) diced trenches at the die backside, a TRP of +5.4 dBm and EIRP of +22 dBm with 5.1% radiated DC-to-THz efficiency was achieved. The achieved radiated power and efficiency in this locked source should be seen as a record (an achievement) for integrated circuits of any technology above 200 GHz.

(34) FIG. 2a schematically shows an exemplary optimal individual area 14 formed on an insulating board 10 by trenches 12 (for example, metallized trenches), for an antenna element 16 (in this example, a radiating source). The exemplary optimal area is found in the range which allows preserving the antenna's Gain, for example in the presence of neighboring antenna elements.

(35) FIG. 2b shows electromagnetic simulation results of the silicon area variation and metal plated trenches impact on the antenna gain. Speaking about frequencies and parameters of the silicon substrate, the Inventors have realized that an optimal area for an antenna in an array can be found empirically, by detecting that the gain of the antenna in the array is stabilized and does not decrease due to the increased area/neighbor antennas. For example, the optimal area was achieved by the proposed technique in the following case: for frequencies from 250-350 GHz and for a silicon substrate with the following characteristics: relative permittivity equal to 11.9, resistivity of 12 ohms.Math.cm. Dimensions of the optimal area depend on the antenna type. In the case of a loop antenna, that area is around 300300 microns.

(36) Through their research, the Inventors have shown that it is possible to design a high gain loop antenna (5-8 dBi gain) in a standard silicon technology (CMOS, Dielectric constant=12, resistivity=12 ohms.Math.cm) when realized within an optimal silicon area. Depth of the channels/metal walls embedded in the silicon substrate may vary up to the depth maximally allowed by thickness of the substrate.

(37) Results of computer simulation of FIG. 2b show that Gain of an antenna can be stabilized over any silicon area if the array is provided with metal plated trenches defining an individual (preferably, optimal) area for that specific antenna. As can be seen in FIG. 2b, the simulated gain of the on-chip antenna degrades dramatically with increase of silicon area without trenches, but remains constant with the trenches setting the pixel silicon area optimally. The stabilized Gain is shown as a horizontal upper line in FIG. 2b.

(38) FIGS. 3a-c show an EM (electromagnetic) model of the antennas array (NM), with corresponding S-parameters and realized Gain parameters achieved by using the proposed trench/dicing technology. According to the concept, a group of elements respectively comprising THz antennas, were arranged into a design of an NM array (for example, a 23 array, but actually any array comprising two or more elements) on a silicon surface limited by available fabrication silicon area of a semiconductor wafer or PCB, while trenches (preferably, metal filled trenches) provided on the backside of the PCB plate so as to define an individual silicon area for each of the elements and separate the individual silicon areas from one another. The metal filled trenches enabled minimal interference between elements of the array and their optimum placement as a tradeoff between performance and silicon area cost.

(39) For example, in 65 CMOS the Inventors' approach allows obtaining a record radiated power of +5.4 dBm at 0.3 THz using only a 23 on-chip array, EIRP of +22 dBm and 5.1% of radiated power to DC power, which is more than five times achieved for an array in any technology at these frequencies.

(40) Therefore, the concepts proposed in this work will be further explained and illustrated using an example of a 300 GHz Wirelessly-Locked 23 Array Radiating +5.4 dBm with 5.1% DC-to-RF Efficiency in 65 nm CMOS (which has also been mentioned with reference to FIG. 1c).

(41) The EM design of the exemplary antenna array (FIG. 3a) included the Voltage Controlled Oscillator (VCO) inductors 16, ground rings, PCB ground plane 20 and bond wires 26. The technological stages of packaging a 23 array on a die 10 may be as follows: 1) filling the trenches 12 with metal walls by impregnating the die/substrate of the chip 10 with a conductive glue, from backside of the die, when the chip is glued (for example with a silver epoxy conductive glue, not shown) on the PCB 20, 2) metallizing sides of the substrate, for example by the same conductive glue, and 3) bonding the chip with metal wires 26 to the PCB 13 (for example, at each pixel of the array). Using as a load the antenna S-parameters extracted from an EM simulator, the VCO was designed to oscillate around 285 GHz at the 3.sup.rd harmonic. From simulation, the differential Colpitts oscillator is able to deliver up to 2.5 dBm at the drain (antenna) at 285 GHz. Based on simulation, an EIRP of +21-22 dBm was calculated. To lock the oscillators, the wireless injection technique presented in [14] was used.

(42) FIG. 3b shows the return loss parameter (in dB) of the array of FIG. 3a (comprising six antennas on the substrate with metal plated trenches), depending on frequency (GHz). S-parameters indicate how well power is delivered to the antenna from a given source (VCO in our case). The antenna is matched when S-parameters are high. As the return loss (which is identical to S11) is lower, it is bettermore power is delivered to the antenna). S11 BW means what is the bandwidth (BW) in which the antenna is matched (i.e. power is delivered properly to the antenna). FIG. 3b shows that the exemplary antenna is matched between of about 250 and 325 GHz; S11 BW: 80 GHz (28%).

(43) Simulation of FIG. 3c shows a realized gain of 11.2 dBi (40% efficiency) with a S11 bandwidth of 80 GHz (28%) around 285 GHz. (See the curve made by triangles, for the above-discussed 23 array). Compared to a single element (the curve made by rectangles), the discussed 23 array has a 7 dB increase being slightly lower than the theoretical maximum gain (7.8 dB). The curve made by circles shows the realized gain in the same array where trenches between pixels are not provided. As mentioned, the use of metal filled trenches enabled minimal interference between elements and their optimum placement as a tradeoff between performance and silicon area cost. Owing to separation of antenna elements, a very good quality of signals can be obtained, On such a basis, the signals may further be successfully pulled, synchronized and wirelessly locked.

(44) FIGS. 4a, 4b show power scans of a single radiating source (FIG. 4a) and a 23 array of the sources (FIG. 4b). Scans of a single and of six pixels (i.e. elements or antennas) were made and TRP of 2.4 dBm and +5.4 dBm were measured, respectively. Very good fit with maximum theoretical array gain are observed for the TRP and EIRP. From the measured EIRP and TRP, the 23 pixels array has a directivity of 16.6 dBi. The 23 pixels array consumes in total 67.2 mW DC power consumption resulting in a record 5.1% radiated power DC-to-THz efficiency. The 2D 23 array occupies a square of about 2.22 mm.sup.2.

(45) FIG. 4c shows the graphs of EIRP and Tuning Range as a function of the frequency and control Gate bias voltage (V) for a single antenna and for the 23 pixels array. The graphs are measurement results. It can be seen that parameters of the antennas array with trenches are significantly better than those of a single antenna element or an array without trenches. The EIRP graph of the array with trenches shows of about double efficiency of the array in comparison with that without trenches.

(46) FIG. 4d shows the graph of EIRP/TRP as a function of the sources number. FIG. 4d shows that the theoretical and the measured values of TRP and EIRP actually coincide for the proposed array.

(47) FIG. 5a schematically illustrates a specific example of the 23 pixels array, which was realized using the TSMC 65 nm CMOS process with 230 m silicon thickness.

(48) FIG. 5b presents a side view of the substrate and an enlarged cross-section of one trench. By using a blade dicer, trenches were provided on the backside of the die/wafer such as PCB. A 50 m width blade was used and a depth dice of about 150 m was realized which fulfills the isolation condition for efficient THz radiation without scarifying mechanical stability. To fill the trenches, the circuit was simply glued on a PCB with a conductive glue filling completely all the trenches, and then wire-bonded.

(49) FIG. 6a schematically shows that in the prior art, a THz transmitter (radiating source, VCO) 30 is usually connected to an antenna 32 via a buffer circuit 31 which is rather complex and expensive; also, the antenna 32 works in the transmitting regime only, to radiate a desired transmitting frequency.

(50) FIG. 6b schematically illustrates the inventive concept of frequency locking, using two exemplary values of frequencies. A locked THz transmitter (radiating source) 36 can be obtained using a rather cheap CMOS-based VCO 36a which basically generates a radiating/transmitting and a subharmonic frequencies with jitter (in this example, 0.3 THz and 0.1 Thz respectively). To lock it, an external source 34 of locked subharmonic frequency is provided. The VCO 36a is directly connected to its antenna 36b, and then so-called wireless injection locking of a subharmonic frequency of the VCO may be performed, using an external source 18 which is locked at that subharmonic frequency. The antenna 36b is adapted to receive that locked frequency from the external source 34. When the internal subharmonic frequency 0.1 THz of the VCO 14, circulating between the transmitter 36a and the antenna 36b, becomes locked owing to the effect of wireless injection from the external source 34, it also results in locking of the radiating frequency of the VCO, produced from the subharmonic frequency, and the radiating frequency 0.3 THz is transmitted from the antenna 36b. It should be noted that the antenna 36a may be adapted to transmit also the subharmonic frequency. An antenna element comprising a transmitter 36a and an antenna 36b is marked 36. A system comprising at least one element 36 and an external source 34 is marked 38.

(51) FIG. 6c shows one implementation of the inventive concept, where a number of elements 36 each comprising a VCO with antenna like that in FIG. 6b are arranged in an array 39 sufficiently close to one another, and when each of the elements is also capable of radiating the subharmonic frequency. The mutual locking (shown by arrows 37 between elements 36) enhances the locking effect of the external source (injector) 34 which may have a wide beam that will radiate at the whole array. FIG. 6c may be understood also as a system 38 illustrating the combined external and mutual wireless injection locking in the array 39.

(52) FIG. 7 shows the measurement results of the EIRP and of tuning range of a single antenna element against the control Gate bias voltage, wherein the antenna element is an antenna+the proposed THz transmitter, when injection locking is applied. To measure the circuit total radiated power, a maximum mechanically allowed scan of 1516 mm2 at a distance of 4 mm was realized. The scan showed that the sum of all the radiated power collected in the scan area results in a directivity of 8.1 dBi and a total radiated power (TRP) of 4.3 dBm for a single element of the array. These results demonstrate advantages of the wireless injection locking in our VCO array.

(53) Table 1 (below) is a combined generalized table where the main design factors of the proposed THz transmitter array are qualitatively compared with the corresponding main design factors of some known types of THz arrays. All the architectures are compared based on the same EIRP, i.e. normalized to the same EIRP value.

(54) TABLE-US-00001 TABLE 1 Frequency Synthesis Architecture Connection DC Locked (of an array) to Antenna Consumption Signal Complexity Area Cost Active MN Very High High Large High Multiplying Chain VCO + PLL MN Medium High Medium High VCO MN Low Low Small Low VCO (this None Low Low Small Low work) MN - Matching Network, typically a transformer; Area - area for fabrication

(55) Table 2 (below) presents a comparison of the proposed solution for a THz source array with various known solutions described in references [4] and [10] to [14] from the list presented at the end of the description. By using post-processing metallized (metal plated) diced trenches at the die backside, a TRP of +5.4 dBm and EIRP of +22 dBm with 5.1% radiated DC-to-THz efficiency was achieved. The achieved radiated power and efficiency in this locked source is a record for integrated circuits of any technology above 200 GHz.

(56) TABLE-US-00002 TABLE 2 JSSC 2012 ISSCC 2014 ISSCC 2015 ISSCC 2013 IMS 2015 RFIC This Reference [4] [10] [11] [12] [13] 2015 Work Freq. (GHz) 280 338 317 260 400 345 296 Tuning Range (%) 3.2 2.1 1.4 7.7 1.1 2.4 (a) EIRP (dBm) 9.4 17.1 22.5.sup.(b) 15.7.sup.(b) 5(c) 13.8 22 TRP (dBm) 7.2 0.9 5.2(b) 0.5(b) 1 5.4 DC consuption 820 1540 610.sup.(d) 800 1400.sup.(d) 105.sup.(d) 67.2.sup.(d) (mW) DC-to-RF 0.023 0.053 0.54.sup.(b) 0.14.sup.(b) 1.2 5.15 Eff. Beam 80/80 45/50 70/0 26/21 Steering ( per direction) Array Type 44 44 44 24 18 14 23 Architecture Coupled Coupled PLL Coupled X4 mult. IL VCOs IL VCOs VCOs VCOs VCOs Locked signal No No Yes No Yes Yes Yes Nominal Voltage 1.1 V 1.4 V 2.3 V 1.2 V 1.4 V 1.2 V 1.4 V (V) Technology 45 nm 65 nm 130 nm 65 nm 45 nm 65 nm 65 nm CMOS CMOS SiGe CMOS CMOS CMOS CMOS Silicon area (mm.sup.2) 7.29 3.9 2.08 2.25 10.5 0.71 2.22 .sup.(a)3 dB bandwidth for multiplying chains. .sup.(b)Use of a silicon lens. .sup.(c)Use of a superstrate quartz. .sup.(d)Does not take into account the DC power consumption of the external locked reference.

(57) The developed concept allows the realization of a scalable THz source array at low cost. Also, it has been demonstrated that the high gain property of antennas in arrays can be achieved for frequencies around 270-350 GHz. However, it can be realized over a much larger frequency spectrum (at least 200-700 GHz, according to the present research).

(58) Advantages of the solution proposed by the Inventors will be discussed below, referring to specific examples, when applicable.

(59) The Inventors suggested using a VCO manufactured by CMOS technology, which, being widely spread and relatively cheap, provides advantages (see below). The inventors suggested directly connecting the VCO with a suitable antenna, (which can also be made by CMOS), thus creating an improved antenna element. The Inventors suggested providing an antenna element (being a single one or an element of an array, for example being the proposed improved one) with its individual area on a silicon substrate/insulating board, by defining such an area by channels made in the substrate (and preferably, by further metallizing the channels). Though CMOS VCO was previously considered unsuitable for locking THz band frequencies, the Inventors have shown that the proposed method surprisingly allows efficiently locking THz band frequencies of such CMOS-based VCOs. For example, the use of a subharmonic frequency of a CMOS-based transmitter/VCO allows working in the range of frequencies lower than f.sub.max of VCO, so the problem of low transmitted Gain does not exist in the inventive solution.

(60) Further, the use of quite a low power, subharmonic frequency locking signal from a remote source working in free space allows obtaining a robust transceiver with a locked THz gap transmitting frequency. Such a transceiver does not require expensive and bulky PLL circuits and/or multiplying schemes, and has very low DC power consumption. More specifically, the proposed approach for injection locking of radiating THz CMOS VCOs alleviates the need for an integrated PLL and allows injection locking without lowering the tank Q, thus preserving the source high output power. For example, wide tuning of 280-294 GHz is demonstrated with up to +7 dBm of EIRP and 0.6 mW of total radiated power from a single element with 3% of radiated power efficiency. The new approach can further be applied to simultaneous wireless injection locking of radiating THz CMOS arrays, saving the required silicon area and DC power consumption and removing the need of complex high frequency distribution networks.

(61) The proposed trenches/channels allow facile design of both the antenna and the rest of the circuit, since they are decoupled by the trenches. In literature, it is usually reported over arrays in these frequencies. Still, relevant results are around +3 dBm EIRP and 0.05 mW total radiated power. Also, a most relevant figure is the efficiency (DC-to-RF energy conversion, measured in %)there people report around 0.14 and 0.015%, whereas the proposed invention has around 1.2% (or higher). Trenches increase the antenna performance and, consequently, the overall performance of the chip.

(62) The novel approach, upon being applied to an array of the described radiating sources, has demonstrated that a combination of mutual (inter-chip) and external reference locking effects is an extremely powerful technique for synthesizing a locked source, with high EIRP, TRP, low DC consumption, and minor circuit complexity. By combining the possibility to lock both frequency and phase, both directivity and TRP of the array are increased, compared to a single element. For example, a maximum EIRP/TRP of +13.8/+1 dBm at 345 GHz from a 14 VCO array is demonstrated, with a locked output signal, and the effect could be scaled up to large 2D arrays.

(63) The important advantage of the present invention is that the proportion between the required expenses and the obtained power and accuracy of the output THz signal is much more favorable than in other existing solutions for the THz gap, mentioned in the background.

(64) The costs involved in designing & manufacturing such systems having desired parameters differ approximately by 500 times between the known existing methods and the proposed technique (for example, 500, 000 USD for existing methods and 5,000 USD for the proposed method.)

(65) It should be understood that other versions and implementations of the proposed method, system and antenna/antennas' array may be proposed, and they are to be considered part of the invention, whenever defined by the claims which follow (after the list of references).

REFERENCES

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