MULTIPLE-LEVEL INTERCONNECT STRUCTURE AND MANUFACTURING METHOD THEREOF

Abstract

Provided are a multiple-level interconnect structure having a scatterometry test layer and a manufacturing method thereof. The multiple level interconnect structure includes a patterned reflective layer, a bulk reflective layer and a patterned test layer. The patterned reflective layer is disposed on a substrate and includes a first reflective pattern and a second reflective pattern separated from each other. The bulk reflective layer is disposed on the patterned reflective layer. The patterned test layer is disposed on the bulk reflective layer.

Claims

1. A multi-level interconnect structure, having a scatterometry test layer, comprising: a patterned reflective layer, disposed on a substrate and comprising a first reflective pattern and a second reflective pattern separated from each other; a bulk reflective layer, disposed on the patterned reflective layer; and a patterned test layer, disposed on the bulk reflective layer.

2. The multi-level interconnect structure of claim 1, wherein the first reflective pattern comprises a plurality of strip patterns arranged in parallel, the second reflective pattern comprises a plurality of conductive via patterns, and the conductive via patterns are located between two adjacent strip patterns.

3. The multi-level interconnect structure of claim 2, wherein a plurality of columns of the conductive via patterns are disposed between two adjacent strip patterns.

4. The multi-level interconnect structure of claim 1, wherein the first reflective pattern comprises a bulk pattern having a plurality of openings, the second reflective pattern comprises a plurality of conductive via patterns, and the plurality of conductive via patterns are located in the plurality of openings.

5. The multi-level interconnect structure of claim 1, wherein the first reflective pattern comprises a plurality of first conductive via patterns, the second reflective pattern comprises a plurality of second conductive via patterns, and the aperture of the plurality of first conductive via patterns and the aperture of the plurality of second conductive via patterns are different from each other.

6. The multi-level interconnect structure of claim 1, wherein the patterned reflective layer further comprises a third reflective pattern, the first reflective pattern comprises a plurality of first conductive via patterns, the second reflective pattern comprises a plurality of second conductive via patterns, the third reflective pattern comprises a plurality of third conductive via patterns, and the aperture of the plurality of first conductive via patterns, the aperture of the plurality of second conductive via patterns and the aperture of the plurality of third conductive vias are different from each other.

7. The multi-level interconnect structure of claim 1, wherein a ratio of the projected area of the patterned reflective layer on the substrate to the projected area of the bulk reflective layer on the substrate is between 0.75 and 0.90.

8. The multi-level interconnect structure of claim 1, wherein a material of the patterned reflective layer comprises metal.

9. The multi-level interconnect structure of claim 1, wherein a material of the bulk reflective layer comprises metal.

10. The multi-level interconnect structure of claim 1, wherein the bulk reflective layer is located directly under the patterned test layer, and the patterned reflective layer is located directly under the bulk reflective layer.

11. The multi-level interconnect structure of claim 1, further comprising a dielectric layer disposed between the bulk reflective layer and the patterned test layer.

12. The multi-level interconnect structure of claim 1, further comprising a dielectric layer disposed between the first reflective pattern and the second reflective pattern.

13. A manufacturing method of a multi-level interconnect structure having a scatterometry test layer, comprising: forming a patterned reflective layer on a substrate, wherein the patterned reflective layer comprises a first reflective pattern and a second reflective pattern separated from each other; forming a bulk reflective layer on the patterned reflective layer; and forming a patterned test layer on the bulk reflective layer.

14. The manufacturing method of a multi-level interconnect structure of claim 13, wherein the first reflective pattern comprises a plurality of strip patterns arranged in parallel, the second reflective pattern comprises a plurality of conductive via patterns, and the conductive via patterns are located between two adjacent strip patterns.

15. The manufacturing method of a multi-level interconnect structure of claim 14, wherein a plurality of columns of the conductive via patterns are disposed between two adjacent strip patterns.

16. The manufacturing method of a multi-level interconnect structure of claim 13, wherein the first reflective pattern comprises a bulk pattern having a plurality of openings, the second reflective pattern comprises a plurality of conductive via patterns, and the plurality of conductive via patterns are located in the plurality of openings.

17. The manufacturing method of a multi-level interconnect structure of claim 13, wherein the first reflective pattern comprises a plurality of first conductive via patterns, the second reflective pattern comprises a plurality of second conductive via patterns, and the aperture of the plurality of first conductive via patterns and the aperture of the plurality of second conductive via patterns are different from each other.

18. The manufacturing method of a multi-level interconnect structure of claim 13, wherein the patterned reflective layer further comprises a third reflective pattern, the first reflective pattern comprises a plurality of first conductive via patterns, the second reflective pattern comprises a plurality of second conductive via patterns, the third reflective pattern comprises a plurality of third conductive via patterns, and the aperture of the plurality of first conductive via patterns, the aperture of the plurality of second conductive via patterns and the aperture of the plurality of third conductive vias are different from each other.

19. The manufacturing method of a multi-level interconnect structure of claim 13, a ratio of the projected area of the patterned reflective layer on the substrate to the projected area of the bulk reflective layer on the substrate is between 0.75 and 0.90.

20. The manufacturing method of a multi-level interconnect structure of claim 13, wherein the bulk reflective layer is located directly under the patterned test layer, and the patterned reflective layer is located directly under the bulk reflective layer.

21. The manufacturing method of a multi-level interconnect structure of claim 13, further comprising forming a dielectric layer on the bulk reflective layer after forming the bulk reflective layer and before forming the patterned test layer.

22. The manufacturing method of a multi-level interconnect structure of claim 13, further comprising forming a dielectric layer between the first reflective pattern and the second reflective pattern.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The accompanying drawings are included to provide a further understanding of the disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the disclosure and, together with the description, serve to explain the principles of the disclosure.

[0032] FIGS. 1A to 1C are schematic cross-sectional views of a manufacturing process of a multi-level interconnect structure drawn in accordance with a first embodiment of the present invention.

[0033] FIG. 2A is a schematic top view of a patterned reflective layer of a multi-level interconnect structure according to the first embodiment of the present invention.

[0034] FIG. 2B is a schematic top view of a bulk reflective layer of a multi-level interconnect structure according to the first embodiment of the present invention.

[0035] FIG. 2C is a schematic top view of a patterned test layer of a multi-level interconnect structure according to the first embodiment of the present invention.

[0036] FIG. 3 is a schematic top view of a patterned reflective layer of a multi-level interconnect structure according to a second embodiment of present invention.

[0037] FIG. 4 is a schematic top view of a patterned reflective layer of a multi-level interconnect structure according to a third embodiment of the present invention.

[0038] FIG. 5 is a schematic top view of the patterned reflective layer of the multi-level interconnect structure according to a fourth embodiment of the present invention.

[0039] FIG. 6 is a schematic top view of a patterned reflective layer of a multi-level interconnect structure according to a fifth embodiment of the present invention.

DESCRIPTION OF THE EMBODIMENTS

[0040] The embodiments are described in detail below with reference to the accompanying drawings, but the embodiments are not intended to limit the scope of the present invention. In addition, the drawings are for illustrative purposes only and are not drawn to the original dimensions. For the sake of easy understanding, the same elements in the following description will be denoted by the same reference numerals.

[0041] In the text, the terms mentioned in the text, such as “comprising”, “including”, “containing” and “having” are all open-ended terms, i.e., meaning “including but not limited to”.

[0042] In addition, the directional terms, such as “on”, “above”, “under” and “below” mentioned in the text are only used to refer to the direction of the drawings, and are not used to limit the present invention.

[0043] When using terms such as “first” and “second” to describe elements, it is only used to distinguish the elements from each other, and does not limit the order or importance of the devices. Therefore, in some cases, the first element may also be called the second element, the second element may also be called the first element, and this is not beyond the scope of the present invention.

[0044] In the text, a range represented by “a value to another value” is a summary expression way to avoid listing all the values in the range one by one in the specification. Therefore, the record of a specific numerical range covers any numerical value within the numerical range, as well as a smaller numerical range defined by any numerical value within the numerical range.

[0045] FIGS. 1A to 1C are schematic cross-sectional views of a manufacturing process of a multi-level interconnect structure drawn in accordance with a first embodiment of the present invention.

[0046] In the present embodiment, the device to be tested for the optical critical dimension measurement and the reflective device for improving the measurement accuracy are disposed in the test region of the substrate. In addition, the manufacturing of the device to be tested and the reflective device may be integrated with the manufacturing of the circuit structure in the device region of the substrate, but the present invention is not limited thereto. Therefore, in the present embodiment, the device to be tested and the reflective device in the test region and the circuit structure in the device region may be collectively referred to as a multi-level interconnect structure. The following will describe the formation of the device to be tested and the reflection device in the test region, and those skilled in the art should be able to clearly understand the formation of the circuit structure in the device region at the same time.

[0047] Referring to FIG. 1A, a substrate 100 is provided. In the present embodiment, the substrate 100 includes a silicon substrate, various semiconductor devices and circuit structures formed on the silicon substrate, and a dielectric layer covering the silicon substrate. In order to make the drawings clear and easy to explain, the above-mentioned various semiconductor devices, circuit structures and dielectric layers are not shown. Then, a dielectric layer 101 is formed on the substrate 100. In the device region, the dielectric layer 101 may be called an inter-layer dielectric layer. Next, a patterned reflective layer 102 is formed on the substrate 100. The material of the patterned reflective layer 102 is, for example, metal. The method of forming the patterned reflective layer 102 includes the following steps, for example. Openings are formed in the dielectric layer 101. Then, the openings are filled with a metal material layer. In the present embodiment, the steps of forming the patterned reflective layer 102 may be integrated with the steps of forming the conductive vias in the device region, but the present invention is not limited thereto.

[0048] In the present embodiment, the patterned reflective layer 102 includes a first reflective pattern 102a and a second reflective pattern 102b separated from each other by the dielectric layer 101. FIG. 2A is a schematic top view of the patterned reflective layer of the multi-level interconnect structure according to the present embodiment. As shown in FIG. 2A, in the present embodiment, the first reflective pattern 102a includes a plurality of parallel strip patterns 102a-1, and the second reflective pattern 102b includes a plurality of conductive via patterns 102b-1. The conductive via patterns 102b-1 are located between two adjacent strip patterns 102a-1. The conductive via patterns 102b-1 and the strip patterns 102a-1 are separated from each other by the dielectric layer 101. In the present embodiment, the conductive via patterns 102b-1 located between two adjacent strip patterns 102a-1 are arranged in one column, but the present invention is not limited thereto. In other embodiments, the conductive via patterns 102b-1 may be arranged in an irregular manner between two adjacent strip patterns 102a-1. In addition, in the present embodiment, these conductive via patterns 102b-1 have the same aperture, but the present invention is not limited thereto. In other embodiments, the conductive via patterns 102b-1 may have different apertures.

[0049] Referring to FIG. 1B, a bulk reflective layer 104 is formed on the dielectric layer 101. The material of the bulk reflective layer 104 is, for example, metal. FIG. 2B is a schematic top view of the bulk reflective layer of the multi-level interconnect structure according to the present embodiment. As shown in FIG. 2B, the bulk reflective layer 104 has a large-area bulk structure on the dielectric layer 101. The method of forming the bulk reflective layer 104 includes the following steps, for example. A metal material layer is formed on the dielectric layer 101. Then, a patterning process is performed on the metal material layer. The material of the bulk reflective layer 104 may be the same as or different from the material of the patterned reflective layer 102, which is not limited by the present invention. In the present embodiment, the steps of forming the bulk reflective layer 104 may be integrated with the steps of forming the circuit layer in the device region, but the present invention is not limited thereto. In the present embodiment, the bulk reflective layer 104 is in contact with the patterned reflective layer 102, but the present invention is not limited thereto. In other embodiments, depending on actual needs, the bulk reflective layer 104 and the patterned reflective layer 102 may be separated by a dielectric layer.

[0050] Referring to FIG. 1C, a dielectric layer 103 is formed on the bulk reflective layer 104. In the present embodiment, the dielectric layer 103 is the same as the dielectric layer 101. In the device region, the dielectric layer 103 and the dielectric layer 101 may be regarded as an integral inter-layer dielectric layer. Then, a patterned test layer 106 is formed on the bulk reflective layer 104 to serve as a scatterometry test layer. The material of the patterned test layer 106 is, for example, metal. FIG. 2C is a schematic top view of the patterned test layer of the multi-level interconnect structure according to the present embodiment. As shown in FIG. 2C, in the present embodiment, the patterned test layer 106 includes a plurality of parallel strip patterns, but the present invention is not limited thereto. In other embodiments, the patterned test layer 106 may have other patterns according to actual needs. The method of forming the patterned test layer 106 includes the following steps, for example. Trenches are formed in the dielectric layer 103. Then, the trenches are filled with a metal material layer. In the present embodiment, the steps of forming the patterned test layer 106 may be integrated with the steps of forming the circuit layer in the device region, but the present invention is not limited thereto. In this way, the multi-level interconnect structure 10 of the present embodiment is formed.

[0051] In the multi-level interconnect structure 10, the bulk reflective layer 104 is located directly under the patterned test layer 106, and the patterned reflective layer 102 is located directly under the bulk reflective layer 104. In this way, when the optical critical dimension is measured, light may be irradiated to the patterned test layer 106, and the measurement may be performed based on the reflected light. In addition, since the bulk reflective layer 104 and the patterned reflective layer 102 are disposed under the patterned test layer 106, when light enters under the patterned test layer 106, the light may be directly reflected and may not carry noise from the lower layer to ensure the measurement accuracy.

[0052] In addition, since the patterned reflective layer 102, which serves as a reflective structure together with the bulk reflective layer 104, is disposed under the bulk reflective layer 104, the problem of light leakage caused by insufficient thickness of the reflective structure may be effectively avoided.

[0053] On the other hand, in the present embodiment, the patterned reflective layer 102 includes reflective patterns of different sizes separated from each other, and the ratio of the projected area of the patterned reflective layer 102 on the substrate 100 to the projected area of the bulk reflective layer 104 on the substrate 100 is between 0.75 and 0.90, such that the bulk reflective layer 104 may be effectively prevented from being dished in the subsequent polishing process to ensure the reflective effect.

[0054] In the present embodiment, as shown in FIG. 2A, the first reflective pattern 102a includes a plurality of parallel strip patterns 102a-1, and the second reflective pattern 102b includes a plurality of conductive via patterns 102b-1, and the conductive via patterns 102b-1 located between two adjacent strip patterns 102a-1 are arranged in a column, but the present invention is not limited thereto. In other embodiments, the patterned reflective layer 102 may include other types of reflective patterns, which will be described below.

[0055] FIG. 3 is a schematic top view of a patterned reflective layer of a multi-level interconnect structure according to a second embodiment of the present invention. As shown in FIG. 3, the difference between the patterned reflective layer 102 of the present embodiment and the patterned reflective layer 102 of the first embodiment is that: in the present embodiment, two columns of conductive via patterns 102b-1 are disposed between two adjacent strip patterns 102a-1. In addition, as in the first embodiment, in the present embodiment, the ratio of the projected area of the patterned reflective layer 102 on the substrate 100 to the projected area of the bulk reflective layer 104 on the substrate 100 is between 0.75 and 0.90. According to actual needs, more columns of the conductive via patterns 102b-1 may be disposed between two adjacent strip patterns 102a-1.

[0056] FIG. 4 is a schematic top view of a patterned reflective layer of a multi-level interconnect structure according to a third embodiment of the present invention. As shown in FIG. 4, the difference between the patterned reflective layer 102 of the present embodiment and the patterned reflective layer 102 of the first embodiment is that: in the present embodiment, the first reflective pattern 102a includes a bulk pattern 102a-2 having a plurality of openings 105, the second reflective pattern 102b includes a plurality of conductive via patterns 102b-2, and one conductive via pattern 102b-2 is located in one opening 105. In addition, as in the first embodiment, in the present embodiment, the ratio of the projected area of the patterned reflective layer 102 on the substrate 100 to the projected area of the bulk reflective layer 104 on the substrate 100 is between 0.75 and 0.90. Depending on actual needs, in other embodiments, a plurality of conductive via patterns 102b-2 may be disposed in one opening 105, or the first reflective pattern 102a may include a plurality of bulk patterns 102a-2. In addition, the number and the arrangement of the openings 105 are not limited in the present invention.

[0057] FIG. 5 is a schematic top view of a patterned reflective layer of a multi-level interconnect structure according to a fourth embodiment of the present invention. As shown in FIG. 5, the difference between the patterned reflective layer 102 of the present embodiment and the patterned reflective layer 102 of the first embodiment is that: in the present embodiment, the first reflective pattern 102a includes a plurality of first conductive via patterns 102a-3, the second reflective pattern 102b includes a plurality of second conductive via patterns 102b-3, and the aperture of the first conductive via patterns 102a-3 and the aperture of the second conductive via patterns 102b-3 are different from each other. In addition, as in the first embodiment, in the present embodiment, the ratio of the projected area of the patterned reflective layer 102 on the substrate 100 to the projected area of the bulk reflective layer 104 on the substrate 100 is between 0.75 and 0.90.

[0058] In the present embodiment, the first conductive via patterns 102a-3 is arranged in an array, the second conductive via patterns 102a-3 are also arranged in an array, and the first conductive via patterns 102a-3 with a smaller aperture are located between adjacent second conductive via patterns 102a-3 with a larger aperture, but the present invention is not limited thereto. In other embodiments, according to actual needs, any arrangement may be used to arrange the first conductive via patterns 102a-3 and the second conductive via patterns 102a-3.

[0059] FIG. 6 is a schematic top view of a patterned reflective layer of a multi-level interconnect structure according to the fifth embodiment of the present invention. As shown in FIG. 6, the difference between the patterned reflective layer 102 of the present embodiment and the patterned reflective layer 102 of the fifth embodiment is that: in the present embodiment, in addition to the first conductive via patterns 102a-3 and the second conductive via patterns 102b-3, the patterned reflective layer 102 also includes a third reflective pattern 102c including a plurality of third conductive via patterns 102c-1. The aperture of the first conductive via patterns 102a-3, the aperture of the second conductive via patterns 102b-3 and the aperture of the third conductive via patterns 102c-1 are different from each other. In addition, as in the first embodiment, in the present embodiment, the ratio of the projected area of the patterned reflective layer 102 on the substrate 100 to the projected area of the bulk reflective layer 104 on the substrate 100 is between 0.75 and 0.90.

[0060] In the present embodiment, the first conductive via patterns 102a-3, the second conductive via patterns 102b-3 and the third conductive via patterns 102c-1 are each arranged in an array. The first conductive via patterns 102a-3 with a smaller aperture are located between adjacent second conductive via patterns 102b-3 with a larger aperture, and the third conductive via patterns 102c-1 with the smallest aperture surround the first conductive via patterns 102a-3 and the second conductive via patterns 102a-3, but the present invention is not limited thereto. In other embodiments, according to actual needs, any arrangement may be used to arrange the first conductive via patterns 102a-3, the second conductive via patterns 102b-3 and the third conductive via patterns 102c-1.

[0061] It will be apparent to those skilled in the art that various modifications and variations may be made to the disclosed embodiments without departing from the scope or spirit of the disclosure. In view of the foregoing, it is intended that the disclosure covers modifications and variations provided that they fall within the scope of the following claims and their equivalents.