LOW-TEMPERATURE IMPLANT FOR BURIED LAYER FORMATION

Abstract

Disclosed herein are methods for forming a buried layer using a low-temperature ion implant. In some embodiments a method may include providing an opening through a mask, wherein the mask is formed directly atop a substrate, and forming a buried layer in the substrate by performing a low-temperature ion implant through the opening of the mask. The method may further include forming an oxide layer over the substrate including over the buried layer.

Claims

1. A method, comprising: providing an opening through a mask, wherein the mask is formed directly on a substrate; forming a buried layer in the substrate by directing ions through the opening of the mask while maintaining the substrate at a temperature of less than or equal to 0 degrees Celsius, wherein the ions are directed into an exposed top surface of the substrate; and forming an oxide layer over the substrate including over the buried layer.

2. The method of claim 1, further comprising removing the mask prior to forming the oxide layer.

3. The method of claim 1, further comprising annealing the substrate and the oxide layer after the oxide layer is formed.

4. The method of claim 1, wherein the ions comprise antimony ions, phosphorous ions, Boron ions, Boron ions co-implanted with Carbon ions, Gallium ions co-implanted with Ge ions, or Indium ions.

5. The method of claim 1, wherein the buried layer is formed while maintaining the substrate at a temperature less than −30° Celsius.

6. The method of claim 1, further comprising forming the oxide layer directly atop the buried layer.

7. A method, comprising: providing a mask directly on a substrate, wherein the mask includes an opening recessed to a top surface of the substrate; forming a buried layer in the substrate by directing ions through the opening of the mask while maintaining the substrate at a temperature of less than or equal to 0 degrees Celsius, wherein the ions are directed into an exposed top surface of the substrate; and forming an oxide layer over the substrate including directly atop the buried layer.

8. The method of claim 7, further comprising removing the mask prior to forming the oxide layer.

9. The method of claim 7, further comprising annealing the substrate and the oxide layer after the oxide layer is formed.

10. The method of claim 7, wherein the ions comprise antimony ions, phosphorous ions, Boron ions, Boron ions co-implanted with Carbon ions, Gallium ions co-implanted with Ge ions, or Indium ions.

11. The method of claim 7, wherein the buried layer is formed while maintaining the substrate at a temperature less than −30° Celsius.

12. A method of forming a buried layer, comprising: patterning an opening through a mask, wherein the mask is provided directly on a substrate; forming a buried layer in the substrate by directing ions through the opening of the mask while maintaining the substrate at a temperature of less than or equal to 0 degrees Celsius, wherein the ions are directed into the top surface of the substrate to form the buried layer without the presence of an oxide layer along the top surface of the substrate; and forming an oxide layer over the substrate including directly atop the buried layer.

13. The method of claim 12, further comprising removing the mask prior to forming the oxide layer.

14. The method of claim 12, further comprising annealing the substrate and the oxide layer after the oxide layer is formed.

15. The method of claim 12, wherein the ions comprise antimony ions, phosphorous ions, Boron ions, Boron ions co-implanted with Carbon ions, Gallium ions co-implanted with Ge ions, or Indium ions.

16. The method of claim 12, wherein the buried layer is formed while maintaining the substrate at a temperature less than −30° Celsius.

17. The method of claim 12, wherein ions directly impact a top surface of the substrate through the mask opening.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The accompanying drawings illustrate exemplary approaches of the disclosure, including the practical application of the principles thereof, as follows:

[0009] FIG. 1 is a cross-sectional side view of a substrate and mask according to embodiments of the present disclosure;

[0010] FIG. 2 is a side cross-sectional view illustrating formation of a buried layer in the substrate using a low-temperature ion implant, according to embodiments of the present disclosure;

[0011] FIG. 3 is a side cross-sectional view illustrating formation of an oxide layer according to embodiments of the present disclosure;

[0012] FIG. 4 is a side cross-sectional view illustrating an annealing process according to embodiments of the present disclosure; and

[0013] FIG. 5 illustrates a schematic diagram of a processing apparatus according to embodiments of the present disclosure.

[0014] The drawings are not necessarily to scale. The drawings are merely representations, not intended to portray specific parameters of the disclosure. The drawings are intended to depict exemplary embodiments of the disclosure, and therefore are not be considered as limiting in scope. In the drawings, like numbering represents like elements.

[0015] Furthermore, certain elements in some of the figures may be omitted, or illustrated not-to-scale, for illustrative clarity. The cross-sectional views may be in the form of “slices”, or “near-sighted” cross-sectional views, omitting certain background lines otherwise visible in a “true” cross-sectional view, for illustrative clarity. Furthermore, for clarity, some reference numbers may be omitted in certain drawings.

DETAILED DESCRIPTION

[0016] Methods, devices, and systems in accordance with the present disclosure will now be described more fully hereinafter with reference to the accompanying drawings, where various embodiments are shown. The methods, devices, and systems may be embodied in many different forms and are not to be construed as being limited to the embodiments set forth herein. Instead, these embodiments are provided so the disclosure will be thorough and complete, and will fully convey the scope of the methods to those skilled in the art.

[0017] Embodiments of the present disclosure provide a novel low-temperature implantation process into a buried substrate layer to enable formation of a high-quality epitaxy layer thereupon. Unlike some prior art approaches that employ a pad oxide to block low dose regions of the substrate, the implant of the present disclosure may directly impact the substrate, thus applying to a wider variety of devices including, but not limited to, bipolar CMOS-DMOS (BCD), bipolar-CMOS (BiCMOS), or bipolar junction transistors (BJT).

[0018] FIG. 1 is a side cross-sectional view of a semiconductor device structure (hereinafter “device”) 100 at one stage of processing. Although non-limiting, the device 100 may eventually become a bipolar complementary metal-oxide-semiconductor (BiCMOS), a CMOS, a DMOS, etc. As shown, the device 100 may include a substrate or wafer 102 made from a semiconductor material. Although non limiting, the substrate 102 may be a bulk silicon wafer, a silicon-on-insulator (SOI) wafer, a silicon wafer with an epitaxial layer, or other substrate suitable for forming a semiconductor device. The semiconductor material may include silicon that is doped p-type or n-type, for example by boron or phosphorous. The semiconductor material may include silicon of a bulk silicon wafer, may include silicon of an epitaxial layer, or may include silicon of a transfer layer.

[0019] As shown, the mask 104 may be formed atop the substrate 102. The mask 104 may including an opening 106 formed therein. The opening 106 may expose a top surface 110 of the substrate. Although non-limiting, the mask 104 may include a photoresist formed by a photolithographic operation. The mask 104 may further include anti-reflection material such as a bottom anti-reflection coating (BARC). The mask 104 may be sufficiently thick to absorb atoms impacting the implant mask 104 during a subsequent implant process, so as to prevent degradation of performance parameters of the semiconductor device.

[0020] As shown in FIG. 2, a low-temperature ion implant process may be performed to deliver ions, such as antimony (Sb) ions or phosphorous (P) ions, into the substrate 102 to form a buried layer 120. An ion beam 118, including desired ions, may be directed at the substrate 102. The substrate 102 may be maintained at a temperature of 0 degrees Celsius or lower. In the embodiment shown, the buried layer 120 may be an n-type buried layer (NBL). In other embodiments, the buried layer 120 may be a p-type buried layer (PBL), which may be doped with ions such as B, Ga in Ge, indium (In), B with C, or BF.sub.2. As shown, the ion beam 118 may be delivered directly into the top surface 110 of the substrate 102 exposed within the opening 106 of the mask 104. In various embodiments, the ion beam 118 may be delivered as part of a cryogenic ion implant, which is performed between 0 and −100 degrees Celsius (C). In some embodiments, the cryogenic ion implant includes chilling a platen (not shown) upon which the substrate 102 is provided.

[0021] In some embodiments, the ion beam 118 may be delivered at a pre-defined angle, a predefined energy, a predefined dose, etc. In some embodiments, both a high current (e.g., 80 KeV or lower) and a medium current (e.g., 100 Kev or higher) can be used to generate high enough vacancies thus fully amorphized substrate 102. Although non-limiting, the implant angle may be perpendicular, or approximately perpendicular, to a plane defined by the top surface 110 of the substrate 102. The implantation angle may vary in other embodiments.

[0022] Next, as shown in FIG. 3, the mask 104 may be removed and an oxide layer (e.g., thermal oxide) 122 may be formed atop the substrate 102, including directly atop the buried layer 120. The oxide layer 122 may function as a capping layer to block dopant out-diffusion. Although non-limiting, the oxide layer 122 may be part of an anneal/diffusion process which anneals the semiconductor material in the buried layer 120 and diffuses the implanted antimony deeper into the substrate 102. During the ramp thermal oxidation process, the temperature of the substrate 102 may be increased, for example, from below 500° C. to above 1000° C. The oxide layer 122 may reduce loss of the implanted dopants, such as antimony, B, or Indium (but not limited to these species) through the top surface 110 of the semiconductor material. Furthermore, the silicon in the buried layer 120 may be partially amorphous or fully amorphous due to the high-dose implant before thermal oxidation process.

[0023] As shown in FIG. 4, the device 100 may then be subjected to an annealing process 128, which drives-in/activates dopants and moves defects (e.g., EOR defects) up to the top surface 110 for removal during a subsequent oxide removal process. The annealing process 128 may be a relatively lower furnace anneal (e.g., below 450° C.) or a higher temperature laser spike anneal (LSA). After oxidation and annealing steps, the buried layer is expected to be defect-free. Although not shown, the oxide layer 122 may then be removed, for example, by a wet etch process, which includes an aqueous solution of dilute buffered hydrofluoric acid. Other methods of removing the oxide layer 122 are within the scope of the present disclosure. After the oxide layer 122 is removed, an epitaxy step with in-situ doping (n-type or p-type) will be processed. Because of the defect-free buried layer, epitaxy quality is improved as compared to those processes using an implant.

[0024] FIG. 5 illustrates a schematic diagram of a processing apparatus 200 useful to perform processes described herein. One example of a beam-line ion implantation processing apparatus is the Varian VIISTA® Trident, available from Applied Materials Inc., Santa Clara, Calif. The processing apparatus 200 may include an ion source 201 for generating ions. For example, the ion source 201 may provide an ion implant, such as the low-temperature ion implant 118 demonstrated in FIG. 2. The processing apparatus 200 may also include a series of beam-line components. Examples of beam-line components may include extraction electrodes 203, a magnetic mass analyzer 211, a plurality of lenses 213, and a beam parallelizer 217. The processing apparatus 200 may also include a platen 219 for supporting a substrate 202 (wafer) to be processed. The substrate 202 may be the same as the substrate/wafer 102 described above. The substrate 202 may be moved in one or more dimensions (e.g. translate, rotate, tilt, etc.) by a component sometimes referred to as a “roplat” (not shown). It is also contemplated that the processing apparatus 200 may be configured to perform heated implantation processes.

[0025] In operation, ions of the desired species, for example, dopant ions, are generated and extracted from the ion source 201. Thereafter, the extracted ions 235 travel in a beam-like state along the beam-line components and may be implanted in the substrate 202. Similar to a series of optical lenses that manipulate a light beam, the beam-line components manipulate the extracted ions 235 along the ion beam. In such a manner, the extracted ions 235 are manipulated by the beam-line components while the extracted ions 235 are directed toward the substrate 202. It is contemplated that the apparatus 200 may provide for improved mass selection to implant desired ions while reducing the probability of undesirable ions (impurities) being implanted in the substrate 202.

[0026] In some embodiments, the processing apparatus 200 can be controlled by a processor-based system controller such as controller 230. For example, the controller 230 may be configured to control beam-line components and processing parameters associated with beam-line ion implantation processes. The controller 230 may include a programmable central processing unit (CPU) 232 that is operable with a memory 234 and a mass storage device, an input control unit, and a display unit (not shown), such as power supplies, clocks, cache, input/output (I/O) circuits, and the like, coupled to the various components of the processing apparatus 200 to facilitate control of the substrate processing. The controller 230 also includes hardware for monitoring substrate processing through sensors in the processing apparatus 200, including sensors monitoring the substrate position and sensors configured to receive feedback from and control a heating apparatus coupled to the processing apparatus 200. Other sensors that measure system parameters such as substrate temperature and the like, may also provide information to the controller 230.

[0027] To facilitate control of the processing apparatus 200 described above, the CPU 232 may be one of any form of general-purpose computer processor that can be used in an industrial setting, such as a programmable logic controller (PLC), for controlling various chambers and sub-processors. The memory 234 is coupled to the CPU 232 and the memory 234 is non-transitory and may be one or more of readily available memory such as random access memory (RAM), read only memory (ROM), floppy disk drive, hard disk, or any other form of digital storage, local or remote. Support circuits 236 may be coupled to the CPU 232 for supporting the processor in a conventional manner. Implantation and other processes are generally stored in the memory 234, typically as a software routine. The software routine may also be stored and/or executed by a second CPU (not shown) that is remotely located from the hardware being controlled by the CPU 232. The memory 234 is in the form of computer-readable storage media that contains instructions, that when executed by the CPU 232, facilitates the operation of the apparatus 200.

[0028] It is to be understood that the various layers, structures, and regions shown in the accompanying drawings are schematic illustrations. For ease of explanation, one or more layers, structures, and regions of a type commonly used to form semiconductor devices or structures may not be explicitly shown in a given drawing. This does not imply that any layers, structures, and/or regions not explicitly shown are omitted from the actual semiconductor structures.

[0029] In various embodiments, design tools can be provided and configured to create the datasets used to pattern the semiconductor layers of the device 100, e.g., as described herein. For example, data sets can be created to generate photomasks used during lithography operations to pattern the layers for structures as described herein. Such design tools can include a collection of one or more modules and can also be comprised of hardware, software or a combination thereof. Thus, for example, a tool can be a collection of one or more software modules, hardware modules, software/hardware modules or any combination or permutation thereof. As another example, a tool can be a computing

[0030] While certain embodiments of the disclosure have been described herein, the disclosure is not limited thereto, as the disclosure is as broad in scope as the art will allow and the specification may be read likewise. Therefore, the above description is not to be construed as limiting. Instead, the above description is merely as exemplifications of particular embodiments. Those skilled in the art will envision other modifications within the scope and spirit of the claims appended hereto.