Method of forming vias in silicon carbide and resulting devices and circuits

Abstract

A method of fabricating an integrated circuit on a silicon carbide substrate is disclosed that eliminates wire bonding that can otherwise cause undesired inductance. The method includes fabricating a semiconductor device including a Group III-V semiconductor layer on a surface on a silicon carbide substrate, wherein the semiconductor device defines at least one via through the silicon carbide substrate and the epitaxial layer.

Claims

1. A semiconductor device comprising: a silicon carbide substrate having a first main surface and a second main surface opposing the first main surface; an active epitaxial device layer on the first main surface of the silicon carbide substrate; a via extending from the second main surface into the silicon carbide substrate toward the first main surface; a first electrical contact over the active epitaxial device layer; and a second electrical contact overlying the second main surface and within the via, wherein the first electrical contact is separated from the second electrical contact at the active epitaxial device layer.

2. The semiconductor device of claim 1, wherein the active epitaxial device layer is silicon carbide.

3. The semiconductor device of claim 1, wherein the active epitaxial device layer comprises a gallium nitride layer and an aluminum gallium nitride layer.

4. The semiconductor device of claim 1, wherein the via extends entirely through the silicon carbide substrate to the active epitaxial device layer.

5. The semiconductor device of claim 1, further comprising additional vias extending from the second main surface into the silicon carbide substrate, wherein the via and the additional vias are disposed in an array.

6. The semiconductor device of claim 1, wherein the second electrical contact is metal.

7. The semiconductor device of claim 1, wherein a diameter of the via is between about 100 m and 1 mm.

8. The semiconductor device of claim 1, wherein the silicon carbide substrate is transparent.

9. The semiconductor device of claim 1, wherein the device further comprises an Al.sub.xGa.sub.1 xN layer on the first main surface of the silicon carbide substrate.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIGS. 1 through 13 are cross-sectional diagrams illustrating the method of forming a via through a silicon carbide substrate to a device in accordance with the present invention; and

(2) FIG. 14 is a scanning electron micrograph (SEM) of a via formed in a silicon carbide substrate according to the present invention.

(3) FIGS. 15-17 are cross sectional diagrams illustrating the method of forming the via through a silicon carbide substrate to a device by using the lift-off method to remove the indium-tin-oxide layer.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

(4) In a first aspect, the invention is a method of forming vias in particular materialspreferably, silicon carbide and Group III nitridesthat enables integrated circuits, and particularly monolithic microwave integrated circuits, to be formed on silicon carbide substrates with epitaxial layers on the substrate. The invention allows the devices to be connected to external circuitry in a manner that reduces the inductance problems that are characteristic of such MMICS when wire bonding is used to form electrical contacts for high frequency devices and circuits.

(5) FIGS. 1 through 11 illustrate in sequential fashion the basic steps of the method aspects of the present invention. These will be described somewhat generally, following which particular experimental details will be set forth. Because much of the background of MMICs and their function is well understood in this art, these will not be described in particular detail other than as necessary to highlight the invention. In the same manner, certain process steps are generally well understood so that where appropriate, these will be simply named rather than described in detail. The novel and non-obvious features of the invention, however, are set forth herein in sufficient detail to provide those referring to the specification with the ability to carry out the invention successfully and without undue experimentation.

(6) FIG. 1 is a cross sectional view of a silicon carbide substrate 20 with a semiconductor device fabricated thereon as indicated by the brackets 21. The device portion includes at least one epitaxial layer 29 on the second surface 28 of the silicon carbide substrate. Although FIG. 1 shows one epitaxial layer 29, the invention described herein applies equally to devices formed in a plurality of epitaxial layers on a silicon carbide substrate. As stated above, the purpose of the present invention is to form a via through the SiC substrate 20 and the epitaxial layer 29, and to use the via to provide an electrical path through the substrate 20 and to a contact 25. For descriptive purposes, FIGS. 1 through 11 illustrate a single via to one contact of a single device. It will nevertheless be understood that the method of the invention, and the resulting structure, are more typically applied to forming numerous vias to numerous devices that form a circuit. In particular, the method is particularly adept for forming conductive vias to the source 22, gate 23, and drain 24 regions of transistors formed in silicon carbide. Certain of the method steps of the invention are, however, most clearly set forth by simplifying the illustrations.

(7) Accordingly, FIG. 1 is meant to illustrate in broad fashion a silicon carbide substrate 20 with a semiconductor device fabricated thereon as indicated by the brackets 21. Representative semiconductor devices include metal-semiconductor field-effect transistors (MESFETs) or high electron mobility transistors (HEMTs) with appropriate source 22, gate 23, and drain 24 regions. In preferred embodiments, particularly for microwave frequency devices, the source 22, gate 23, and drain 24 regions are all formed in a wide band gap material such as silicon carbide, or certain of the Group III nitrides such as aluminum nitride (AlN), gallium nitride (GaN), and related binary, ternary, and tertiary Group III nitride compounds such as AlGaN and InAlGaN. The invention, therefore, encompasses devices that include a plurality of wide band-gap epitaxial layers on a silicon carbide substrate.

(8) The device 21 is formed on a silicon carbide substrate 20 that has a first surface 27 and a second surfaces 28.

(9) FIG. 2 illustrates the same substrate 20 and corresponding device 21 as FIG. 1, but with a conductive contact 25 in place on the uppermost surface 26 of the epitaxial layer. Those familiar with devices such as MESFETS and HEMTs will immediately recognize that an exemplary device may also include a contact to the gate region 23 and another to the drain region 24. As just noted, however, such contacts are not shown in FIGS. 1-11 for the purpose of simplifying the presentation of the relevant information. Accordingly, FIG. 2 simply shows the conductive contact 25 to the source region 22 of the illustrated device. It will be understood that when the device is formed entirely in a single portion of silicon carbide, the entire portion can be considered the substrate 20.

(10) The conductive contact 25 of the invention herein is preferably formed of platinum. Conventional metals may be used for any of the contacts in a particular embodiment.

(11) Alternatively, and without departing in any manner from the invention, the substrate can also include one or more epitaxial layers (epilayers) in which the device portion 21 is formed. In such embodiments, the surface 26 would refer to the uppermost surface (in the orientation of FIGS. 1-4) of the epitaxial layer. Those familiar with the growth of semiconductor materials, and particularly the growth of silicon carbide, will recognize that the use of a substrate and an epitaxial layer (or layers) even though made of the same material, provides a method of (in most circumstances) gaining an improved crystal lattice in the epitaxial layers (epilayers) as compared to the substrate.

(12) The fabrication of epilayers on a substrate is well understood in the art. The invention herein includes at least one and preferably a plurality of epitaxial layers made of semiconductor material other than silicon carbide. Group III nitride epilayers on a silicon carbide substrate are especially advantageous. The Group III nitride epilayers provide a wide band gap material in which a semiconductor device capable of operating at microwave frequencies may be formed. Epitaxial layers of particular interest include layers of gallium nitride for forming an HEMT or a MESFET therein. Other Group III nitride layers are particularly suitable for forming HEMTs therein. These other epitaxial layers include layers of InGaN, layers of InAlGaN, a combination of epitaxial layers made of AlGaN and GaN, and a combination of layers made of AlGaN, AlN, and GaN for forming HEMTs therein. The epilayers include a lower surface 29 in contact with the second surface 28 of a silicon carbide substrate 20 and an uppermost surface 26 for forming device contacts thereon.

(13) The Group III nitride semiconductor materials are especially advantageous for forming the channel region of a MESFET or an HEMT. An HEMT according to the invention herein includes a Group III nitride semiconductor material forming a barrier layer on a Group III nitride semiconductor channel layer as shown in HEMT 50 of FIG. 12. The barrier layer 54 of the HEMT 50 has a bandgap energy that is greater than the bandgap energy of the channel layer 52 so that the junction of the barrier layer 54 and the channel layer 52 yields a two dimensional electron gas. The two dimensional electron gas conducts a controllable current from the source 58 to drain 60 in the HEMT. The HEMT may also include a spacer layer 56, formed of a Group III nitride such as aluminum nitride, between the channel 52 and barrier 54 layers to optimize device performance.

(14) Certain embodiments of HEMTs may have various configurations for the source 58, gate 59 and drain 60 contacts. FIG. 12 illustrates one embodiment in which the source 58 and drain 60 contacts may be platinum deposits on the Group III nitride channel layer 52, and the gate contact 59 is a platinum deposit on the Group III nitride barrier layer 54. In an HEMT formed with a barrier layer 54 of AlGaN on a GaN channel layer 52 on a silicon carbide substrate 51, the gate contact 59 may be a platinum contact placed on the AlGaN layer because platinum exhibits rectifying behavior on AlGaN. The source and drain contacts 58, 60 of this embodiment may then be deposits of platinum that extend all the way to the GaN layer because platinum is ohmic on GaN.

(15) Other materials and positions for the source, gate, and drain contacts are possible in a transistor, depending upon the application at hand. FIG. 13 illustrates another embodiment in which the source 78, gate 79, and drain 80 contacts are made of appropriate materials that are ohmic or rectifying as needed on the barrier layer 77 of an HEMT 70. FIG. 13, therefore, shows an HEMT 70 formed with an AlGaN barrier layer 77 on a channel layer 76 of GaN on a silicon carbide substrate 75. The source 78, gate 79, and drain 80 contacts of FIG. 13 are made of materials that give the appropriate ohmic or rectifying current response on the AlGaN barrier layer 77. The gate contact 79 may be formed of titanium, platinum, chromium, alloys of tungsten and titanium, or platinum silicide and achieve a rectifying current response on the AlGaN barrier layer 77. The source and drain contacts 78, 80 may be formed of alloys of titanium, aluminum, and nickel and achieve the desired ohmic response on the AlGaN barrier layer 77. The invention herein, therefore, requires only that source and drain contacts be formed so that the source and drain contact material exhibits ohmic behavior when placed on an epitaxial layer made of a semiconductor material other than silicon carbide. Likewise, the gate contact must be formed of a contact material that exhibits rectifying behavior when placed on an epitaxial layer made of a semiconductor material other than silicon carbide.

(16) The placement of contacts on a silicon carbide based transistor requires considerations other than simple conductivity. The contact must respond appropriately when a current is conducted across it in a controlled circuit, as discussed above. The contact must also be conducive to standard fabrication techniques that are compatible with the remaining portions of the device. The invention herein emphasizes these considerations with the additional advantage of placing contacts on a transistor that are made of appropriate materials serving as electrical conduits and etch stops in the fabrication of conductive vias. Accordingly, FIG. 2 shows a conductive etch stop material, which may be indium-tin-oxide (ITO), or preferably platinum, in the form of a contact 25 placed at a predetermined position on the uppermost surface 26 of the epitaxial layer 29. As shown in greater detail below, the contact 25 has physical qualities that enable it to serve as an endpoint of a conductive via through the device. By serving the dual purpose of electrical contact and etch stop, the contact 25 alleviates the need for an extra etch stop material being added to the manufacturing process.

(17) FIG. 3 illustrates that in order to provide a high quality contact for the devices utilizing an indium-tin-oxide contact 25, the contact 25 is typically further coated with a noble metal 30 which in preferred embodiments is typically gold. The noble metal 30 would not be necessary for devices utilizing a platinum contact as the etch stop.

(18) At this point, one of the particular advantages of the invention can be highlighted: the use of conductive ITO, or platinum as the case may be, as the etch stop eliminates the need to add and remove another etch stop material before and after the etch step respectively. Instead, the ITO or platinum is simply incorporated into the device or circuit before the via is etched. Because the ITO or platinum etch stop does such double duty, fewer materials need be introduced into the process environment, and fewer process steps are required. As known those familiar with semiconductor manufacturing techniques, processes using fewer steps and fewer materials, yet producing the desired structures, are generally advantageous. Furthermore, eliminating a foreign etch stop material that would otherwise have to be both added and then removed, is particularly advantageous.

(19) FIG. 4 illustrates that in preferred embodiments, the device, particularly the uppermost epitaxial layer and the source 22, the gate 23, and the drain 24 regions, are covered with a protective polymer layer 31 which in preferred embodiments is a polyimide. The polyimide layer 31 protects the device underneath, and provides a leveling effect for the precursor for appropriate handling in the following manufacturing steps.

(20) FIG. 5 illustrates that in a next step, the polymer-coated uppermost surface 26 of the epitaxial layer 29 is mounted on a platen 32. The platen 32 is preferably formed of silicon carbide, in this case for its mechanical and thermal properties rather than its electronic advantages. Typically, a mounting adhesive 33 is used to fix the polyimide coated surface 31 to the platen 32. The mounting adhesive can be any appropriate material that will keep the polyimide-coated device and substrate fixed to the silicon carbide platen 32 during the subsequent processing steps while both withstanding those steps and avoiding any interference with them. Such adhesives are generally well known in the art and will not be described in detail herein.

(21) FIG. 6 illustrates that in the next step of the preferred method, the semiconductor substrate 20 is ground and polished until it is substantially transparent. The grinding and polishing are carried out for at least three reasons. First, because etching through silicon carbide is difficult under any circumstances, minimizing the thickness of the silicon carbide substrate 20 helps facilitate the overall etching process. Second, by grinding and polishing the substrate 20 until it is substantially transparent, an appropriate optical path can be defined from the first surface 27 of the substrate 20 to the metal contact 25 so that appropriate positions for the vias can be aligned and etched to the contact 25 in the desired manner, as described herein with respect to the remaining drawings. Third, the resulting thinner substrate (i.e., less mass) offers thermal advantages for the resulting device or MMIC.

(22) According to the present invention, when etching a via the front side etch stop pads should be conductive so that the multiple layers forming the integrated circuit will be connected, thereby allowing the circuit to perform its desired function. Further, the etch mask on the backside of the sample is preferably transparent to permit optical alignment (including visual alignment) of the sample with the front side etch stop.

(23) FIG. 7 illustrates that in the next steps of the preferred method of the invention, the first surface 27 of the substrate 20 is coated with a layer 34 of indium-tin-oxide (ITO). The ITO is selected and incorporated for at least two reasons. First, the ITO layer 34 can be formed to be transparent, so that the method of the invention can incorporate typical microlithography and masking techniques used in semiconductor design and manufacture. Second, and as discussed in the Experimental section to follow herein, the ITO provides a good masking material for SiC because the desired etchants discriminate as between SiC and ITO in a manner that is both desired and necessary during the etching process.

(24) In another embodiment, the layer 34 on the substrate's first surface 27 can comprise magnesium oxide (MgO), which offers the same advantagesselectivity and transparencyas ITO. As known to those familiar with MgO, it can be produced in a very dense form with a very high melting point (2800 C.).

(25) The ITO layer 34 is then coated with an appropriate photoresist layer 35. Photoresist compounds are generally well known in the art and will not be otherwise discussed in detail herein, other than to note that an appropriate photoresist material should be compatible with deposition on the ITO layer 34 and should provide an appropriate level of definition when exposed and developed. The exposed photoresist layer 35 provides a guide for etching the ITO layer 34, the substrate 20, and the epitaxial layer 29.

(26) FIG. 8 illustrates the precursor structure after the photoresist 35 has been masked, exposed, and developed, steps which can otherwise be carried out in conventional fashion provided they are consistent with the remainder of the process and materials. Opening the photoresist forms a defined opening 36 in the photoresist layer 35 through which the ITO layer 34 can be appropriately opened and then, as illustrated in FIG. 9, the appropriate via 37 can be formed.

(27) As FIG. 9 illustrates, the invention herein is a method of fabricating a semiconductor device with a via that is formed by etching steps to provide a conductive path from the first surface 27 of the substrate to the source 22, gate 23, or drain 24 regions of the device. The conductive path eliminates the need for wire bonding when the semiconductor device is incorporated into an integrated circuit because the contacts are electrically accessible through the via. The semiconductor device with the conductive via is fabricated by forming at least one epitaxial layer 29 of a wide bandgap semiconductor material other than silicon carbide on a silicon carbide substrate 20. The substrate preferably has first and second surfaces on opposite sides, and the at least one epitaxial layer 29 comprises a lower surface 38 in contact with the second surface 28 of the silicon carbide substrate 20 and an uppermost surface 26 for fabricating semiconductor device components thereon. Source 22, gate 23, and drain 24 regions of the device are defined by placing respective contacts at predetermined positions on the uppermost surface of the epitaxial layer 29 or layers.

(28) A mask is then applied to the first surface 27 of the silicon carbide substrate 20. The mask is aligned on the photoresist layer 35 to define points that will be opened by developing the photoresist layer using conventional means. Masking the first surface of the silicon carbide substrate defines predetermined locations for a plurality of conductive vias opposite from and aligned with the predetermined positions for the contacts connected to the source 22, gate 23, and drain 24 regions.

(29) Next, a plurality of conductive vias are etched through the silicon carbide substrate 20 and through the epitaxial layer, or epitaxial layers 29, to provide conductive paths from the first surface of the silicon carbide substrate 27 to each respective contact on the source 22, gate 23, or drain 24 region.

(30) The inventors herein have developed a series of steps to conveniently and accurately etch all of the layers necessary in fabricating semiconductor devices on a silicon carbide substrate.

(31) In certain embodiments of the invention, the transparent ITO layer 34 is etched within the region defined by the mask with a first reactive ion etch. This first reactive ion etch may be carried out using boron trifluoride as the etchant or etched in chorine chemistry.

(32) In a more preferred embodiment, openings in the ITO layer 34 are accomplished by using a traditional lift-off technique. In lift-off, the bare substrate 20 onto which the ITO 34 will be patterned is covered with photoresist 35. In this embodiment, therefore, the order of layers 34 and 35 are reversed from that shown in FIGS. 7-9 and are shown in detail in FIGS. 15-17. Traditional patterning of the photoresist 35 using ultraviolet irradiation through a patterned opaque screen and a wet chemical developer is used to expose only the regions of the substrate 20 surface that will become the etch mask. Typically, circular or oval islands of photoresist remain as the regions which will eventually become the etched via holes in the substrate 20. Subsequently, an ITO film 34 is deposited onto the patterned substrate. The ITO-covered, patterned wafer is then immersed into a solvent that dissolves the photoresist islands, and the ITO 34 resting on top of the photoresist 35 is also removed. Typically, acetone can be used to dissolve the photoresist 35. The result is a thin film of ITO mask on the substrate with predetermined openings that expose the substrate to an etchant. In this manner, the openings in the ITO guide the etching process for forming vias in the semiconductor layers.

(33) The silicon carbide substrate 20 is etched next with an etchant that removes silicon carbide but does not remove the material other than silicon carbide forming the epitaxial layer 29 on the second surface 28 of the substrate 20. Etching of the silicon carbide, therefore, stops at an epitaxial layer 29 on the substrate 20. In one embodiment, the step of etching the silicon carbide substrate includes etching within the region defined by the mask with an inductively coupled plasma. The inductively coupled plasma etching of the silicon carbide substrate may be carried out in fluorine chemistry using sulfur hexafluoride (SF.sub.6) as the etchant.

(34) Third, the epitaxial layer 29, or layers, are etched with an etchant that removes the material other than silicon carbide, forming the epitaxial layer 29, but does not remove the silicon carbide or the materials used to form source, gate, or drain contacts, so that etching the epitaxial layer 29 stops at each respective source, gate, and drain region. The step of etching the epitaxial layer, or layers, preferably includes etching within the region defined by the mask with a second reactive ion etch. In one embodiment, chlorine chemistry is used to etch the epitaxial layers in the reactive ion etch.

(35) In the preferred embodiment, upon completing the etching process, the ITO layer is effectively removed using solutions of hydrochloric acid and de-ionized water having an acid content in the range of about 7% to about 50% hydrochloric acid. Typical embodiments use a 1:1 ratio of hydrochloric acid and de-ionized water. The method herein could also include grinding off the transparent ITO layer 34 to ensure metal adhesion to the backside of the substrate when installing the overall device in a circuit. The first surface 27 of the silicon carbide substrate 20 is then subject to further inductively coupled plasma etching in a fluorine chemistry, after grinding off the transparent layer, to repair any damage to the substrate caused by grinding.

(36) The steps of the etching process yield precursor products at certain points in the method described herein. The invention, therefore, includes circuit precursors at different levels of fabrication and etching. For example, one circuit precursor includes a polished silicon carbide substrate 20 having respective first and second surfaces 27 and 28, at least one Group III nitride epitaxial layer 29 on the second surface 28 of a silicon carbide substrate 20, an uppermost surface 38 of the epitaxial layer 29 for forming electrical contacts thereon, a semiconductor device 21 in the epitaxial layer 29, respective contacts, one of which is shown by example 25 on the uppermost surface 26 for defining source 22, gate 23, and drain 24 regions for a semiconductor device 21 in the epitaxial layer 29, a polymer coating covering the entire epitaxial layer 29 including the contacts, and a transparent layer 34 selected from the group consisting of indium-tin-oxide and magnesium oxide on the first surface of the polished transparent substrate.

(37) A circuit precursor may include at least one via extending from the layer of photoresist 35 on the silicon carbide substrate 20, through the silicon carbide substrate, to the second surface 28 of the substrate under the epitaxial layers. Alternatively, a circuit precursor according to this invention may comprise at least one via extending through the silicon carbide substrate 20 and through the at least one epitaxial layer 29, from the first surface of the substrate all the way to the contacts, shown in the figures by example contact 25.

(38) In a particularly advantageous step, the method of the invention incorporates the original conductive contact 25 as the etch stop. In one preferred embodiment, the conductive contact 25 is made of platinum for each respective source, gate and drain, which may serve as a useful etch stop in etching the epitaxial layers. The reactive ion etch utilizing chlorine chemistry, described above for etching the epitaxial layers, does not etch platinum. The platinum contact of the semiconductor device, therefore, serves as the etch stop. In this manner, the method of the invention avoids using additional stepsand (often just as importantly) additional materialsto add and then remove a separate etch stop. Again, it is to be understood that although the Figures illustrate only one via, such is for the purpose of clarifying the illustrations, and the invention is advantageously used for opening multiple vias.

(39) FIG. 10 illustrates that in preferred embodiments, the via is metallized to provide a conductive path from the first surface of the substrate to each respective source, gate, and drain contact. In a preferred embodiment, the via is first sputter-coated with three layers of metal: titanium, platinum, and gold (Ti/Pt/Au), in that order, along the floor and walls of the etched trench. This coating is designated as 40 in FIG. 10. The coating 40 is then electroplated with a noble metal 41, preferably gold, to form the complete contact from the first surface 27 of the substrate 20 through the substrate to the lower surface of the epitaxial layer 26, and more particularly to the contact 25 which is part of the device portion 21. In preferred embodiments, the photoresist and indium-tin-oxide layer 34 and the photoresist layer 35 are both removed prior to the step of sputter coating with the Ti/Pt/Au coating 40 and the electroplating with the gold 41. The device precursor is then removed from the platen 32 and the protective polyimide layer 31 is stripped to produce the resulting device illustrated in FIG. 11.

(40) FIG. 14 is an SEM micrograph of a 100 micron diameter via hole etched in a 4 mil (1000 mil=1 inch) silicon carbide wafer according to the present invention. Although FIGS. 1-13 are drawings and FIG. 14 is a photograph, by way of comparison, the top surface illustrated in FIG. 14 corresponds to the first surface 27 in the drawings. As understood by those of skill in this art, the ability to put vias of this diameter in silicon carbide substrates of this thickness, makes broadband, high frequency MMICS possible in desirable silicon carbide substrates.

(41) The invention is a method of etching vias, typically (although not necessarily limited to) about 25 to 200 microns in diameter through a silicon carbide substrate, 100 to 200 microns thick. The inventive etch process yields an etch rate of between about 0.5 and 0.8 microns per minute (/min.), a selectivity to the etch mask of 150, and anisotropy of 90 to 99%.

(42) The central issue of etching vias in silicon carbide is finding an etch process which etches silicon carbidea material of high stability and high bond strengtha reasonable rate (e.g., 0.5 /min) while minimizing the erosion of the etch mask.

(43) The invention satisfies these diametrically opposing requirements by the choice of mask material, plasma parameters, and chemistry.

(44) In the invention, indium-tin-oxide (ITO) is the preferred etch mask for vias in silicon carbide for several reasons. First, ITO is stable and does not etch in the fluorine chemistry that is most efficient and preferred for etching silicon carbide. Second, unlike other hard metal masks, ITO does not sputter at the ion energies that are sufficient to break silicon carbide bonds, and thus can etch silicon carbide. Third, ITO is also transparent, which allows the etch mask to be aligned through the wafer to the edge pads. Fourth, ITO may also be used for the etch stop, because it is conductive and a can serve as the material on which the etch stops.

(45) As noted above, one of the best etch masking materials for vias etches in silicon carbide is Indium-Tin-Oxide (ITO). The ITO etch mask is patterned as follows. The wafer is first blanket coated with ITO, then with photoresist. The photoresist is exposed through a mask with UV light and the exposed areas harden, thus transferring the mask pattern onto the photoresist. The photoresist acts as a mask in the subsequent etch of the ITO in the chlorine chemistry, thus transferring the pattern of the photomask onto the ITO. The ITO then acts a mask in the subsequent etch of the silicon carbide vias in fluorine chemistry.

(46) An inductively coupled plasma (ICP) is used in the invention to generate a high density SF.sub.6 plasma to etch vias in silicon carbide for several reasons. First achieving a high etch rate in the silicon carbide while minimizing the erosion of the etch mask requires a high density and low energy plasma. The use of ICP is critical for this purpose because it allows a high density plasma to be generated, and it permits the independent control of plasma density by adjusting the coil power and ion energy by adjusting the chuck power. A high coil power (600-1500 W with about 800 W preferred) is selected to maximize plasma density.

(47) An important point of the invention is the use of a chuck power in the ICP system that maximizes the etch rate of the silicon carbide while keeping the erosion of the ITO or MgO etch mask minimal. As the chuck power is increased in an ICP system, the etch rate of the silicon carbide increases; this increase, however, is much more drastic at low chuck powers than at high chuck powers. As the chuck power is increased the erosion rate of the ITO or MgO etch mask is minimal and does not increase initially; at higher chuck powers, however, it increases rapidly. Thus, the invention incorporates the recognition that a chuck power can be selected that on one hand maximizes SiC etch rate and on the other hand maximizes the difference in the etch rates of SiC and ITO etch mask. In preferred embodiments, this chuck power level is determined to be between about 1 to 2 watts of power per square centimeter (Wcm.sup.2) presently being preferred.

(48) In preferred embodiments, the invention incorporates sulfur hexafluoride (SF.sub.6) chemistry to etch vias in silicon carbide, because it is deemed to be the most efficient of the fluoride chemistries for such purpose. The invention does not use any gas additive, as it tends to slow down the etch rate of the silicon carbide and speeds up the mask erosion by sputtering. The invention uses SF.sub.6 at a pressure of 1 to 5 milliTorr (mT), with about 3 mT being preferred. Similarly, the gas is supplied at a rate of between about 5 and 100 standard cubic centimeters per minute (sccm), with about 10 sccm being preferred.

(49) In further investigations employing the use of SF.sub.6, it was determined that SF.sub.6 yielded a higher SiC to ITO mask selectivity (approximately 150:1) than NF.sub.3 or CF.sub.4 (approximately 70:1). As discussed above, conventional methods of etching SiC included the use of NF.sub.3 or SF.sub.6 diluted with Ar and CF.sub.4/O.sub.2. Upon investigation, however, the addition of Ar or O.sub.2 to SF.sub.6 or NF.sub.3 reduced the etch rate in SiC and increased mask erosion due to the lower percentage of fluorine and greater ion bombardment. Thus, the use of SF.sub.6 without additional gases is preferable in achieving the increased etch rate and high selectivity with respect to an ITO mask of the present invention.

(50) The etch rate of a via can be increased by raising the temperature of the substrate or thin film applied thereon. Elevations in temperature may be achieved by halting the flow of helium to the backside of the sample, which serves to cool the sample. Otherwise, the backside pressure is maintained at between about 1 and 10 torr. The chemical reactions affecting the etch rate (e.g., breaking of molecular bonds) can also be increased by increasing the gas flow and chamber pressure.

(51) An increase in the chemical reactions affecting the via etch results in an increased lateral etch and, thus, sidewall slope of the via. The increase in the chemical reactions also leads to an increase in the etch rate and erosion of the ITO mask. Further, spiking and surface imperfections may result from the enhanced chemical reactions.

(52) As exemplified by the referenced cited in the Background, the equipment and processes used to generate inductively coupled plasmas are generally well-known and well-understood in this art. Accordingly, the techniques described herein can be carried out by those of ordinary skill in this art, and without undue experimentation.

EXPERIMENTAL

(53) In preferred embodiments, the present invention also comprises a method of dry etching a via in SiC using sulfur hexafluoride chemistry in an inductively coupled plasma (ICP). In a particular embodiment of the invention, the dry etching was conducted in a Model 790 ICP system manufactured by Plasma-Therm Incorporated.

(54) In this system, the wafer is placed on a He-cooled chuck in the process chamber, the wafer is clamped and subsequently the process chamber is evacuated to 10.sup.5 Torr with a turbo and mechanical pump. Five to twenty cubic centimeter per minute electronic grade sulfur hexafluoride is injected into the process chamber and a butterfly valve above the turbo pump is throttled to achieve the operating pressure of 2 to 5 mT. Subsequently, power is applied to generate a plasma. This system uses two radio frequency (RF) power sources. One is connected to the chuck and is used to control energies of ions reaching the substrate and is set between 1 to 2 W/cm.sup.2. The second RF source is connected to a three turn inductor coil wrapped around the ceramic process chamber. The second RF source provides the main plasma generating power, controls plasma densities and is set between 800 and 1200 W.

(55) Prior to etching the via, the SiC substrate is coated with ITO, then patterned with photoresist using standard photolithography. The ITO is then dry etched in chlorine chemistry in which the photoresist is the etch mask. Vias are subsequently etched in SiC in fluorine chemistry in which the ITO is the etch mask. The via dry etch process is highly anisotropic, with SiC etch rate of 0.5 to 0.8 micron/min, and selectivity to the etch mask of 100 to 150.

(56) In the specification, there have been disclosed typical embodiments of the invention, and, although specific terms have been employed, they have been used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being set forth in the following claims.