Method for fabricating a JFET transistor within an integrated circuit and corresponding integrated circuit

Abstract

An integrated circuit of the BiCMOS type includes at least one vertical junction field-effect transistor. The vertical junction field-effect transistor is formed to include a channel region having a critical dimension of active surface that is controlled by photolithography.

Claims

1. A method for fabricating an integrated circuit including a vertical junction field-effect transistor and a field effect transistor, comprising: forming, in a first semiconductor well of a first type of conductivity, two spaced apart gate regions of a second type of conductivity which define a channel region of the vertical junction field-effect transistor; forming, in the first semiconductor well, a field implantation region surrounding the channel region and two spaced apart gate regions; forming, in a second semiconductor well of the first type of conductivity, source and drain regions of the second type of conductivity for the field effect transistor; forming, in the first semiconductor well, contact regions of the second type of conductivity which electrically connect the two spaced apart gate regions of the vertical junction field-effect transistor to the field implantation region of the vertical junction field-effect transistor; wherein a same dopant implantation step is used to form the source and drain regions for the field effect transistor and the contact regions for the vertical junction field-effect transistor.

2. The method of claim 1, wherein forming the two spaced apart gate regions comprises: forming two spaced apart trenches in said first semiconductor well that bound said channel region; and filling the two spaced apart trenches with a semiconductor material of a second type of conductivity.

3. The method of claim 2, wherein forming the field implantation region comprises: forming a field trench in said first semiconductor well; and filling the field trench with said semiconductor material of the second conductivity type; wherein a same etching step is used to form the two spaced apart trenches and the field trench in the first semiconductor well; and wherein a same deposition step is used to fill the two spaced apart trenches and the field trench.

4. The method of claim 3, wherein the integrated circuit further includes a bipolar transistor, further comprising: forming a base region in a third semiconductor well for the bipolar transistor; and forming an emitter region in the base region; wherein said same dopant implantation step is used to form the source and drain regions for the field effect transistor, the contact regions for the vertical junction field-effect transistor and the emitter region of the bipolar transistor.

5. A method for fabricating an integrated circuit including a vertical junction field-effect transistor and a field effect transistor, comprising: forming, in a first semiconductor well of a first type of conductivity, two spaced apart gate regions of a second type of conductivity which define a channel region of the vertical junction field-effect transistor; forming, in a second semiconductor well of the first type of conductivity, source and drain regions of the second type of conductivity for the field effect transistor; forming insulating regions in the first semiconductor well over the two spaced apart gate regions and in the second semiconductor well delimiting a region which contains the source and drain regions; forming, in the first semiconductor well, contact regions of the second type of conductivity, each contact region positioned adjacent insulating regions in the first semiconductor well over the two spaced apart gate regions and extending under said insulating regions to make contact with the two spaced apart gate regions of the vertical junction field-effect transistor; wherein a same dopant implantation step is used to form the source and drain regions for the field effect transistor and the contact regions for the vertical junction field-effect transistor.

6. The method of claim 5, wherein forming the two spaced apart gate regions comprises: forming two spaced apart trenches in said first semiconductor well that bound said channel region; and filling the two spaced apart trenches with a semiconductor material of a second type of conductivity.

7. The method of claim 6, further comprising forming a field implantation region surrounding the channel region and two spaced apart gate regions, wherein forming the field implantation region comprises: forming a field trench in said first semiconductor well; and filling the field trench with said semiconductor material of the second conductivity type; wherein a same etching step is used to form the two spaced apart trenches and the field trench in the first semiconductor well; and wherein a same deposition step is used to fill the two spaced apart trenches and the field trench.

8. The method of claim 7, wherein forming said contact regions in the first semiconductor well comprises forming said contact regions to electrically connect the two spaced apart gate regions of the vertical junction field-effect transistor to the field implantation region of the vertical junction field-effect transistor.

9. The method of claim 7, wherein the integrated circuit further includes a bipolar transistor, further comprising: forming a base region in a third semiconductor well for the bipolar transistor; and forming an emitter region in the base region; wherein said same dopant implantation step is used to form the source and drain regions for the field effect transistor, the contact regions for the vertical junction field-effect transistor and the emitter region of the bipolar transistor.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Other advantages and features of the invention will become apparent upon examining the detailed description of non-limiting embodiments and their implementation and from the appended drawings in which:

(2) FIGS. 1 to 8 show embodiments of the invention and their implementation.

DETAILED DESCRIPTION

(3) For the sake of clarity, as is common in the representation of integrated circuits, FIGS. 1 to 8 are shown schematically and are not to scale, the common elements from one figure to another being denoted using the same references.

(4) Furthermore, in the following, the first type of conductivity will be denoted as being the N type and the second type of conductivity as being the P type, even though the reverse is also possible according to the invention.

(5) FIG. 1 illustrates one example of a vertical junction field-effect transistor T1, forming part of an integrated circuit CI formed on a semiconductor substrate 10 with P-type doping. This transistor T1 is notably fabricated within a semiconductor well 21 with N-type doping and comprises a drain region, a source region 81, a gate region 46, and a channel region ZC.

(6) The drain region comprises a buried layer 11 of the N.sup.+ type, more highly doped than the well 21, and a contact well 31 also highly-doped of the N.sup.+ type. The contact well 31 extends from the surface of the well 21 down to the buried layer 11.

(7) The gate region 46 comprises two neighboring vertical trenches filled with a highly-doped semiconductor material of the P.sup.+ type. These trenches bound the vertical channel region ZC between them. The distance D between these trenches defines the critical dimension of active surface of the channel of the transistor.

(8) Highly-doped gate contact regions 71 of the P type are disposed on the surface of the well 21 and in contact with the gate regions 46.

(9) The highly-doped source region 81 of the N.sup.+ type is formed on top of the channel region ZC, also on the surface of the well 21.

(10) Furthermore, local regions of oxidation 50 are formed between the gate contact regions 71 and the source region 81 and between the gate contact regions 71 and the drain contact well 31, in order to insulate these regions from one another. Similarly, local regions of oxidation 50 are formed at the lateral ends of the surface of the well in order to insulate the transistor T1 from the rest of the integrated circuit CI of which it forms a part.

(11) These regions 50 may be of the LOCOS type or else shallow trenches (STI: Shallow Trench Isolation).

(12) FIG. 2 illustrates the result of initial steps of one example of a method for fabricating an integrated circuit CI. The integrated circuit CI here comprises five regions Z1, Z2, Z3, Z4, and Z5, bounded in the following figures by dashed lines, in which a JFET transistor T1, a bipolar transistor of the NPN type T2, an insulated-gate field-effect transistor of the PMOS type T3, a bipolar transistor of the PNP type T4 and an insulated-gate field-effect transistor of the NMOS type T5 will respectively be fabricated according to one embodiment of the invention.

(13) Within a substrate 10 of silicon with P-type doping, highly-doped buried layers 11, 12, 13 of the N.sup.+ type have been formed by shallow implantation in the respective regions Z1, Z2, Z3 of the substrate 10. Semiconductor wells 21, 22, 23 with N-type doping have been formed by epitaxy on top of these buried layers 11, 12, 13, respectively.

(14) Similarly, highly-doped buried layers 14, 15 of the P.sup.+ type have been formed by shallow implantation in the respective regions Z4, Z5, on which wells with n-type doping have been formed by epitaxy, then respectively converted into wells 24, 25 with P-type doping by ion implantation and diffusion of the dopants.

(15) Highly-doped contact wells 31, 32 of the N.sup.+ type have also been formed by implantation into the wells 21, 22. A highly-doped contact well 34 of the P.sup.+ type has been formed by implantation into the well 24.

(16) Each contact well 31, 32, 34 extends from the surface of the respective semiconductor well down to the respective buried layer.

(17) In the following step, illustrated by FIG. 3, a layer of masking resist 40 is deposited on the surface of the wells 21 to 25 then etched according to a pattern pre-established by photolithography, exposing etch sites 40 on the surface of the wells 21 and 22.

(18) Shallow trenches are etched into the wells 21 and 22 at the location of the etch sites 40.

(19) A highly-doped semiconductor material of the P.sup.+ type is deposited into the trenches, forming field implantation regions 41, 42 in the respective wells 21, 22, and two gate regions 46 of the future JFET transistor in the well 21.

(20) The future channel region ZC of the JFET transistor has thus been formed between the two gate regions 46, whose critical dimension of active surface D is controlled by photolithography.

(21) Indeed, the lateral diffusion of the dopants in the well 21 is negligible compared with the dimension D and thus the dimension D is precisely determined by the corresponding part of the pattern transferred onto the resist.

(22) Furthermore, the channel region ZC has been formed simultaneously with steps for fabrication of the NPN transistors of the integrated circuit.

(23) FIG. 4 illustrates the result of steps not shown, amongst which a second masking has been implemented in order to form field implantation regions 44 within the well 24 with a highly-doped material of the N type.

(24) Active regions of the integrated circuit CI have been bounded by local oxidations 50 on the surface of the wells 21 to 25, for example according to a known method of the LOCOS type (acronym coming from LOCal Oxidation of Silicon).

(25) Implantations of dopants have also been carried out, forming an intrinsic base region 52 and an extrinsic base region 62 respectively P-doped and highly-doped of the P.sup.+ type within the well 22, and an intrinsic base region 54 and an extrinsic base region 64 respectively doped N and highly-doped of the N.sup.+ type within the well 24.

(26) The following step, shown in FIG. 5, is a photolithography step common to all the formations of the JFET, PMOS and PNP transistors.

(27) A layer 70 of resist is deposited onto the surface of the wells 21 to 25 in which openings, also formed by photolithography according to a pre-established pattern, expose implantation sites 70 on the surfaces of the wells 21, 23 and 24.

(28) A dopant of the P type is implanted at high density and to a shallow depth into these implantation sites 70, simultaneously forming an emitter 74 of the future PNP transistor, the gate contact regions 71 of the future JFET transistor, and the source and drain regions 73 of the future PMOS transistor, within the corresponding wells 24, 21 and 23.

(29) The following step, shown in FIG. 6, is a photolithography step common to the formations of the JFET, NPN and NMOS transistors.

(30) A layer 80 of resist is deposited on the surface of the wells 21 to 25 in which openings, also formed by photolithography according to a pre-established pattern, expose implantation sites 80 on the surface of the wells 21, 22 and 25.

(31) A dopant of the N type is implanted at high density and to a shallow depth into these implantation sites 80, simultaneously forming an emitter 82 of the future transistor NPN, the source 81 of the future JFET transistor, and the source and drain regions 85 of the future NMOS transistor.

(32) FIG. 7 shows an integrated circuit obtained according to one embodiment, comprising a vertical junction field-effect transistor T1, a bipolar transistor of the NPN type T2, a bipolar transistor of the PNP type T4, a PMOS transistor T3 and an NMOS transistor T5. The insulated gates of the PMOS transistor T3 and NMOS transistor T5 have been formed in a conventional manner and comprise an insulating layer 93, for example of silicon oxide, and a layer of gate material 95, for example polycrystalline silicon.

(33) The following steps for contact formation, including for example steps for silicidation and for deposition of contacts, are carried out in a conventional manner and are not shown.

(34) FIG. 8 shows schematically a cellular structure architecture for JFET transistors of the type of the transistor T1 shown in FIG. 1, in the plane P2, seen as a top view.

(35) The cellular structure SCEL comprises several unitary cells CEL.sub.i, and each unitary cell CEL.sub.i comprises a JFET transistor notably comprising a drain region 31, two gate contact regions 71 and a source region 81.

(36) The saturation drain current is known and controlled for each unitary cell. Thus, a saturation drain current may be adjusted to a desired value by connecting several unitary cells in parallel.

(37) The saturation drain current of the cellular structure is then equal to the sum of the saturation drain currents of each unitary cell connected in parallel.

(38) The cellular structure architecture of JFET transistors avoids having to fabricate the JFET transistors that are more extended in order to obtain a higher saturation drain current, extended JFET transistors exhibiting edge effects that are difficult to control and to model.

(39) It is clear that the present invention is capable of several variants and modifications which will be apparent to those skilled in the art. In particular, the invention may be applied to the fabrication of a JFET transistor with a channel of the P type by reversing the corresponding types of conductivity.