Method for producing a nitride compound semiconductor device

Abstract

A method for procuring a nitride compound semiconductor device is disclosed. In an embodiment the method includes growing a first nitride compound semiconductor layer onto a growth substrate, depositing a masking layer, growing a second nitride compound semiconductor layer onto the masking layer, growing a third nitride compound semiconductor layer onto the second nitride compound semiconductor layer such that the third nitride compound semiconductor layer has non-planar structures and growing a fourth nitride compound semiconductor layer onto the non-planar structures such that the fourth nitride compound semiconductor layer has an essentially planar surface. The method further includes growing a functional layer sequence of the nitride compound semiconductor device, connecting a side of the functional layer sequence located opposite to the growth substrate to a carrier and removing the growth substrate.

Claims

1. A method for producing a nitride compound semiconductor device, the method comprising: growing a first nitride compound semiconductor layer onto a growth substrate; depositing a masking layer; growing a second nitride compound semiconductor layer onto the masking layer; growing a third nitride compound semiconductor layer onto the second nitride compound semiconductor layer such that the third nitride compound semiconductor layer has non-planar structures; growing a fourth nitride compound semiconductor layer onto the non-planar structures such that the fourth nitride compound semiconductor layer has an essentially planar surface; growing a functional layer sequence of the nitride compound semiconductor device; connecting a side of the functional layer sequence located opposite to the growth substrate to a carrier; removing the growth substrate; and producing coupling-out structures on a surface of the nitride compound semiconductor device facing away from the carrier by an etching process which removes at least part of the first, second and third nitride compound semiconductor layers, wherein the method is performed in the recited order.

2. The method according to claim 1, wherein the non-planar structures are pyramidal structures.

3. The method according to claim 1, wherein the non-planar structures include side facets which are constituted by a [1-101] crystal face or an [11-22] crystal face.

4. The method according to claim 1, wherein at least part of the coupling-out structures are constituted by a [1-101] crystal face or an [11-22] crystal face.

5. The method according to claim 1, wherein the non-planar structures have an average height of between 1 m and 5 m.

6. The method according to claim 1, wherein the etching process is a wet chemical etching process.

7. The method according to claim 1, wherein the second nitride compound semiconductor layer and/or the fourth nitride compound semiconductor layer are produced at a growth temperature higher than 1,050 C.

8. The method according to claim 1, wherein the third nitride compound semiconductor layer is produced at a growth temperature which is by at least 40 C. lower than the growth temperature of the second nitride compound semiconductor layer.

9. The method according to claim 1, wherein the nitride compound semiconductor layers are produced by a metal organic vapor phase epitaxy, wherein NH.sub.3 is used as a reaction gas, and wherein an NH.sub.3 gas flow is at least 70% smaller in an formation of the second and third nitride compound semiconductor layers than in an formation of the fourth nitride compound semiconductor layer.

10. The method according to claim 1, wherein the masking layer is a silicon nitride layer.

11. The method according to claim 1, wherein the masking layer has a plurality of openings of an average lateral extent of between 100 nm and 1,000 nm.

12. The method according to claim 1, wherein the growth substrate is a sapphire substrate.

13. The method according to claim 1, wherein the functional layer sequence includes an n-type semiconductor region, a p-type semiconductor region, and an active layer disposed between the n-type semiconductor region and the p-type semiconductor region.

14. The method according to claim 1, wherein the nitride compound semiconductor device is a light-emitting diode.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The invention is explained in more detail below with reference to embodiments illustrated in FIGS. 1 to 7.

(2) In the drawings,

(3) FIGS. 1 to 7 are schematic views of an embodiment of the method which each illustrate an intermediate method step.

(4) In the Figures, identical or identically acting components are in each case provided with the same reference numerals. The components illustrated and the size ratios of the components to one another should not be regarded as to scale.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

(5) In the first step of the method as schematically illustrated in FIG. 1, a first nitride compound semiconductor layer 1 has been grown onto a growth substrate 10. The growth substrate 10 is preferably a sapphire substrate.

(6) The first nitride compound semiconductor layer 1 shown here, same as the additional nitride compound semiconductor layers deposited in subsequent method steps, comprises a III nitride compound semiconductor material, preferably In.sub.xAl.sub.yGa.sub.1-x-yN, with 0x1, 0y1 and x+y 01. However, this material does not necessarily have to be of a mathematically exact composition according to the above formula. In fact, it may include one or plural dopants as well as additional components which will basically not change the characteristic physical properties of the In.sub.xAl.sub.yGa.sub.1-x-yN material. For the sake of simplicity, the above formula only contains the most essential components of the crystal lattice (In, Al, Ga, N) even if these may partially be replaced by small amounts of other substances. The first nitride compound semiconductor layer 1 may in particular be a GaN layer.

(7) Growing the first nitride compound semiconductor layer 1 is performed in the same way as growing the additional nitride compound semiconductor layers, preferably by means of metal organic vapor phase epitaxy (MOVPE). The first nitride compound semiconductor layer 1 preferably has a thickness of between 10 nm and 1,000 nm, for example, of approx. 300 nm.

(8) It is possible to deposit a thin nucleation layer (not shown) on the growth substrate 10, for example, by sputtering, before growing the first nitride compound semiconductor layer 1. The nucleation layer can in particular contain AlN.

(9) In the intermediate step of FIG. 2, a masking layer 11 has been deposited on the first nitride compound semiconductor layer 1. The masking layer 11 is formed from a material onto which a nitride compound semiconductor cannot be grown easily. The masking layer 11 is preferably a silicon nitride layer. The masking layer 11 preferably has a plurality of openings of an average lateral extent of between approx. 100 nm and 1,000 nm. The areas of the masking layer 11 disposed between the openings advantageously have a lateral extent b of between approx. 10 nm and 500 nm.

(10) In the intermediate step of FIG. 3, a second nitride compound semiconductor layer 2 has been grown onto the first nitride compound semiconductor layer 1 and the masking layer 11. The second nitride compound semiconductor layer 2 grows primarily in the openings in the masking layer, in which case the material of the second nitride compound semiconductor layer 2 can laterally overgrow at least part of the masking layer 11. The second nitride compound semiconductor layer 2 is, for example, deposited by means of MOVPE using an NH.sub.3 gas flow of between 10 slm and 50 slm at a growth rate of 1 m/h.

(11) The second nitride compound semiconductor layer 2 is preferably grown at a growth temperature of above 1,050 C. The growth temperature is in particular chosen so as to produce substantially two-dimensional growth. In other words, the nitride compound semiconductor material of the second nitride compound semiconductor layer 1 essentially grows in a [0001] crystal direction, with the surface of the growing crystallites being thus constituted primarily by a [0001] crystal plane which is also referred to as the c-plane. The growth of the second nitride compound semiconductor layer 2 is advantageously stopped before the growing crystallites have coalesced.

(12) In another method step schematically illustrated in FIG. 4, a third nitride compound semiconductor layer 3 has been grown onto the second nitride compound semiconductor layer 2. For growing the third nitride compound semiconductor layer 3, growth conditions are changed so as to yield essentially three-dimensional growth of the crystallites. In particular, this can be brought about by reducing the growth temperature by at least 40 C., preferably by approx. 50 C. to 80 C., relative to the growth temperature of the second nitride compound semiconductor layer 2.

(13) More specifically, the third nitride compound semiconductor layer 3 essentially grows in crystal directions that do not correspond to the [0001] crystal direction. Growing the third nitride compound semiconductor layer 3 produces three-dimensional non-planar structures which may in particular be pyramidal. The side facets 3a of the pyramidal structures are in particular constituted by a [1-101] crystal face or a [11-22] crystal face.

(14) Growth of the third nitride compound semiconductor layer 3 is preferably stopped once the growing three-dimensional structures have completely coalesced to yield pyramidal structures of a desired height. Growth may be monitored in situ in the coating installation by means of reflectometry, for example. For this purpose, a laser beam is, for example, directed onto the growth surface at a normal incident angle, i.e., parallel to the direction of growth, and the reflectivity of the surface is then determined from the reflected intensity measured with a detector. Reflectivity decreases as the pyramidal structures increase in size. Calibration of the reflectivity of the surface thus provides information on the size of the pyramidal structures. Advantageously, pyramidal structures are produced having a height of between 1 m and 5 m, preferably of between 2 m and 3 m.

(15) In the additional method step illustrated in FIG. 5, a fourth nitride compound semiconductor layer 4 has been grown onto the non-planar structures of the third nitride compound semiconductor layer 3. For growing the fourth nitride compound semiconductor layer 4, growth conditions are changed again. Same as when growing the second nitride compound semiconductor layer 2, growth conditions are set so as to yield essentially two-dimensional growth. This allows the pyramidal structures to be overgrown in such a way that an essentially planar surface is obtained. It has turned out that defects kink at the boundary surfaces of the non-planar structures, in particular at the [1-101] crystal faces or the [11-22] crystal faces which are inclined relative to the growth substrate. The defect density in the fourth nitride compound semiconductor layer 4 is thus particularly low. In particular, changing the growth conditions twice from essentially two-dimensional growth to essentially three-dimensional growth and vice versa allows a particularly low defect density to be achieved in the nitride compound semiconductor material of the fourth nitride compound semiconductor layer 4.

(16) The growth conditions when growing the fourth nitride compound semiconductor layer 4 may in particular be identical to the growth conditions for growing the second nitride compound semiconductor layer 2. In particular when growing the fourth nitride compound semiconductor layer 4, the growth temperature is increased relative to the growth temperature of the third nitride compound semiconductor layer 3, preferably by 50 C. to 80 C. For example, the growth temperature is raised by approx. 75 C. When growing the fourth nitride compound semiconductor layer 4, the NH.sub.3 gas flow can be increased as well. Preferably, the NH.sub.3 gas flow when growing the second and third nitride compound semiconductor layers 2, 3 is between approx. 10% and 30% of the value present when the fourth nitride compound semiconductor layer 4 is grown. When growing the second nitride compound semiconductor layer 2 and the third nitride compound semiconductor layer 3, the NH.sub.3 gas flow can be approx. 10 slm and when growing the fourth nitride compound semiconductor layer 4 the NH.sub.3 gas flow can be approx. 50 slm. However, it is also possible to keep the NH.sub.3 gas flow constant and to only raise the growth temperature when growing the fourth nitride compound semiconductor layer 4.

(17) In the subsequent method step which is illustrated in FIG. 6, the essentially planar surface of the fourth nitride compound semiconductor layer 4 is then used for growing a functional semiconductor layer sequence 8 thereonto. The quality of the functional semiconductor layer sequence 8 benefits in particular from low defect density in the fourth nitride compound semiconductor layer 4 onto which it is grown. In particular, the functional semiconductor layer sequence 8 is characterized by very low defect density which is achieved in particular by changing the growth conditions of the subjacent nitride compound semiconductor layers 2, 3, 4 twice.

(18) The functional semiconductor layer sequence 8 may in particular be a light-emitting semiconductor layer sequence of an optoelectronic device. For example, the nitride compound semiconductor device is an LED and the functional semiconductor layer sequence 8 is a light-emitting diode layer sequence. In particular, the functional semiconductor layer sequence 8 can have an n-type semiconductor region 5, an active layer 6 and a p-type semiconductor region 7. The light-emitting diode layer sequence only shown in simplified form can be composed of a plurality of single layers, and because such layer sequences are per se known, they shall not be discussed in more detail here.

(19) Furthermore, in the intermediate step shown in FIG. 6, on its side opposite the growth substrate 10, the functional semiconductor layer sequence 8 has been connected to a carrier 13. The carrier 13 may in particular be a silicon wafer. The carrier 13 can be connected to the functional semiconductor layer sequence 8 by means of a connection layer 12 such as a solder layer. Advantageously, the functional semiconductor layer sequence 8 is provided with a mirror layer 9 before it is connected to the carrier 13, which mirror layer 9 serves to reflect the radiation emitted in the direction of the carrier 13 in the finished nitride compound semiconductor device toward the opposite radiation exit surface and to thus increase the radiation yield. The mirror layer 9 may comprise silver or aluminum, for example. Furthermore, the functional semiconductor layer can be provided with electrical contacts (not shown). An electrical contact can be constituted by an electrically conductive mirror layer 9, for example. Furthermore it is possible to provide vias for electrical contacting which extend into the n-type semiconductor region 7. Such options for electrical contacting are per se known and thus not illustrated in detail in the Figures.

(20) In the method step shown in FIG. 7, the growth substrate 10 has been removed from the layer sequence produced. The growth substrate 10 may, for example, be removed from the layer sequence using a laser lift-off process. As an alternative, the growth substrate 10 may be removed using ultrasound, a wet chemical process, by generating shearing forces, in particular through a temperature treatment, or through the application of purely mechanical force.

(21) Furthermore, an etching process has been conducted which was used to at least partially remove the first nitride compound semiconductor layer 1, the masking layer 11, the second nitride compound semiconductor layer 2 and the third nitride compound semiconductor layer 3. The etching process is preferably conducted in a wet chemical manner, using KOH as the etchant. The etching process is used to produce coupling-out structures 14 on the surface of the device which is located opposite the carrier 13, which surface may in particular be the radiation exit area.

(22) It has turned out that the etching process stops especially at the boundary surfaces on which the side facets of the pyramidal structures had previously been formed. Ending at the side facets are vertically extending dislocations through which the etchant preferably penetrates the semiconductor materialwhich slows down or even stops the etching process at the side facets. The side facets of the pyramidal structures therefore act as an etch stop layer.

(23) At least part of the side facets 14a of the coupling-out structures 14 can therefore be constituted by a [1-101] crystal face or an [11-22] crystal face. The coupling-out structures 14 are advantageously three-dimensional structures which are at least partially inverse to the non-planar three-dimensional structures produced when growing the third nitride compound semiconductor layer 3.

(24) The size and shape of the coupling-out structures 14 can therefore be influenced in particular by the growth period and the growth conditions during the production of the third nitride compound semiconductor layer 3. Furthermore, the spatial distribution and size of the coupling-out structures can be influenced in a targeted manner by the previously deposited masking layer 11. Depending on the size of the coupling-out structures 14, this not only improves radiation coupling-out but also allows the spatial radiation characteristics to be specifically influenced, if necessary. Consequently, the spatial angle can be used to influence radiation characteristics, and thus the far field of the optoelectronic device, while the epitaxy process is still ongoing.

(25) The coupling-out structures 14 may also comprise further recesses in the fourth nitride compound semiconductor layer 4 which do not match the inverse pyramidal structures of the third nitride compound semiconductor layer 3. These recesses are illustrated in FIG. 7 in the form of the small pyramids next to and between the large pyramids and are produced in the etching process based on the previously planar regions of the surface of the fourth nitride compound semiconductor layer 4. In this case, the etching process stops in particular at dislocations which are still present and which are parallel to the crystallographic c-plane. Vertically extending dislocations, through which the etchant preferably penetrates the semiconductor material, usually end at these transversely extending dislocations. Consequently, also dislocations which extend parallel to the c-plane have an effect similar to an etch stop layer.

(26) The invention is not restricted by the description given with reference to the exemplary embodiments. Rather, the invention encompasses any novel feature and any combination of features, in particular any combination of features in the claims, even if this feature or this combination is not itself explicitly indicated in the claims or exemplary embodiments.