Method for fabricating a semiconductor package

Abstract

A method for fabricating a semiconductor package is provided. Semiconductor dice are disposed on a top surface of a carrier. Each of the semiconductor dice has an active surface and a bottom surface that is opposite to the active surface. Input/output (I/O) pads are distributed on the active surface. Interconnect features are printed on the carrier and on the active surface of each of the semiconductor dice. The top surface of the carrier, the semiconductor dice and the interconnect features is encapsulated with an encapsulant. The carrier is then removed.

Claims

1. A method for fabricating a semiconductor package, comprising: providing a carrier; adhering semiconductor dice to a top surface of the carrier by an adhesive that is in direct physical contact with the top surface of the carrier, wherein each of the semiconductor dice has an active surface and a bottom surface that is opposite to the active surface, and wherein a plurality of input/output (I/O) pads are distributed on the active surface of each of the semiconductor dice; printing interconnect features, the printing comprising: printing a first conductive pad on the carrier; printing a second conductive pad on the active surface of at least one of the semiconductor dice; and printing a conductive wire connecting the first and second conductive pads, wherein the interconnect features comprise the first conductive pad, the second conductive pad and the conductive wire; encapsulating the top surface of the carrier, the semiconductor dice and the interconnect features with an encapsulant; and removing the carrier.

2. The method for fabricating a semiconductor package according to claim 1, wherein the carrier comprises glass, silicon, or metal.

3. The method for fabricating a semiconductor package according to claim 1, wherein the conductive wire is integrally formed with the first and second conductive pads.

4. The method for fabricating a semiconductor package according to claim 1, wherein the interconnect features are composed of silver, gold, copper, carbon nanotube, graphene, or nano metal particles.

5. The method for fabricating a semiconductor package according to claim 1, wherein the conductive wire and the first and second conductive pads are formed by using a 3D printer or a wire bonding tool having a 3D printing function.

6. The method for fabricating a semiconductor package according to claim 1, wherein after the formation of the interconnect features, a dicing process is performed to singulate individual semiconductor packages from one another.

7. The method for fabricating a semiconductor package according to claim 1, wherein a passive device is disposed on the carrier.

8. The method for fabricating a semiconductor package according to claim 7, wherein the passive device comprises a discrete capacitor device, a resistor device or an inductor device.

9. The method for fabricating a semiconductor package according to claim 1 further comprising: performing a curing process or a drying process to cure the interconnect features and remove solvent from the interconnect features.

10. The method for fabricating a semiconductor package according to claim 1, wherein the conductive wire comprises an integral portion with different patterns, diameters, or structural features formed along its lengthwise direction.

11. The method for fabricating a semiconductor package according to claim 1, wherein the conductive wire comprises a widened portion, wherein the widened portion comprises a pad, a plate or a grid.

12. The method for fabricating a semiconductor package according to claim 1 further comprising: after removing the carrier, forming a connecting element directly on the first conductive pad for further connection.

13. The method for fabricating a semiconductor package according to claim 12, wherein the connecting element comprises a conductive bump or a conductive ball.

14. A method for fabricating a semiconductor package, comprising: providing a carrier; arranging a semiconductor die on a top surface of the carrier; printing temporary interconnect features on the top surface of the carrier and on an active surface of the semiconductor die; encapsulating the top surface of the carrier, the active surface of the semiconductor die and the temporary interconnect features with an encapsulant; removing the carrier; removing the temporary interconnect features thereby forming cavity in the encapsulant; and filling the cavity with conductive material to form interconnect features.

15. The method for fabricating a semiconductor package according to claim 14, wherein the temporary interconnect features comprises a conductive pad and a conductive wire, and wherein the conductive wire is integrally formed with the conductive pad.

16. The method for fabricating a semiconductor package according to claim 15, wherein a passive device is disposed on the carrier.

17. The method for fabricating a semiconductor package according to claim 16, wherein one terminal of the passive device is electrically connected to the conductive wire.

18. The method for fabricating a semiconductor package according to claim 14, wherein the temporary interconnect features are composed of a non-conductive material or an ashable material.

19. The method for fabricating a semiconductor package according to claim 14, wherein the interconnect features are composed of silver, gold, copper, carbon nanotube, graphene, nano metal particles, or solder.

20. The method for fabricating a semiconductor package according to claim 1, wherein the printing of the first conductive pad is performed after adhering the semiconductor dice to the top surface of the carrier.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings:

(2) FIG. 1 is a schematic, cross-sectional diagram showing a conventional stacked multichip package;

(3) FIG. 2 is a schematic, cross-sectional diagram showing an exemplary semiconductor package in accordance with one embodiment of the invention;

(4) FIG. 3 is a schematic, cross-sectional diagram showing an exemplary package-on-package (PoP) in accordance with another embodiment of the invention;

(5) FIG. 4 is a schematic, cross-sectional diagram showing an exemplary multi-die package in accordance with still another embodiment of the invention;

(6) FIG. 5 to FIG. 9 are schematic, cross-sectional diagrams showing an exemplary method for fabricating the semiconductor package as set forth in FIG. 2 according to one embodiment of the invention;

(7) FIG. 10 to FIG. 12 are schematic, cross-sectional diagrams showing an exemplary method for fabricating the semiconductor package as set forth in FIG. 2 according to another embodiment of the invention; and

(8) FIG. 13 is a schematic perspective diagram showing an exemplary semiconductor package in accordance with still another embodiment of the invention.

DETAILED DESCRIPTION

(9) In the following detailed description of embodiments of the invention, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific preferred embodiments in which the disclosure may be practiced.

(10) These embodiments are described in sufficient detail to enable those skilled in the art to practice them, and it is to be understood that other embodiments may be utilized and that mechanical, chemical, electrical, and procedural changes may be made without departing from the spirit and scope of the present disclosure. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of embodiments of the present invention is defined only by the appended claims.

(11) Please refer to FIG. 2. FIG. 2 is a schematic, cross-sectional diagram showing an exemplary semiconductor package in accordance with one embodiment of the invention. As shown in FIG. 2, semiconductor package 1 comprises a semiconductor die 110. The semiconductor die 110 has a top surface or active surface 110a and a bottom surface 110b that is opposite to the active surface 110a. A plurality of bond pads or input/output (I/O) pads 121 are distributed on the active surface 110a. According to the embodiment of the invention, the active surface 110a, the I/O pads 121, and four side surfaces between the active surface 110a and the bottom surface 110b are covered with an encapsulant 200 such as a molding compound.

(12) In some embodiments, the encapsulant 200 may be formed of an epoxy, a resin, a moldable polymer, or the like. The encapsulant 200 may be applied while substantially liquid, and then may be cured through a chemical reaction, such as in an epoxy or resin. In some other embodiments, the molding compound may be an ultraviolet (UV) or thermally cured polymer applied as a gel or malleable solid capable of being disposed around the semiconductor die 110, and then may be cured through a UV or thermal curing process. The encapsulant 200 may be cured with a mold (not shown).

(13) According to the embodiment of the invention, the bottom surface 110b is exposed from a bottom surface 200b of the encapsulant 200. The encapsulant 200 has a top surface 200a that is opposite to the bottom surface 200b. According to the embodiment of the invention, the exposed bottom surface 110b of the semiconductor die 110 is flush with the bottom surface 200b of the encapsulant 200. According to the embodiment of the invention, no re-distribution layer (RDL) is required on the active surface 110a of the semiconductor die 110.

(14) For the sake of simplicity, the structural details within the semiconductor die 110 are not shown in this figure. It is understood that the semiconductor die 110 may comprise a semiconductor substrate such as a silicon substrate. On the main surface of the semiconductor substrate, a plurality of circuit elements such as transistors may be formed. A plurality of inter-layer dielectric (ILD) layers may be deposited on the semiconductor substrate. The ILD layer may be formed of organic materials, which include a polymer base material, non-organic materials, which include silicon nitride (SiN.sub.x), silicon oxide (SiO.sub.x), graphene, or the like. A plurality of metal interconnection layers may be formed within the ILD layers. The I/O pads 121 of the semiconductor die 110 may be formed in the topmost metal layer covered with a passivation layer, but not limited thereto.

(15) A plurality of conductive pads 216 and 218 are distributed on the bottom surface 200b of the encapsulant 200. The conductive pads 216 and 218 are arranged around the semiconductor die 110 and are electrically connected to the I/O pads 121 on the active surface 110a through the conductive wires 116 and 118 respectively. A plurality of connecting elements 230 such as conductive bumps (e.g. C4 bumps or copper pillars) or conductive balls (e.g. BGA balls) may be formed on the conductive pads 216 and 218 for further connection.

(16) It is one germane feature of the embodiment of the invention that the conductive wires 116 and 118 are integrally formed with the conductive pads 216 and 218. According to the embodiment of the invention, for example, the conductive wires 116 and 118 and the conductive pads 216 and 218 may be formed by using a three-dimensional (3D) printer or a wire bonding tool having 3D printing function. The conductive wires 116 and 118 and the conductive pads 216 and 218 are encapsulated by the encapsulant 200. According to the embodiment of the invention, no packaging substrate or interposer is required. Further, since the conductive wires 116 and 118 are formed by using a 3D printer or a wire bonding tool having 3D printing function, the conductive wires 116 and 118 may comprise a portion that is bent at right angles, which may avoid shorting of the adjacent wires.

(17) According to the embodiment of the invention, the semiconductor package 1 may further comprise a passive device 210 such as a discrete capacitor device, a resistor device, an inductor device, or the like. The passive device 210 may be disposed adjacent to the bottom surface 200b of the encapsulant 200. According to the embodiment of the invention, the passive device 210 may have two terminals 210a and 210b that are electrically connected to the conductive wire 116a and the conductive wire 118a, respectively.

(18) According to the embodiment of the invention, the conductive wire 116a and the conductive wire 118a are integrally formed with the conductive wires 116 and 118, respectively. Therefore, the terminal 210a is electrically connected to the conductive pad 216 and the semiconductor die 110 through the integral conductive wires 116 and 116a, and the terminal 210b is electrically connected to the conductive pad 218 and the semiconductor die 110 through the integral conductive wires 118 and 118a.

(19) According to the embodiment of the invention, the conductive wire 116 or 118 may have an integral portion with different patterns, diameters, or structural features formed along the lengthwise direction of the conductive wire 116 or 118. For example, FIG. 2 illustrates that the conductive wire 118 may have a widened portion 118b, which is disposed adjacent to the top surface 200a of the encapsulant 200. The widened portion 118b may comprise a pad, a plate, a grid, but not limited thereto.

(20) Please refer to FIG. 3. FIG. 3 is a schematic, cross-sectional diagram showing an exemplary semiconductor package in accordance with another embodiment of the invention, wherein like numeral numbers designate like regions, layers, or elements. As shown in FIG. 3, the semiconductor package 2 may be a package-on-package (PoP). The semiconductor package 2 comprises a bottom die package 100 having the structural features as described in FIG. 2. The bottom die package 100 is different from the semiconductor package 1 of FIG. 2 in that openings 260 such as laser-drilled openings are formed in the top surface 200a of the encapsulant 200.

(21) Each of the openings 260 may expose a portion of the integral portion 118b, which in this embodiment may function as an integral bond pad. Conductive elements 320 including, but not limited to, under bump metals and bumps are formed within the openings 260 and on the exposed integral portion 118b. A top die package 300 comprising a molded integrated circuit die 310 is mounted on the conductive elements 320.

(22) Please refer to FIG. 4. FIG. 4 is a schematic, cross-sectional diagram showing an exemplary semiconductor package in accordance with still another embodiment of the invention, wherein like numeral numbers designate like regions, layers, or elements. As shown in FIG. 4, the semiconductor package 3 may be a multi-die package. The semiconductor package 3 may comprise a lower semiconductor die 110 and an upper semiconductor die 410 that is directly stacked on the lower semiconductor die 110. The upper semiconductor die 410 may be adhesively secured to the top surface of the lower semiconductor die 110. A plurality of bond pads or I/O pads 121 are distributed on an active surface 110a of the lower semiconductor die 110 and a plurality of bond pads or I/O pads 421 are distributed on an active surface 410a of the upper semiconductor die 410.

(23) According to the embodiment of the invention, the upper semiconductor die 410 partially overlaps with the lower semiconductor die 110 when viewed from the above. Therefore, the upper semiconductor die 410 comprises an overhanging side edge 412. The overhanging side edge 412 and a bottom surface 410b beyond an edge of the lower semiconductor die 110 are encapsulated by the encapsulant 200.

(24) Likewise, a plurality of conductive pads 216 and 218 may be distributed on the bottom surface 200b of the encapsulant 200. The conductive pads 216 and 218 may be arranged in an array around the semiconductor die 110 and may be electrically connected to the I/O pads 121 on the active surface 110a and I/O pads 421 on the active surface 410a through the conductive wires 116 and 118 respectively.

(25) A plurality of connecting elements 230 such as conductive bumps (e.g. C4 bumps or copper pillars) or conductive balls (e.g. BGA balls) may be formed on the conductive pads 216 and 218 for further connection. According to the embodiment of the invention, at least an I/O pad 421 is interconnected to at least an I/O pad 121 through the conductive wire 118 and a branched conductive wire 118a, for example, which is integrally formed with the conductive wire 118.

(26) FIG. 5 to FIG. 9 are schematic, cross-sectional diagrams showing an exemplary method for fabricating the semiconductor package 1 as set forth in FIG. 2 according to one embodiment of the invention. As shown in FIG. 5, first, a carrier 500 may be provided. The carrier 500 may comprise glass, silicon, metal, or any suitable materials. A plurality of semiconductor dice 110 is disposed on the carrier 500. Each of the semiconductor dice 110 has a top surface or active surface 110a and a bottom surface 110b that is opposite to the active surface 110a. A plurality of bond pads or I/O pads 121 are distributed on the active surface 110a.

(27) The semiconductor dice 110 may be adhesively secured to the top surface of the carrier 500. Optionally, passive devices 210, such as a discrete capacitor device, a resistor device, an inductor device, or the like, may also be disposed on the carrier 500.

(28) As shown in FIG. 6, interconnect features 510 including, but not limited to, conductive pads 216 and 218 and conductive wires 116 and 118, are formed on the carrier 500 and on the top surfaces 110a of the semiconductor dice 110. The conductive wires 116 and 118 are integrally formed with the conductive pads 216 and 218, respectively. The passive device 210 may have two terminals 210a and 210b that are electrically connected to the conductive wire 116a and the conductive wire 118a, respectively.

(29) For example, the conductive wires 116 and 118 and the conductive pads 216 and 218 may be formed by using a 3D printer or a wire bonding tool having 3D printing function. For example, the interconnect features 510 may be composed of silver, gold, copper, carbon nanotube, graphene, or nano metal particles, but not limited thereto. After the formation of the interconnect features 510, optionally, a curing process or a drying process may be performed to cure the interconnect features 510 and/or remove solvent from the interconnect features 510.

(30) According to the embodiment of the invention, for example, the conductive wire 118 may have an integral portion with different patterns, diameters, or structural features formed along its lengthwise direction. For example, the conductive wire 118 may have a widened portion 118b. The widened portion 118b may comprise a pad, a plate, a grid, but not limited thereto. It is understood that other features, for example, a heat pipe (not shown), may also be printed on the carrier 500 at this stage.

(31) As shown in FIG. 7, subsequently, the top surface of the carrier 500, the top surfaces 110a of the semiconductor dice 110, the conductive wires 116 and 118, and the conductive pads 216 and 218 are encapsulated by the encapsulant 200. For example, the encapsulant 200 may comprise a molding compound including, but not limited to, an epoxy or resin.

(32) As shown in FIG. 8, the carrier 500 is then removed to expose the bottom surface 200b of the encapsulant 200, the bottom surfaces 110b of the semiconductor dice 110, and the conductive pads 216 and 218. A plurality of connecting elements 230 such as conductive bumps (e.g. C4 bumps or copper pillars) or conductive balls (e.g. BGA balls) may be formed on the conductive pads 216 and 218 for further connection. Although not shown in this figure, it is understood that a passivation layer may be formed on the bottom surface 200b of the encapsulant 200 and bottom surfaces 110b of the semiconductor dice 110.

(33) As shown in FIG. 9, after the formation of the connecting elements 230, a dicing process is performed to singulate individual semiconductor packages 1 from one another. During the aforesaid dicing process, a dicing tape (not shown) may be used to provide temporary support.

(34) FIG. 10 to FIG. 12 are schematic, cross-sectional diagrams showing an exemplary method for fabricating the semiconductor package 1 according to another embodiment of the invention, wherein like numeral numbers designate like regions, layers, or elements.

(35) As shown in FIG. 10, after mounting the semiconductor die 110 and the passive device 210 on the carrier 500, a temporary interconnect features 510 may be formed by using a 3D printer. According to the embodiment of the invention, the temporary interconnect features 510 may be composed of a non-conductive material or an ashable material. For the sake of simplicity, only one semiconductor die 110 on the carrier 500 is shown.

(36) Subsequently, the top surface of the carrier 500, the top surface 110a of the semiconductor die 110, and the temporary interconnect features 510 are encapsulated by the encapsulant 200. For example, the encapsulant 200 may comprise an epoxy molding compound.

(37) As shown in FIG. 11, the carrier 500 is then removed to expose the bottom surface 200b of the encapsulant 200, the bottom surfaces 110b of the semiconductor dice 110, and a portion of the temporary interconnect features 510. Subsequently, the temporary interconnect features 510 is completely removed, thereby forming cavity 530 within the encapsulant 200.

(38) As shown in FIG. 12, the cavity 530 is then filled up with conductive material to form interconnect features 510 including, but not limited to, conductive pads 216 and 218 and conductive wires 116 and 118. The conductive wires 116 and 118 are integrally formed with the conductive pads 216 and 218. The passive device 210 may have two terminals 210a and 210b that are electrically connected to the conductive wire 116a and the conductive wire 118a, respectively.

(39) For example, the interconnect features 510 may be composed of silver, gold, copper, carbonnanotube, graphene, nano metal particles, or solder, but not limited thereto. After the formation of the interconnect features 510, optionally, a curing process, a reflow process, or a drying process may be performed.

(40) FIG. 13 is a schematic perspective diagram showing an exemplary semiconductor package in accordance with still another embodiment of the invention, wherein like numeral numbers designate like regions, layers, or elements. As shown in FIG. 13, the semiconductor package 4 may be a multi-die package. The semiconductor package 4 may comprise a substrate 101 having a top surface 101a and a bottom surface 101b that is opposite to the top surface 101a. The substrate 101 may comprise a packaging substrate or a printed wiring board, but not limited thereto. A plurality of bond fingers 102 may be arranged on the top surface 101a of the substrate 101 along its perimeter. On the bottom surface 101b, a plurality of solder balls 103 may be arranged.

(41) The semiconductor package 4 may comprise a lower semiconductor die 110 and an upper semiconductor die 410 that is directly stacked on the lower semiconductor die 110. The upper semiconductor die 410 may be adhesively secured to the top surface 110a of the lower semiconductor die 110. A plurality of bond pads or I/O pads 121 are distributed on an active surface 110a of the lower semiconductor die 110 and a plurality of bond pads or I/O pads 421 are distributed on an active surface 410a of the upper semiconductor die 410. According to the embodiment of the invention, the upper semiconductor die 410 partially overlaps with the lower semiconductor die 110 when viewed from the above. Therefore, the upper semiconductor die 410 comprises an overhanging side edge 412. The overhanging side edge 412 and a bottom surface 410b beyond an edge of the lower semiconductor die 110 may be encapsulated by the encapsulant (not shown).

(42) According to the embodiment of the invention, 3D printed features 600 including, but not limited to, conductive wires 610, PMU (power management unit) heatpipe 620, inductor 630, and power bar 640, may be formed on the top surface 410a of the upper semiconductor die 410 and on the top surface 110a of the lower semiconductor die 110. According to the embodiment of the invention, the conductive wires 610 may interconnect the bond pads 421, the bond pads 121, and/or the bond fingers 102. For example, one conductive wire 610 may be electrically connected to multiple bond fingers 102 through the sub-wires 610a that is formed integrally with the conductive wire 610.

(43) Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.