PARALLEL-CONNECTED MERGED-FLOATING-GATE NFET-PFET EEPROM CELL AND ARRAY

Abstract

A shared floating gate device, the device including an. nFET, a pFET including a different material than that of the nFET, and a floating gate.

Claims

1. A device, comprising; an nFET; a pFET ; and a floating gate, wherein the nFET and the pFET share floating gate.

2. The device of claim 1, wherein the nFET and the pFET share the floating gate to form an electrically erasable and programmable non-volatile memory device.

3. The device of claim 1, wherein the nFET includes an nFET gate dielectric, wherein the pFET includes a pFET gate dielectric, and wherein the pFET gate dielectric and the nFET dielectric comprise different materials.

4. The device of claim 3, wherein the different materials are selected so that a difference of energy barriers for a hot-carrier injection formed by the nFET gate dielectric and the pFET gate dielectric is 1 eV or less.

5. The device of claim 1, wherein the nFET comprises one of: Y.sub.2O.sub.3; ZrO.sub.2; and HfO.sub.02.

6. The device of claim 1, wherein the pFET comprises one of: Si.sub.3N.sub.4; Y.sub.2O.sub.3; ZrO.sub.2; and HfO.sub.2.

7. An electrically erasable programmable read-only memory (EEPROM) cell, the cell comprising: an nFET; a pFET; and a floating gate, wherein the NFET and the pFET share the floating gate.

8. The cell of claim 7, wherein the nFET and the pFET share the floating gate to form an electrically programmable and erasable non-volatile memory device.

9. The cell of claim 7, wherein the nFET includes an nFET gate dielectric, wherein the pFET includes a pFET gate dielectric, and wherein the pFET gate dielectric and the nFET dielectric comprise different materials.

10. The cell of claim 9, wherein the different materials are selected so that a difference of energy barriers for a hot-carrier injection formed by the nFET gate dielectric and pFET gate dielectric is 1 eV or less.

11. The cell of claim 7, wherein the nFET comprises one of: Y.sub.2O.sub.3; ZrO.sub.2; and HfO.sub.2.

12. The cell of claim 7, wherein the pFET comprises one of: Si.sub.3N.sub.4; Y.sub.2O.sub.3; ZrO.sub.2; and HfO.sub.2.

13. An array structure, comprising: a plurality of cells, each cell including: an nFET; a pFET; a floating gate; and an nFET access transistor including a drain connected to a source of the nFET and a drain of the pFET.

14. The array structure of claim 13, further comprising one nFET access transistor per word-line.

15. The array structure f claim 13, further comprising one bit-line per pFET access transistor.

16. The array structure of claim 13, further comprising a word-line and two bit-lines per each cell, said word-line being connected to the gate of the access transistor, one of said bit-lines being connected to the source of the pFET and the other one of said bit-lines being connected to the drain of nFET.

17. The array structure of claim 13, further comprising peripheral logic circuits, wherein the plurality of cells and the peripheral logic circuits are built on a same substrate.

18. The array structure of claim 13, further comprising peripheral logic circuits, wherein the plurality of cells is built on a polycrystalline silicon film-on-insulator and the peripheral logic circuits are built on a bulk silicon substrate.

19. The array structure of claim 13, further comprising peripheral logic circuits, wherein the plurality of cells and the peripheral logic circuits are built on a same bulk silicon substrate.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Aspects of the invention will be better understood from the following detailed description of the exemplary embodiments of the invention with reference to the drawings, in which:

[0026] FIG. 1 exemplarily shows a parallel-connected merged-floating-gate nFET-pFET EEPROM cell 100 according to an embodiment of the present invention;

[0027] FIG. 2 exemplarily shows an EEPROM array 200 including the cell 100 with one access transistor per wordline according to an embodiment of the present invention;

[0028] FIG. 3 exemplarily shows an EEPROM array operation of the array 200 with cell (0, 0) using exemplary TABLES 1-2;

[0029] FIG. 4A-4B exemplarily depict experimental data with different dielectric/oxide materials; and

[0030] FIG. 5A-5E exemplarily depict a method of manufacture of the parallel-connected merged-floating-gate nFET-pFET EEPROM cell 100.

DETAILED DESCRIPTION

[0031] The invention will now be described with reference to FIGS. 1-5E, in which like reference numerals refer to like parts throughout. It is emphasized that, according to common practice, the various features of the drawings are not necessarily to scale. On the contrary, the dimensions of the various features can be arbitrarily expanded or reduced for clarity.

[0032] By way of introduction of the exemplarily parallel-connected merged-floating-gate nFET-pFET EEPROM cell 100 depicted in FIG. 1 and the top view thereof, the cell 100 includes a pFET with a reduced energy barrier for hot-electron injection 101, a pFET terminal 102, a common floating gate 103, an nFET terminal 104, an nFET with reduced energy barrier for hot-hole injection 105, a common node 106, and an access transistor (i.e., nFET) 107. The drain of pFET 102, the source of pFET 104, and the drain of access transistor 107 are connected together to form the common node 106.

[0033] That is, FIG. 1 exemplarily depicts a shared floating gate device including an nFET 104 with an nFET gate dielectric and a pFET 102 with a pFET gate dielectric where the nFET 104 and pFET 102 are connected in parallel and share a common gate 103 which is floating, to form an electrically programmable and erasable non-volatile memory device, Thus, the common floating gate (i.e., made of electrically conducting material) is sandwiched between the nFET and the pFET. The nFET gate dielectric and the pFET dielectric are made of different materials selected so that the difference of the energy barriers for hot-carrier injection formed by the nFET and pFET dielectric is 1 eV or less.

[0034] Moroever, the nFET gate dielectric can include, for example, Y.sub.2O.sub.3, ZrO.sub.2, HfO.sub.2, or the like. The pFET gate dielectric can include, for example, Si.sub.3N.sub.4, Y.sub.2O.sub.3, ZrO.sub.2, HfO.sub.2, or the like.