PHASE-LOCKED LOOP CIRCUIT, CORRESPONDING RADAR SENSOR, VEHICLE AND METHOD OF OPERATION

Abstract

A circuit includes a phase-frequency-detector generating first and second digital control signals indicative of phase differences between an input reference-signal and an output-signal, a charge-pump generating a control-signal based upon the first and second digital control signals, and an oscillator-circuit. The oscillator-circuit includes an active core coupled between first and second nodes, with a tunable resonant circuit a set of capacitances selectively connected between the first and second nodes, wherein a tap between the first and second variable capacitances receives the control-signal for tuning the tunable resonant circuit. A timer-circuit generates a timing-signal based upon the input reference-signal and a reset-signal. A calibration-circuit controls which capacitances of the set of capacitances are connected between the first and second nodes, in response to the timing-signal and a comparison between a threshold and a voltage-signal that is based upon auxiliary pulsed currents generated based upon the first and second digital control signals.

Claims

1. A circuit, comprising: a phase-frequency detector configured to generate first and second digital control signals indicative of phase differences between an input reference signal and an output signal; a charge pump configured generate a control signal based upon the first and second digital control signals; an oscillator circuit comprising: an active core coupled between first and second nodes; and a tunable resonant circuit comprising an inductance coupled between the first and second nodes, first and second variable capacitances coupled between the first and second nodes, and a set of capacitances selectively connected between the first and second nodes, wherein a tap between the first and second variable capacitances receives the control signal for tuning the tunable resonant circuit; a timer circuit configured to generate a timing signal based upon the input reference signal and a reset signal; and a calibration circuit configured to control which capacitances of the set of capacitances are connected between the first and second nodes, in response to the timing signal and a comparison between a threshold and a voltage signal, the voltage signal being based upon auxiliary pulsed currents generated based upon the first and second digital control signals.

2. The circuit of claim 1, wherein the timer circuit comprises an OR gate configured to generate the timing signal, the OR gate having a first input receiving the reset signal and a second input receiving a clock signal from a frequency divider circuit.

3. The circuit of claim 2, wherein the frequency divider circuit has a first input receiving the input reference signal and the reset signal, and has an output connected to the second input of the OR gate.

4. The circuit of claim 3, wherein the frequency divider circuit is configured to divide the input reference signal by a given factor to produce a clock signal that is provided to the second input of the OR gate.

5. The circuit of claim 4, wherein the frequency divider circuit has a reset input that receives the reset signal, providing for synchronization of operation of the timer circuit with performance of a calibration phase.

6. The circuit of claim 5, wherein the timer circuit further comprises a counter circuit having a reset input coupled to receive the reset signal and a clock input coupled to receive the clock signal from the frequency divider circuit, the counter circuit defining a duration of the calibration phase based on a number of pulses of the clock signal counted.

7. The circuit of claim 6, wherein the counter circuit operates based upon a counter modulus which determines an output frequency of the counter circuit, thereby controlling the duration of the calibration phase.

8. The circuit of claim 1, wherein the calibration circuit includes an auxiliary charge pump circuit configured to provide the auxiliary pulsed currents to an integrator capacitance based on the first digital control signal and second digital control signal.

9. The circuit of claim 8, wherein the calibration circuit further comprises a comparator circuit configured to compare a voltage across the integrator capacitance with the threshold, and to generate a comparator output signal that triggers the selective connection of the set of capacitances between the first and second nodes.

10. The circuit of claim 9, wherein the calibration circuit utilizes the comparator output signal to trigger a serial-in parallel-out (SIPO) register, which determines which capacitances of the set of capacitances are connected between the first and second nodes.

11. The circuit of claim 10, wherein the SIPO register is configured to generate a thermometer code in response to the comparator output signal, the thermometer code corresponding to the selective connection of the set of capacitances to achieve desired tuning of the tunable resonant circuit.

12. The circuit of claim 11, wherein each bit shift in the thermometer code generated by the SIPO register results in the coupling or decoupling of a given unit capacitor within the set of capacitances, thereby fine-tuning frequency of the oscillator circuit.

13. The circuit of claim 6, wherein the calibration circuit is further configured to dynamically adjust calibration during periods identified as dead times between chirp signals in a radar sensor application.

14. The circuit of claim 13, wherein the calibration circuit is configured to receive a reset signal marking beginning of a dead time and initiate the calibration phase in synchronization with the dead times.

15. A method, comprising: generating first and second digital control signals indicative of phase differences between an input reference signal and an output signal; generating a control signal based upon the first and second digital control signals; tuning a tunable resonant circuit based upon the control signal; generating a timing signal based upon the input reference signal and a reset signal; and controlling which capacitances of a set of capacitances are connected between first and second nodes of an oscillator circuit, in response to the timing signal and a comparison between a threshold and a voltage signal, the voltage signal being based upon auxiliary pulsed currents generated based upon the first and second digital control signals.

16. The method of claim 15, further comprising generating the timing signal base upon a logical OR between the reset signal and a clock signal generated by a frequency divider circuit.

17. The method of claim 16, further comprising generating the clock signal based upon the input reference signal and the reset signal.

18. The method of claim 17, wherein the clock signal is generated by dividing the input reference signal by a given factor.

19. The method of claim 18, further comprising defining a duration of a calibration period based upon a number of pulses of the clock signal counted.

20. The method of claim 19, wherein the counting of the clock signal is performed by a counter circuit operated based upon a counter modulus which determines an output frequency of the counter circuit, thereby controlling the duration of the calibration phase.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0043] One or more embodiments will now be described, by way of example only, with reference to the annexed figures, wherein:

[0044] FIG. 1, which was described in the foregoing, is a diagram exemplary of a possible time-frequency relationship of radar signals in a frequency-modulated continuous-wave (FMCW) radar system,

[0045] FIG. 2 is a circuit block diagram exemplary of a PLL circuit as possibly used in a radar sensor,

[0046] FIG. 3 is a circuit block diagram exemplary of a voltage-controlled oscillator circuit as possibly used in a PLL circuit,

[0047] FIGS. 4A and 4B are diagrams exemplary of possible time-frequency relationship of signals in one or more embodiments of the present description,

[0048] FIG. 5 is a circuit block diagram exemplary of a PLL circuit according to one or more embodiments of the present description,

[0049] FIG. 6 is a circuit block diagram exemplary of another PLL circuit according to one or more embodiments of the present description,

[0050] FIGS. 7A to 7E are diagrams exemplary of possible behavior of signals in one or more embodiments of the present description,

[0051] FIG. 8 is a circuit block diagram exemplary of possible implementation details of one or more embodiments of the present description, and

[0052] FIG. 9 is a circuit block diagram exemplary of a radar architecture in a vehicle according to one or more embodiments of the present description.

DETAILED DESCRIPTION

[0053] In the ensuing description, one or more specific details are illustrated, aimed at providing an in-depth understanding of examples of embodiments of this description. The embodiments may be obtained without one or more of the specific details, or with other methods, components, materials, etc. In other cases, certain structures, materials, or operations are not illustrated or described in detail so that certain aspects of embodiments will not be obscured.

[0054] Reference to an embodiment or one embodiment in the framework of the present description is intended to indicate that a particular configuration, structure, or characteristic described in relation to the embodiment is comprised in at least one embodiment. Hence, phrases such as in an embodiment or in one embodiment that may be present in one or more points of the present description do not necessarily refer to one and the same embodiment. Moreover, particular conformations, structures, or characteristics may be combined in any adequate way in one or more embodiments.

[0055] The headings/references used herein are provided merely for convenience and hence do not define the extent of protection or the scope of the embodiments.

[0056] For simplicity, throughout the figures annexed herein, like parts or elements are indicated with like references/numerals. For brevity, a corresponding description will not be repeated for each and every figure.

[0057] By way of introduction to the detailed description of exemplary embodiments, reference may first be made to FIG. 2.

[0058] FIG. 2 is a circuit block diagram exemplary of a PLL circuit 20 as possibly used in a radar sensor. For instance, the PLL circuit 20 may rely on a suitable calibration strategy.

[0059] The PLL circuit 20 may comprise: an input node 200 configured to receive an input reference signal f.sub.ref; a phase-frequency detector (PFD) circuit 202 having a first input configured to receive the input reference signal f.sub.ref; a charge pump (CP) circuit 204 coupled at the output of the phase-frequency detector circuit 202; a low-pass filter circuit 206 coupled at the output of the charge pump circuit 204 and configured to generate, at a respective output node 208, a control signal V.sub.C; a voltage-controlled oscillator (VCO) circuit 210 coupled at node 208 and controlled by the control signal V.sub.C, the voltage-controlled oscillator circuit 210 configured to generate at an output node 212 an output signal f.sub.O; and a feedback loop configured to provide the output signal f.sub.O at a second input of the phase-frequency detector circuit 202.

[0060] The feedback loop may optionally comprise a frequency divider circuit 214.

[0061] As exemplified in FIG. 2, the voltage-controlled oscillator circuit 210 may comprise an active core 216 (e.g., a biasing circuit) coupled to an LC resonant circuit 218.

[0062] The active core 216 may comprise a pair of transistors M1 and M2, e.g., metal-oxide semiconductor (MOS) field-effect transistors. As exemplified in FIG. 2, a first transistor M1 may have a source terminal coupled to a voltage reference node (e.g., ground GND) and a drain terminal coupled to a first terminal 219a of the LC resonant circuit 218, and a second transistor M2 may have a source terminal coupled to the voltage reference node GND and a drain terminal coupled to a second terminal 219b of the LC resonant circuit 218. The control (gate) terminal of the first transistor M1 may be coupled to the drain terminal of the second transistor M2, and the control (gate) terminal of the second transistor M2 may be coupled to the drain terminal of the first transistor M1.

[0063] As exemplified in FIG. 2, the LC resonant circuit 218 may comprise an inductive component and a capacitive component coupled between the first terminal 219a and the second terminal 219b.

[0064] As exemplified herein, the inductive component may comprise an inductor L and the capacitive component may comprise one or more (e.g., a pair of) variable capacitors or varactors C.sub.V, e.g., coupled in series between terminals 219a and 219b.

[0065] As exemplified herein, the control signal V.sub.C may be applied at a node 224 intermediate the two varactors C.sub.V.

[0066] As exemplified in FIG. 2, the LC resonant circuit 218 may further comprise an array (or bank) of capacitors 220 coupled in parallel to the varactor(s) C.sub.V. The array of capacitors 220 may be configured to receive a set of configuration signals from an analog-to-digital converter circuit 222. The analog-to-digital converter 222 may be coupled to node 208 to receive the control signal V.sub.C. For instance, the analog-to-digital converter 222 may comprise an N-bit ADC and the array of capacitors 220 may comprise 2.sup.N unit capacitors.

[0067] The configuration signals (e.g., an N-bit binary signal generated by the ADC 222) may be used to activate and de-activate a set of switches respectively coupled to the capacitors in the array of capacitors 220, so that the overall capacitance of the capacitive component of the LC resonant circuit 218 may be changed to tune the output frequency of the voltage-controlled oscillator 210.

[0068] In a PLL circuit 20 as exemplified in FIG. 2, the analog-to-digital converter 222 and the array of capacitors 220 may be used to perform an adjustment (e.g., a calibration) of the tuning curve of the LC resonant circuit 218 to compensate the effect of process, voltage and/or temperature variations. This calibration strategy may advantageously avoid the use of large varactors which may lead to high power consumption and high phase noise.

[0069] As exemplified in FIG. 3, which is a circuit block diagram exemplary of possible implementation details of a voltage-controlled oscillator circuit 210 for use in a PLL circuit 20, the analog-to-digital converter 222 may comprise a successive approximation analog-to-digital converter (SA-ADC) configured to calibrate the LC resonant circuit.

[0070] A successive approximation analog-to-digital converter may comprise a comparator circuit 300 having a first (e.g., non-inverting) input coupled to node 208 to receive the control signal V.sub.C and a second (e.g., inverting) input coupled to a node 302 to receive a reference voltage signal V.sub.R. For instance, the reference voltage signal V.sub.R may be equal to half of a supply voltage V.sub.CC of the PLL circuit 20 (i.e., V.sub.R=V.sub.CC/2). The successive approximation analog-to-digital converter may further comprise a successive approximation register (SAR) 304 configured to receive an output signal from the comparator circuit 300 and to provide the N-bit configuration signal to the array of capacitors 220.

[0071] As exemplified in FIG. 3, a first switch S.sub.FT may be arranged in the propagation path between the configuration node of the LC resonant circuit 218 (here, the node 224 intermediate the varactors C.sub.V) and the first input of the comparator circuit 300 (e.g., node 208), and a second switch S.sub.CT may be arranged in the propagation path between the configuration node of the LC resonant circuit 218 and the second input of the comparator circuit 300 (e.g., node 302).

[0072] Therefore, calibration and tuning of a voltage-controlled oscillator circuit 210 as exemplified in FIG. 3 may be performed in two steps to avoid instability.

[0073] In the calibration step, the first switch S.sub.FT is opened and the second switch S.sub.CT is closed. The varactor(s) C.sub.V provide a constant capacitance value (e.g., an average value) and the ADC converter 222 achieves calibration of the LC resonant circuit 218 by enabling a selected subset of the capacitors in the array of capacitors 220.

[0074] In the tuning step, the first switch S.sub.FT is closed and the second switch S.sub.CT is opened. The varactor(s) C.sub.V is connected to the control voltage V.sub.C and changes its capacitance value to provide a frequency tuning within the calibrated tuning curve.

[0075] The solution described above may not be satisfactory insofar as the calibration step may take a long time (e.g., N times the settling time of the PLL circuit), and as a result, calibration may be performed only at the start-up of the radar system.

[0076] One or more embodiments may thus aim at providing an improved calibration system for a PLL circuit to be used, for instance, in an automotive radar application.

[0077] In that respect, one or more embodiments may rely on a dynamic calibration performed during the dead time DT between subsequent chirp signals, as exemplified in FIGS. 4A and 4B.

[0078] FIG. 4A is a diagram exemplary of a possible time-frequency relationship of a radar transmission signal TX in one or more embodiments. As previously discussed, the transmission signal TX may comprise plural chirps (i.e., frequency sweeps between a lower frequency f.sub.min and an upper frequency f.sub.max) having a duration T.sub.m (e.g., around 10 ?s, 1 ?s=10.sup.?6 s). The duration of the dead time DT which separates subsequent chirps may be, for instance, around 2 ?s.

[0079] The duration of the dead time DT or inter-chirp idle time (which may comprise a calibration phase) may depend on the settling time of the PLL circuit. In other words, during a dead time the PLL circuit may stabilize by bringing the operating frequency of the LC resonant circuit from the maximum value f.sub.max to the minimum value f.sub.min, before starting a new frequency sweep (e.g., a new chirp).

[0080] FIG. 4B is a diagram exemplary of a possible time-frequency relationship of the output signal f.sub.O generated by the voltage-controlled oscillator during a dead time DT in one or more embodiments (it is noted that the time scales of FIG. 4A and FIG. 4B are thus not the same). As exemplified in FIG. 4B, the frequency of the output signal f.sub.O may be decreased from f.sub.max to f.sub.min in a quantized or staircase-like manner, e.g., by progressively (or sequentially) activating the capacitors in the array of capacitors 220.

[0081] FIG. 5 is a circuit block diagram exemplary of certain components of a PLL circuit 50 according to one or more embodiments, e.g., for use in a radar sensor.

[0082] In one or more embodiments, a PLL circuit 50 may comprise: an input node 500 configured to receive an input reference signal f.sub.ref (e.g., at a frequency of 100 MHz); a phase-frequency detector (PFD) circuit 502 having a first input configured to receive the input reference signal f.sub.ref, the phase-frequency detector circuit 502 being configured to generate (in an otherwise conventional manner) digital control signals UP and DOWN; a charge pump (CP) circuit 504 coupled at the output of the phase-frequency detector circuit 502 and configured to receive therefrom the digital control signals UP and DOWN; a low-pass filter circuit 506 coupled at the output of the charge pump circuit 504 and configured to generate, at a respective output node 508, a control signal V.sub.C; a voltage-controlled oscillator (VCO) circuit 510 coupled at node 508 and controlled by the control signal V.sub.C, the voltage-controlled oscillator circuit 510 configured to generate an output signal f.sub.O (e.g., between nodes 519a and 519b); and a feedback loop configured to provide the output signal f.sub.O at a second input of the phase-frequency detector circuit 502.

[0083] The feedback loop may optionally comprise a frequency divider circuit 514.

[0084] As exemplified in FIG. 5, the low-pass filter circuit 506 may comprise a filter capacitor CF coupled between node 508 and a reference voltage node GND.

[0085] As exemplified in FIG. 5, the voltage-controlled oscillator circuit 510 may comprise an active core 516 (e.g., a biasing circuit) coupled to an LC resonant circuit 518.

[0086] The active core 516 may comprise a pair of transistors M1 and M2, e.g., MOS field-effect transistors. As exemplified in FIG. 5, a first transistor M1 may have a source terminal coupled to the reference voltage node GND (e.g., ground) and a drain terminal coupled to the first terminal 519a of the LC resonant circuit 518, and a second transistor M2 may have a source terminal coupled to the reference voltage node GND and a drain terminal coupled to the second terminal 519b of the LC resonant circuit 518. The control (gate) terminal of the first transistor M1 may be coupled to the drain terminal of the second transistor M2, and the control (gate) terminal of the second transistor M2 may be coupled to the drain terminal of the first transistor M1.

[0087] As exemplified in FIG. 5, the LC resonant circuit 518 may comprise an inductive component and a capacitive component coupled between the first terminal 519a and the second terminal 519b of the LC resonant circuit 518.

[0088] As exemplified in FIG. 5, the inductive component may comprise one or more inductors L. For instance, the inductive component may comprise a pair of inductors L, with a supply voltage V.sub.DD applied at a node intermediate the two inductors L. By way of example, the supply voltage V.sub.DD may be a supply voltage for a logic circuit, e.g., equal to about 1 V.

[0089] As exemplified in FIG. 5, the capacitive component may comprise one or more (e.g., a pair of) variable capacitors or varactors C.sub.V coupled in series. As exemplified herein, the control signal V.sub.C may be applied at a node 524 intermediate the two varactors C.sub.V.

[0090] As exemplified in FIG. 5, the LC resonant circuit 518 may further comprise an array (or bank) of capacitors 520 coupled in parallel to the varactor(s) C.sub.V.

[0091] The array of capacitors 520 may be configured to receive a set of configuration signals from a calibration circuit 52. The configuration signals may be used to activate and de-activate a set of switches respectively coupled to the capacitors in the array of capacitors 520, so that the overall capacitance of the capacitive component of the LC resonant circuit 518 may be changed to tune the output frequency of the voltage-controlled oscillator 510.

[0092] In one or more embodiments, the calibration circuit 52 may comprise a register 522 (e.g., a twelve-bit register). The register 522 may comprise a serial-in parallel-out (SIPO) register. The SIPO register 522 may have a data-in input D configured to be coupled to a voltage signal providing a high logic value, e.g., the supply voltage V.sub.DD. The SIPO register 522 may have a reset input R configured to receive a reset signal R. The SIPO register 522 may have a clock input ck configured to receive a digital (e.g., pulsed) signal generated by an integrator circuit.

[0093] In one or more embodiments, the reset signal R may comprise pulses corresponding to the start of dead time intervals DT between the transmitted chirp signals.

[0094] As exemplified in FIG. 5, the integrator circuit may comprise a digital integrator implemented by a counter circuit 526. The counter circuit 526 may have a reset input R configured to receive the reset signal R, and a clock input ck configured to receive a digital (e.g., pulsed) signal generated at the output of an AND logic gate 528. For instance, the counter circuit 526 may have a counter modulus of 2.sup.3, i.e., it may generate a pulse at its output as a result of a number 2.sup.3=8 of pulses received at the respective clock input ck.

[0095] As exemplified in FIG. 5, the AND logic gate 528 may have a first input configured to receive an output signal from an edge-triggered D flip-flop circuit 530. The D flip-flop circuit 530 may have a data-in input D configured to be coupled to a voltage signal providing a high logic value, e.g., the supply voltage V.sub.DD. The D flip-flop circuit 530 may have a clock input ck configured to receive the digital control signal DOWN generated by the phase-frequency detector circuit 502. The D flip-flop circuit 530 may have a reset input R configured to receive a reset signal R from the output of an OR logic gate 532.

[0096] As exemplified in FIG. 5, the OR logic gate 532 may have a first input configured to receive the digital control signal UP generated by the phase-frequency detector circuit 502, and a second input configured to receive the reset signal R. Therefore, the reset signal R may comprise pulses corresponding to pulses in the reset signal R and pulses in the control signal UP.

[0097] As exemplified in FIG. 5, the AND logic gate 528 may have a second input configured to receive a timing signal TS from a timer circuit 54.

[0098] For instance, the timing signal TS may be generated as an inverted replica (by an inverter circuit 534) of an output signal from a counter circuit 536.

[0099] As exemplified in FIG. 5, the counter circuit 536 may have a reset input R configured to receive the reset signal R, and a clock input ck configured to receive a digital (e.g., pulsed) signal generated at the output of an AND logic gate 538. For instance, the counter circuit 536 may have a counter modulus of 2.sup.7, i.e., it may generate a pulse at its output as a result of a number 2.sup.7=128 of pulses received at the respective clock input ck.

[0100] As exemplified in FIG. 5, the AND logic gate 538 may have a first input configured to receive the reference signal f.sub.ref (e.g., by coupling to node 500) and a second input configured to receive the timing signal TS (e.g., via a feedback loop of the timer circuit 54).

[0101] As exemplified in FIG. 5, the PLL circuit 50 may comprise a switch S.sub.V configured to selectively couple the control node 508 of the voltage-controlled oscillator 510 to a node 540 providing a reference control voltage V.sub.C,min.

[0102] The switch S.sub.V may be controlled by the timing signal TS. For instance, the switch S.sub.V may be close during the calibration phase of the PLL circuit 50 (e.g., during the dead times DT between the chirp signals) and may be open during the transmission phase of signal TX.

[0103] Therefore, in one or more embodiments a counter circuit 536 may be used to set the timing of the calibration phase. The calibration may start with a reset pulse in the reset signal R at the beginning of a dead time. The dynamic calibration may rely on (digital) integration of the control signal DOWN, e.g., exploiting pulses in the signal DOWN to advance the counter 526 (e.g., a 2.sup.3 counter). The output signal from the counter 526 may be used to trigger shifts of the register 522, thereby generating a thermometer code (e.g., a 12-bit thermometer code) for activating (e.g., inserting via respective switches) the capacitors in the array of capacitors 520. For instance, each shift of the value of the register 522 may result in a unit capacitor in the array of capacitors 520 being coupled in parallel to the varactors C.sub.V of the LC resonant circuit 518.

[0104] In one or more embodiments, the counter circuit 536 (e.g., a 2.sup.7 counter) may define the whole calibration time.

[0105] FIG. 6 is a circuit block diagram exemplary of another PLL circuit 60 according to one or more embodiments, e.g., for use in a radar sensor.

[0106] Differently from the circuit exemplified in FIG. 5, the circuit exemplified in FIG. 6 may rely on an analog calibration circuit 62. The circuit exemplified in FIG. 6 may thus comprise a main charge pump circuit 504a and an auxiliary charge pump circuit 504b coupled to the PFD circuit 502 to receive the signals UP and DOWN. It is noted that, despite being illustrated at different locations of FIG. 5 for ease of illustration, the main and auxiliary charge pump circuits 504a and 504b may be coupled at the output of the same PFD circuit 502.

[0107] As exemplified in FIG. 6, the register 522 may comprise a serial-in parallel-out (SIPO) register. The SIPO register 522 may have a data-in input D configured to be coupled to a voltage signal providing a high logic value, e.g., the supply voltage V.sub.DD. The SIPO register 522 may have a reset input R configured to receive a reset signal R. The SIPO register 522 may have a clock input ck configured to receive a digital (e.g., pulsed) signal generated by an AND logic gate 600.

[0108] As exemplified in FIG. 6, the AND logic gate 600 may have a first input configured to receive an output signal from a comparator circuit 602. The comparator circuit 602 may be configured to compare a threshold voltage signal VTH received at a respective first (e.g., non-inverting) input 604 to a voltage signal V.sub.CP received at a respective second (e.g., inverting) input 606.

[0109] As exemplified in FIG. 6, the auxiliary charge pump circuit 504b may provide an auxiliary pulsed current I.sub.CP,A to node 606. The auxiliary current I.sub.CP,A may be used to charge an integrator capacitance C.sub.C coupled between node 606 and a supply voltage node providing a supply voltage V.sub.DD. A switch S.sub.C may be provided in parallel to the integrator capacitance C.sub.C to selectively discharge the integrator capacitance C.sub.C.

[0110] The switch S.sub.C may be controlled by an integration signal IS generated at an output of a timer circuit 64.

[0111] As exemplified in FIG. 6, the timer circuit 64 may comprise an OR logic gate 608 configured to generate the integration signal IS. The OR logic gate 608 may have a first input configured to receive the reset signal R, and a second input configured to receive a signal f.sub.ck generated at the output of a frequency divider circuit 610.

[0112] The frequency divider circuit 610 (e.g., a divider by factor 2.sup.3=8) may have a reset input R configured to receive the reset signal R, and a clock input ck configured to receive the reference signal f.sub.ref (e.g., the same reference signal of the PLL circuit). In one or more embodiments, providing the reference signal f.sub.ref at the clock input ck of the frequency divider circuit 610 may be advantageous, insofar as it may not require an internal clock generator.

[0113] As exemplified in FIG. 6, the AND logic gate 600 may have a second input configured to receive a timing signal TS, e.g., an inverted replica (for instance, generated by an inverter circuit 612) of an output signal from a counter circuit 614.

[0114] As exemplified in FIG. 6, the counter circuit 614 may have a reset input R configured to receive the reset signal R, and a clock input ck configured to receive the signal f.sub.ck generated at the output of the frequency divider circuit 610. For instance, the counter circuit 614 may have a counter modulus of 2.sup.4, i.e., it may generate a pulse at its output as a result of a number 2.sup.4=16 of pulses received at the respective clock input ck.

[0115] As exemplified in FIG. 6, the PLL circuit 60 may comprise a switch S.sub.V configured to selectively couple the control node 508 of the voltage-controlled oscillator 510 to a node 540 providing a reference control voltage V.sub.C,min.

[0116] The switch S.sub.V may be controlled by the timing signal TS. For instance, the switch S.sub.V may be closed during the calibration phase of the PLL circuit 60 (e.g., during the dead times between the chirp signals) and may be opened during the transmission phase of signal TX.

[0117] Therefore, in one or more embodiments a counter circuit 614 may be used to set the timing of the calibration phase. The calibration may start with a reset pulse at the beginning of a dead time.

[0118] Dynamic calibration based on analog integration as exemplified in FIG. 6 may exploit the sign of the current I.sub.CP,A generated by the auxiliary charge pump circuit 504b to trigger the comparator circuit 602 that drives the register 522.

[0119] In one or more embodiments as exemplified in FIG. 6, a commutation of the comparator circuit 602 after the integration of a certain number of current pulses of the auxiliary current I.sub.CP,A may trigger a shift of the register 522, thereby generating a thermometer code (e.g., a 12-bit thermometer code) for activating the capacitors in the array of capacitors 520. For instance, each shift of the value of the register 522 may result in a unit capacitor in the array of capacitors 520 being coupled in parallel to the varactors C.sub.V of the LC resonant circuit 518.

[0120] The speed of the analog integrator may benefit from relying on an auxiliary charge pump circuit 504b, insofar as the current I.sub.CP,A, the capacity C.sub.C and the threshold voltage VTH can be sized properly to set the switching time T.sub.SW of comparator 602 congruent with the chirp dead time DT. For instance, the current I.sub.CP,A and the capacity C.sub.C may be sized once defined the switching time T.sub.SW, based on the following equation:

[00004]$I_{\mathrm{CP},A}=\frac{C_C.Math.V_{TH}}{T_{SW}}$

[0121] In one or more embodiments as exemplified in FIG. 6, the divider circuit 610 may define the clock period of the clock signals f.sub.ck. A first semi-period of the clock signals f.sub.ck may be used to discharge the capacitance C.sub.C, and a second semi-period of the clock signals f.sub.ck may be used for charge integration until switching of the comparator 602.

[0122] In one or more embodiments as exemplified in FIG. 6, the counter circuit 614 (e.g., a 2.sup.4 counter) may define the whole calibration time.

[0123] FIGS. 7A to 7E are diagrams exemplary of possible time evolution of various signals in one or more embodiments. In particular, FIG. 7A exemplifies a time-frequency relationship of a radar transmission signal TX, FIG. 7B exemplifies a time-amplitude relationship of a reset signal R, FIG. 7C exemplifies a time-amplitude relationship of a reference signal f.sub.ref as received at the input node 500 of a PLL circuit 50 or 60, FIG. 7D exemplifies a time-amplitude relationship of an auxiliary current I.sub.CP,A as provided by an auxiliary charge pump circuit 504b, and FIG. 7E exemplifies a time-amplitude relationship of a clock signal f.sub.ck as generated at the output of the frequency divider circuit 610. It is noted that the time scale of FIG. 7A is different from the time scale of FIGS. 7B to 7E, with these latter figures providing a magnified view of a dead time interval DT between two subsequent chirp signals.

[0124] As exemplified in FIG. 7A, the duration T.sub.m of the ramp of a chirp signal may be in the range of 10 us to 40 ?s, and the duration of the dead time DT may be in the range of 2 us to 10 ?s.

[0125] As exemplified in FIG. 7B, a reset pulse may be generated in the reset signal R at the beginning or shortly after the beginning of a dead time DT to trigger (or enable) the calibration phase.

[0126] As exemplified in FIG. 7C, the reference signal f.sub.ref provided at the input node 500 of the PLL circuit may provide a reference time. Purely by way of non-limiting example, the reference signal f.sub.ref may have a period of 10 ns (1 ns=10.sup.?9 s), i.e., a frequency of 100 MHz.

[0127] As exemplified in FIG. 7D, the auxiliary current I.sub.CP,A generated by the auxiliary charge pump circuit 504b may comprise pulses having a duration of, e.g., 2 ns and the same period of the reference signal f.sub.ref.

[0128] As exemplified in FIG. 7E, the period T.sub.ck of the clock signal f.sub.ck generated at the output of the frequency divider circuit 610 may be equal to 80 ns (i.e., eight times the period of the reference signal f.sub.ref, insofar as the divider circuit 610 has modulus 2.sup.3). Half of the period T.sub.ck (e.g., 40 ns) may be used for discharging the integrator capacitance C.sub.C, and another half of the period T.sub.ck (e.g., another 40 ns) may be used for integration.

[0129] Therefore, purely by way of non-limiting example, the overall calibration time may be equal to 1.28 ?s in case the reference signal f.sub.ref has a frequency of 100 MHz and assuming 4 pulses of the auxiliary current I.sub.CP,A, wherein each pulse has a duration of 2 ns. The overall calibration time may be equal to sixteen times the period of the clock signal f.sub.ck, insofar as the counter circuit 614 has modulus 2.sup.4.

[0130] Both digital and analog calibration techniques (e.g., as exemplified with reference to FIGS. 5 and 6, respectively) may be suitable for cellular applications. This first case may involve pre-charging the filter capacitance CF and the varactor(s) C.sub.V to an average value of the control voltage V.sub.C (e.g., selecting V.sub.C,min equal to said average value).

[0131] Another solution can be adopted, e.g., with the aim of achieving a higher response speed. This second case may involve pre-charging the filter capacitance CF and the varactor(s) C.sub.V to a value close to the final value of the control voltage V.sub.C.

[0132] Such a second solution may be implemented by replacing the switch S.sub.V with an A/D flash converter, as exemplified in FIG. 8.

[0133] As exemplified in FIG. 8, one or more embodiments may comprise a voltage divider network or voltage ladder comprising a set of resistances Ro, . . . , RN coupled in series between the supply voltage V.sub.DD and ground GND to generate a set of increasing voltage levels V.sub.C1, . . . , V.sub.CN.

[0134] The control node 508 of the voltage-controlled oscillator 510 (to which the filter capacitance CF and the varactor(s) C.sub.V are coupled) may be selectively coupleable to any of the voltage levels V.sub.C1, . . . , V.sub.CN by respective switches S.sub.V1, . . . , S.sub.VN. The switches S.sub.V1, . . . , S.sub.VN may be controlled by respective control signals generated by decoding, at a decoder circuit 800, the most significant bits of the divider programming word (or coarse division word) CDW of the frequency divider circuit 514 in the feedback loop of the PLL circuit 50 or 60.

[0135] By way of example, once a change of communication channel is desired, the frequency divider 514 may modify its division ratio by changing the divider programming word and may return the bit sequence to the decoder circuit 800. The decoder may thus enable a part of the voltage ladder through the switches S.sub.V1, . . . , S.sub.VN so that the varactor(s) C.sub.V and the filter capacitance CF may be pre-loaded at a value close to the final value of the control voltage. Once the varactor(s) and the filter capacitance are pre-loaded, the PLL loop may be closed and the varactor(s) may perform a fine tuning by compensating the residual frequency difference between signals f.sub.ref and f.sub.O.

[0136] Therefore, in one or more embodiments the filter capacitor CF and the varactor(s) C.sub.V may be connected to one of the voltage levels generated by a resistive string which corresponds to the conversion of the most significant bits (MSB) of the divider programming word.

[0137] It is noted that the inductive component and the capacitive component in the LC resonant circuit 518 may be arranged according to various other arrangements (compare, for instance, the different arrangements exemplified in FIGS. 2, 5 and 6), without departing from the scope of this disclosure. For instance, one or more embodiments may comprise one of a Hartley oscillator, a Colpitts oscillator or a Clapp oscillator.

[0138] It is noted that, while being suitable for performing a calibration phase during the dead times between chirp signals, one or more embodiments may involve performing the calibration phase (also) at the start-up of the PLL circuit.

[0139] As exemplified in FIG. 9, one or more embodiments may be applied in a vehicle V. The vehicle V may comprise a power supply system 900, a control unit 902 (e.g., a microcontroller unit, MCU) and a radar sensor 904.

[0140] The radar sensor 904 may comprise a PLL circuit 906, a transmitter circuit 908, a receiver circuit 910, transmitter antenna 912 and a receiver antenna 914.

[0141] The power supply system 900 may provide a supply voltage (e.g., equal to 1 V or 3.3 V) to the radar sensor 904 and a supply voltage (e.g., equal to 3.3 V or 5 V) to the control unit 902.

[0142] The control unit 902 may provide an input reference signal f.sub.ref to control the PLL circuit 906. The PLL circuit 906 may provide a variable-frequency signal f.sub.O to drive the transmitter circuit 908 (e.g., according to a FMCW driving scheme). The transmitter circuit may bias the transmitter antenna 912 accordingly, to emit a transmission signal TX.

[0143] The receiver antenna 914 may receive the echo signal RX and provide it to the receiver circuit 910 which processes the information about the transmitted and received signals to provide information about the distance of a target object.

[0144] One or more embodiments may thus provide one or more of the following advantages: fast dynamic calibration suitable for use in automotive radar sensors, insofar as one or more embodiments may not require a delay equal to N times the settling time of the PLL circuit; dynamic compensation of temperature variations; fast pre-charge of the filter capacitor CF (via the switch S.sub.V or switches S.sub.V1, . . . , S.sub.VN) during the dead times, which may result in a faster response of the PLL circuit; improved accuracy by performing the dynamic calibration during dead times between subsequent chirp signals; fast repositioning at the minimum frequency value f.sub.min after sweeping a complete frequency ramp during a chirp signal; and faster data acquisition as a result of the reduction of the dead time duration between subsequent chirp signals.

[0145] It is noted that temperature variations may produce a deviation of the PLL output frequency. The calibration technique disclosed herein facilitates compensating process and supply variations, as well as temperature variations, by the insertion of the capacitances of the array of capacitances of the LC resonant circuit. In particular, a calibration technique as disclosed herein may be dynamic, i.e., it may be performed between one chirp and another. By acquiring several hundred chirps for each radar scan, one or more embodiments facilitate a constant compensation of temperature variations, in contrast with conventional systems which do not have this characteristic insofar as they perform the calibration at startup and cannot compensate for variations that occur after and throughout the operating time. In one or more embodiments, the temperature compensation may be accurate insofar as it is performed with the same periodicity as the chirp, e.g., 10-40 ?s. Temperature variations taking place within a single chirp period may be negligible.

[0146] As exemplified herein, a circuit such as a PLL circuit (e.g., 50, 60) may comprise: a tunable resonant circuit (e.g., 518) having a first node (e.g., 519a) and a second node (e.g., 519b) and comprising an inductance (e.g., L) coupled between said first node and said second node, a variable capacitance (e.g., C.sub.V) coupled between said first node and said second node, and a set of capacitances (e.g., 520) selectively coupleable between said first node and said second node; a control node (e.g., 508) coupled to said variable capacitance, the control node configured to receive a control signal (e.g., V.sub.C), wherein said tunable resonant circuit is tunable as a function of said control signal; a biasing circuit (e.g., 516) coupled to said tunable resonant circuit and configured to bias the tunable resonant circuit to generate a variable-frequency output signal (e.g., f.sub.O) between said first node and said second node; a phase-frequency detector circuit (e.g., 502) sensitive to an input reference signal (e.g., f.sub.ref) and to said variable-frequency output signal and configured to generate a first digital control signal (e.g., UP) and a second digital control signal (e.g., DOWN) as a function of a timing offset of said variable-frequency output signal with respect to said input reference signal, wherein said first digital control signal asserted is indicative of a first operational state wherein said timing offset has a first sign (e.g., indicative of said variable-frequency output signal being phase delayed with respect to said input reference signal) and said second digital control signal asserted is indicative of a second operational state wherein said timing offset has a second sign, opposite said first sign (e.g., indicative of said input reference signal being phase delayed with respect to said variable-frequency output signal); a charge pump circuit (e.g., 504; 504a) and a filter circuit (e.g., 506) configured to generate said control signal as a function of said first digital control signal and said second digital control signal; a timer circuit (e.g., 54; 64) sensitive to a reset signal (e.g., R) and configured to generate a timing signal (e.g., TS), wherein said timing signal is asserted in response to a pulse sensed in said reset signal and de-asserted after a time interval (e.g., T.sub.ck/2) from said sensed pulse; and a calibration circuit (e.g., 52; 62) configured to selectively couple between said first node and said second node selected capacitances in said set of capacitances as a function of said second digital control signal in response to said timing signal being asserted.

[0147] As exemplified herein, the circuit may be configured to: generate said variable-frequency output signal comprising frequency sweeps separated by dead times (e.g., DT); and generate pulses in said reset signal at the beginning of said dead times.

[0148] As exemplified herein, the circuit may comprise a switch (e.g., S.sub.V) configured to selectively couple said control node to a reference control voltage (e.g., V.sub.C,min) in response to said timing signal being asserted.

[0149] As exemplified herein, the circuit may comprise: a feedback loop configured to provide said variable-frequency output signal to said phase-frequency detector circuit, wherein the feedback loop comprises a frequency divider circuit (e.g., 514); a voltage divider network (e.g., V.sub.DD, Ro, . . . , RN) configured to generate a set of different reference control voltages (e.g., V.sub.C1, . . . , V.sub.CN); and a set of switches (e.g., S.sub.V1, . . . , S.sub.VN) configured to selectively couple said control node to a respective reference control voltage in said set of different reference control voltages as a function of a divider programming word (e.g., CDW) of said frequency divider circuit.

[0150] As exemplified herein, said calibration circuit may be configured to count a number of pulses occurring in said second digital control signal and to couple between said first node and said second node a capacitance in said set of capacitances in response to a counted number of pulses in said second digital control signal reaching a threshold value.

[0151] As exemplified herein, said calibration circuit may comprise a digital counter circuit (e.g., 526) configured to count said number of pulses occurring in said second digital control signal.

[0152] As exemplified herein, said calibration circuit may comprise: a further charge pump circuit (e.g., 504b) configured to generate a pulsed current signal (e.g., I.sub.CP,A) as a function of said first digital control signal and said second digital control signal; an integrator circuit (e.g., S.sub.C, C.sub.C) configured to generate a signal (e.g., V.sub.CP) indicative of a value of an integral over time of said pulsed current signal; and a comparator circuit (e.g., 602) configured to compare said signal indicative of a value of an integral over time of said pulsed current signal to a threshold voltage (e.g., VTH) to detect said counted number of pulses in said second digital control signal reaching said threshold value.

[0153] As exemplified herein, a radar sensor (e.g., 904) may comprise a circuit (e.g., 906) according to one or more embodiments and a transmitter circuit (e.g., 908) coupled to an antenna (e.g., 912). The circuit may be configured to receive said input reference signal from a microcontroller unit (e.g., 902) and provide said variable-frequency output signal to said transmitter circuit.

[0154] As exemplified herein, a vehicle (e.g., V) may comprise a radar sensor according to one or more embodiments.

[0155] As exemplified herein, a method of operating a circuit according to one or more embodiments may comprise: biasing the tunable resonant circuit to generate a variable-frequency output signal between said first node and said second node; generating a first digital control signal and a second digital control signal as a function of an input reference signal and said variable-frequency output signal, wherein said first digital control signal asserted is indicative of a first operational state wherein said timing offset has a first sign and said second digital control signal asserted is indicative of a second operational state wherein said timing offset has a second sign, opposite said first sign; generating a control signal as a function of said first digital control signal and said second digital control signal; receiving said control signal at said control node coupled to said variable capacitance and tuning said tunable resonant circuit as a function of said control signal; sensing a reset signal and generating a timing signal, wherein said timing signal is asserted in response to a pulse sensed in said reset signal and de-asserted after a time interval from said sensed pulse; and selectively coupling between said first node and said second node selected capacitances in said set of capacitances as a function of said second digital control signal in response to said timing signal being asserted.

[0156] Without prejudice to the underlying principles, the details and embodiments may vary, even significantly, with respect to what has been described by way of example only, without departing from the extent of protection.

[0157] The extent of protection is determined by the annexed claims.