Planar power module with spatially interleaved structure

Abstract

Provided is a planar power module with a spatially interleaved structure, including a top power substrate, a bottom power substrate arranged opposite to the top power substrate, and a plurality of interleaved switch units configured between the top power substrate and the bottom power substrate; wherein adjacent interleaved switch units are electrically connected through a current commutator so that the interleaved switch units form spatial position interleaving. Problems of uneven parallel currents and uneven heat dissipation in the power module are solved.

Claims

1. A planar power module with a spatially interleaved structure, comprising a top power substrate, a bottom power substrate arranged opposite to the top power substrate, and a plurality of interleaved switch units configured between the top power substrate and the bottom power substrate; the plurality of interleaved switch units comprises a plurality of first bower semiconductor chips, a plurality of second bower semiconductor chips, and a plurality of power spacers; wherein each of the plurality of interleaved switch units comprises one of the plurality of first power semiconductor chips, one of the plurality of second power semiconductor chips, and two of the plurality of power spacers, which are configured between the top power substrate and the bottom power substrate; in each of the plurality of interleaved switch units, the first power semiconductor chip is arranged on a top of one of the two power spacers, and the second power semiconductor chip is arranged on a bottom of the other one of the two power spacers; and in the plurality of interleaved switch units, the plurality of first power semiconductor chips and the plurality of second power semiconductor chips are arranged at intervals.

2. The planar power module with a spatially interleaved structure according to claim 1, wherein the top power substrate comprises a top insulation layer, a first metal layer configured on a lower surface of the top insulation layer, and a top conductive substrate configured on an upper surface of the top insulation layer; wherein the first metal layer is connected with an AC power terminal.

3. The planar power module with a spatially interleaved structure according to claim 2, wherein the bottom power substrate comprises a bottom insulation layer, a second metal layer configured on an upper surface of the bottom insulation layer, and a bottom conductive substrate configured on a lower surface of the bottom insulation layer; wherein the second metal layer is connected with a DC power terminal.

4. The planar power module with a spatially interleaved structure according to claim 3, wherein the top insulation layer and the bottom insulation layer are made of silicon nitride.

5. The planar power module with a spatially interleaved structure according to claim 3, wherein the top conductive layer and the bottom conductive layer are made of aluminum.

6. The planar power module with a spatially interleaved structure according to claim 1, wherein the first power semiconductor chip and the second power semiconductor chip that are adjacent to each other are connected in parallel to form upper and lower switches of a half-bridge structure.

7. The planar power module with a spatially interleaved structure according to claim 1, wherein the first power semiconductor chip and the second power semiconductor chip are silicon-based power semiconductor chips.

8. The planar power module with a spatially interleaved structure according to claim 1, wherein the power spacers are made of copper.

Description

BRIEF DESCRIPTION OF DRAWINGS

(1) FIG. 1 is a schematic diagram of an overall structure of a planar power module with a spatially interleaved structure according to an embodiment of the present invention;

(2) FIG. 2 is a schematic diagram of components of a planar power module with a spatially interleaved structure according to an embodiment of the present invention; and

(3) FIG. 3 is a front view of a planar power module with a spatially interleaved structure according to an embodiment of the present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

(4) In order to make the objectives, technical solutions and advantages in implementations of the present invention clearer, the technical solutions in the implementations of the present invention will be described in detail below with reference to the accompanying drawings in the implementations of the present invention. It is obvious that the implementations to be described are only a part rather than all of the implementations of the present invention. All other implementations derived by those of ordinary skill in the art based on the implementations of the present invention without creative efforts should fall within the protection scope of the present invention. Therefore, the following detailed description of the implementations of the present invention provided in the accompanying drawings is not intended to limit the scope for which protection is sought by the present invention, but merely to represent the selected implementations of the present invention. All other implementations derived by those of ordinary skill in the art based on the implementations of the present invention without creative efforts should fall within the protection scope of the present invention.

(5) Specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

(6) The present invention discloses a planar power module with a spatially interleaved structure, which is intended to overcome the deficiency of the prior art.

(7) Referring to FIGS. 1 to 3, an embodiment of the present invention provides a planar power module with a spatially interleaved structure, including a top power substrate, a bottom power substrate arranged opposite to the top power substrate, and a plurality of interleaved switch units 1 (composed of 11 and 12 or 13 and 14) configured between the top power substrate and the bottom power substrate.

(8) Adjacent interleaved switch units 1 are electrically connected through a current commutator 2, so that the interleaved switch units 1 form spatial position interleaving.

(9) In this embodiment, the top power substrate includes a top insulation layer 118, a first metal layer 117 configured on a lower surface of the top insulation layer 118, and a top conductive layer 119 configured on an upper surface of the top insulation layer 118.

(10) The first metal layer 117 is connected with an AC power terminal 133.

(11) In this embodiment, the bottom power substrate includes a bottom insulation layer 121, a second metal layer 120 configured on an upper surface of the bottom insulation layer 121, and a bottom conductive layer 122 configured on a lower surface of the bottom insulation layer 121.

(12) The second metal layer 120 is connected with a DC power terminal. The DC power terminal includes a positive terminal 131 and a negative terminal 132.

(13) In this embodiment, the interleaved switch units include: a first power semiconductor chip 116, a second power semiconductor chip 113, and a plurality of power spacer configured between the top power substrate and the bottom power substrate (it is to be understood that the chips herein configured on the top are defined as first power semiconductor chips, such as icons 116, 112, 108, 104, and similarly, the chips configured at the bottom are defined as second power semiconductor chips 113, 109, 105, 100). Icons of the power spacer are (102, 103, 106, 107, 110, 111, 114, 115, 123, 124, 125, 126, 127, 128, 129, 130). It is to be understood that the power spacers are configured for electrical connections, heat transfer, and mechanical support.

(14) The first power semiconductor chip 116 is configured between the AC power terminal 133 and the first metal layer 117, the second power semiconductor chip 113 is configured between the DC power terminal and the second metal layer 120, and the first power semiconductor chip and the second power semiconductor chip 113 are interleaved in a vertical direction.

(15) In this embodiment, the first power semiconductor chip 116 and the second power semiconductor chip 113 that are adjacent to each other are connected in parallel to form upper and lower switches of a half-bridge structure.

(16) It shall be noted that two groups of parallel power semiconductor chips (four in each group and a total of 8) constitute upper and lower switches of a classical half-bridge structure in this embodiment. In actual power module design, the chip's number via parallel or series connection domains the current capability and breakdown voltage level. In addition, anti-parallel diode chips can be considered as required. It is noteworthy that the power semiconductor chips mentioned in this embodiment include, but are not limited to, wide-band-gap power semiconductor chips.

(17) In this embodiment, the interleaved switch units are connected through a current commutator, so that the first power semiconductor chip and the second power semiconductor chip form spatial position interleaving. Adjacent semiconductor chips are distributed on the top power substrate and the bottom power substrate, thereby achieving two thermal performance advantages under a compact layout condition:

(18) Firstly, a degree of thermal coupling among a plurality of chips is greatly reduced. It may be understood that under the same working conditions and with the same semiconductor chip, compared with the traditional power module, coupling thermal resistance between the chips is reduced a lot, so the temperature of the chips may also be reduced greatly. It is to be understood that the chips can bear greater current levels and power levels.

(19) Secondly, thermal coupling between each chip and the remaining chips is consistent, and even chip temperatures in the working state can greatly improve the overall reliability of the power module. It is to be understood that the even chip temperatures can ensure consistent threshold voltages, thereby ensuring dynamic current equalization between the parallel chips. Besides, the even chip temperatures can ensure the reliability of the soldering layers between the chips and the power substrates, avoiding thermal runaway due to a certain soldering layer failure. The spatial interleaving arrangement of the plurality of chips further directly determines the balanced current sharing.

(20) Based on this embodiment, electrical properties can be improved in two aspects: the first is mutual inductance cancellation in the inner of interleaved switch unit.

(21) The second is mutual inductance cancellation between adjacent interleaved switches. Such two effects jointly reduce the parasitic inductance in the commutation loop and implement balanced current sharing between parallel branches.

(22) This embodiment implements a half-bridge structure. Such a structure (which may be composed of one or more structures in series-parallel connections) may constitute, but is not limited to, DC-AC, DC-DC, AC-AC, and AC-DC converter circuits such as a three-phase inverter full-bridge circuit, a synchronous rectifier, and a single-phase inverter full-bridge. The packaging structure proposed in this embodiment has a very low parasitic inductance of the commutation loop and has static and dynamic balanced current sharing functions of parallel branches for high-current applications, so the balanced current sharing and lower voltage overshoot can be obtained. In this embodiment, the thermal coupling of all chips is greatly reduced, and degrees of thermal coupling among all the chips are rather equal, so high heat transfer efficiency and even chip junction temperatures distribution can be obtained. In this embodiment, the heat generated by all chips has two transfer paths, thus greatly reducing the thermal resistance from the chips to the environment. Based on the above, the packaging structure proposed in the present invention can operate reliably at a very high current level, a very high switching frequency, and a high junction temperature. Thereby, it can make full use of the superior performance of semiconductor chips, especially of third-generation semiconductor chips.

(23) In this embodiment, the first power semiconductor chip and the second power semiconductor chip may be silicon-based power semiconductor chips.

(24) It shall be noted that in other embodiments, the first power semiconductor chip and the second power semiconductor chip may also be SiC-based or GaN-based power semiconductor chips, which are not specifically limited herein, but these solutions are all within the protection scope of the present invention.

(25) In this embodiment, the power spacer may be made of copper.

(26) It shall be noted that in other embodiments, the power spacer assembly may also be made of elementary substance aluminum, copper-molybdenum-copper composite plate material, tungsten-copper alloy material, or zinc-copper alloy material, which are not specifically limited herein, but these solutions are all within the protection scope of the present invention.

(27) In this embodiment, the top insulation layer and the bottom insulation layer may be made of silicon nitride.

(28) It shall be noted that in other embodiments, the top insulation layer 118 and the bottom insulation layer 121 may also be made of aluminum oxide or aluminum nitride, which are not specifically limited herein, but these solutions are all within the protection scope of the present invention.

(29) In this embodiment, the top conductive layer 119 and the bottom conductive layer 122 may be made of aluminum.

(30) It shall be noted that in other embodiments, the top conductive layer and the bottom conductive layer may also be made of copper, which are not specifically limited herein, but these solutions are all within the protection scope of the present invention.

(31) Based on the planar power module with a spatially interleaved structure according to the present invention, adjacent first power semiconductor chips and second power semiconductor chips form a spatially interleaved structure; that is, any two adjacent chips are not on the same horizontal plane. Such an interleaved arrangement manner can greatly reduce a degree of thermal coupling among all chips, making the degree of thermal coupling among the chips relatively average, to reach even temperature distribution. With such an interleaved arrangement manner, in the adjacent parallel chips' current loop, current directions are opposite. In this way, an effect of greatly mutual parasitic inductance may be produced between adjacent chips, thereby greatly reducing parasitic inductance, and balancing parasitic inductance of each parallel commutation branch. This makes the power module have smaller voltage overshoot and dynamic and static balanced current sharing during switching transience.

(32) The above are merely preferred implementations of the present invention. The protection scope of the present invention is not limited to the above embodiments, and all technical solutions under the idea of the present invention fall within the protection scope of the present invention.