SEMICONDUCTOR DEVICE AND FABRICATION METHODS THEREOF

Abstract

A semiconductor device and fabricating method thereof is disclosed. The method comprises depositing epitaxial layers over a silicon substrate to form a semiconductor layer surface; forming at least one mesa portion on the semiconductor layer surface; depositing a metal stack on the semiconductor layer surface; subjecting the semiconductor layer surface to a rapid thermal annealing system for a two-step ohmic contact annealing in H.sub.2/N.sub.2 forming gas (FG) and then nitrogen; subjecting the semiconductor layer surface to an oxygen plasma treatment; and depositing a T-shaped metal gate on the semiconductor layer surface. A semiconductor device comprises a semiconductor layer surface having an epitaxial layer disposed over a silicon substrate; at least one mesa portion formed on the semiconductor layer surface; a metal stack, disposed on the semiconductor layer surface, and sequentially annealed in FG and nitrogen; and a T-shaped metal gate on the semiconductor layer surface.

Claims

1. A method of fabricating a semiconductor device, the method comprising: (a) depositing an epitaxial layer over a substrate to form a semiconductor layer surface; (b) subjecting the semiconductor layer surface to an etching process for forming at least one mesa portion; (c) depositing a metal stack on the semiconductor layer surface; (d) subjecting the semiconductor layer surface to a rapid thermal annealing (RTA) system for ohmic contact annealing in forming gas (FG) comprising H.sub.2 and N.sub.2; and (e) subjecting the semiconductor layer surface to the RTA system for ohmic contact annealing in nitrogen (N.sub.2).

2. The method of claim 1, wherein the substrate comprises silicon, and further comprising: (f) subjecting the semiconductor layer surface to an oxygen plasma treatment; and (g) depositing a T-shaped metal gate on the semiconductor layer surface.

3. The method of claim 1, wherein the epitaxial layer is deposited over the substrate using metal organic chemical vapor deposition (MOCVD).

4. The method of claim 1, wherein the epitaxial layer comprises: a buffer layer comprising gallium nitride (GaN); a back barrier layer formed on the buffer layer, the back barrier layer comprising In.sub.yGa.sub.1−yN, wherein y is in a range of 0.05-0.2; a channel layer formed on the back barrier layer, the channel layer comprising GaN; an interlayer formed on the channel layer, the interlayer comprising AlN; a lattice-matched barrier layer formed on the interlayer, the lattice-matched barrier layer comprising In.sub.xAl.sub.1−xN, wherein x is 0.17; and a cap layer formed on the lattice-matched barrier layer, the cap layer comprising GaN.

5. The method of claim 4, wherein the etching treatment removes material from a portion of the epitaxial layer, and the at least one mesa portion is formed by removing material from a portion of the buffer layer of the epitaxial layer, such that a ledge of the buffer layer is formed.

6. The method of claim 1, wherein the metal stack comprises titanium (Ti), aluminum (Al), nickel (Ni), gold (Au), or a combination of any two or more thereof.

7. The method of claim 1, wherein: step (d) comprises annealing in FG at a temperature in a range of 700-900° C. for a duration in a range of 10-50 seconds; and step (e) comprises annealing in N.sub.2 at a temperature in a range of 750-950° C. for a duration in a range of 10-50 seconds.

8. The method of claim 1, wherein the T-shaped metal gate comprises Ni, Au, or a combination thereof, with a gate width (W.sub.g) of 2×20 μm.

9. The method of claim 1, wherein step (e) occurs after step (d) and at least step (d) occurs before step (g), and FG comprises 5% H.sub.2 and 95% N.sub.2.

10. The method of claim 1, wherein the semiconductor device comprises a high electron mobility transistor (HEMT).

11. The method of claim 10, wherein the semiconductor device comprises a 50-nm gate length InAlN/GaN HEMT on Si.

12. The method of claim 11, wherein the 50-nm gate length InAlN/GaN HEMT on Si semiconductor device has surface properties including one or more of: a subthreshold swing (SS) in a range of 90-140 mV/dec, a transconductance (g.sub.m) peak in a range of 315-515 mS/mm, a low draw-induced barrier lowing (DIBL) in a range of 50-80 mV/V, and high power gain cutoff frequency (f.sub.max) in a range of 200-340 GHz.

13. The method of claim 1, wherein no passivation process is applied to the semiconductor device.

14. A semiconductor device comprising: a semiconductor layer surface including an epitaxial layer over a substrate comprising silicon; at least one mesa portion formed on the semiconductor layer surface; a metal stack on the semiconductor layer surface, the metal stack being sequentially annealed in FG and then in N.sub.2, each for a predetermined duration; and a T-shaped metal gate on the semiconductor layer surface.

15. The semiconductor device of claim 14, wherein the epitaxial layer comprises: a buffer layer comprising a group III-nitride material; a back barrier layer formed on the buffer layer, the back barrier layer comprising at least In; a channel layer formed on the back barrier layer, the channel layer comprising a group III-nitride material; an interlayer formed on the channel layer, the interlayer comprising Al; a lattice-matched barrier layer formed on the interlayer, the lattice-matched barrier layer comprising In.sub.xAl.sub.1−xN; and a cap layer formed on the lattice-matched barrier layer, the cap layer comprising a group III-nitride material.

16. The semiconductor device of claim 15, wherein the back barrier layer has a thickness in a range of 1-7 nm and comprises In.sub.0.12Ga.sub.0.88N.

17. The semiconductor device of claim 16, wherein one or more of: the buffer layer has a thickness in a range of 1-3 μm; the back barrier layer comprises InyGa1−yN, wherein y is in a range of 0.05-0.2; the channel layer comprises GaN; the channel layer has a thickness in a range of 10-20 nm; the interlayer comprises aluminum nitride (AlN); the interlayer has a thickness in a range of 0.1-2.1 nm; the lattice-matched barrier layer comprises In.sub.xAl.sub.1−xN, wherein x is in a range of 0-0.3; the lattice-matched barrier layer has a thickness in a range of 5-11 nm. the cap layer comprises GaN; the cap layer has a thickness in a range of 0-4 nm.

18. The semiconductor device of claim 16, wherein one or more of: the buffer layer comprises 2-μm undoped GaN; the lattice-matched barrier layer comprises 8-nm In.sub.0.17Al.sub.0.83N; and the cap layer comprises 2-nm GaN.

19. The semiconductor device of claim 17, having one or more of a source-drain spacing (L.sub.sd) in a range of 0-2 μm; a gate-source spacing (L.sub.gs) in a range of 375-575 nm; and a gate footprint (L.sub.a) in a range of 30-70 nm.

20. A method of subjecting a semiconductor layer surface to post-metallization annealing, the method comprising: (a) subjecting the semiconductor layer surface to a first anneal phase, the first anneal phase comprising subjecting the semiconductor layer surface to an RTA system for ohmic contact annealing in forming gas (FG) comprising H.sub.2 and N.sub.2; and (b) subjecting the semiconductor layer surface to a second anneal phase, the second anneal phase comprising subjecting the semiconductor layer surface to the RTA system for ohmic contact annealing in N.sub.2; wherein step (b) occurs after step (a).

21. The method of claim 20, further comprising: (c) subjecting the semiconductor layer surface to a pre-anneal phase, the pre-anneal phase comprising heating to a first temperature for a first predetermined duration; (d) subjecting the semiconductor layer surface to a post-anneal phase, the post-anneal phase comprising heating to a second temperature.

22. The method of claim 21, wherein: the first temperature is in a range of 15-35° C.; the first predetermined duration is in a range of 30-90 seconds; and the second temperature is in a range of 15-35° C.; step (a) comprises annealing the semiconductor layer surface in FG at a temperature in a range of 700-900° C. for a duration in a range of 10-50 seconds; step (b) comprises annealing the semiconductor layer surface in N.sub.2 at a temperature in a range of 750-950° C. for a duration in a range of 10-50 seconds; and step (d) comprises annealing the semiconductor layer surface in FG.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The invention is best understood from the following detailed description when read in connection with the accompanying drawings, with like elements having the same reference numerals. When a plurality of similar elements are present, a single reference numeral may be assigned to the plurality of similar elements with a small letter designation referring to specific elements. When referring to the elements collectively or to a non-specific one or more of the elements, the small letter designation may be dropped. This emphasizes that according to common practice, the various features of the drawings are not drawn to scale unless otherwise indicated. On the contrary, the dimensions of the various features may be expanded or reduced for clarity. Included in the drawings are the following figures:

[0013] FIG. 1 depicts an exemplary method of fabricating a semiconductor device in accordance with an embodiment of the invention;

[0014] FIGS. 2A-2B depict an exemplary semiconductor device fabricated in accordance with at least the method of FIG. 1, showing an exemplary semiconductor layer surface;

[0015] FIGS. 3A-3D is a schematic depicting steps of the method of FIG. 1;

[0016] FIG. 4 depicts exemplary parameters of an exemplary annealing step of the method of FIG. 1;

[0017] FIG. 5 depicts an X-ray photoelectron spectra (XPS) of exemplary layers taken from the semiconductor layer surface of FIGS. 2A-2B after the annealing steps of FIG. 1;

[0018] FIGS. 6A-6B are schematics depicting certain layers taken from the semiconductor layer surface of FIGS. 2A-2B, before and after the annealing steps of FIG. 1;

[0019] FIGS. 7A-7D are graphs depicting the valence band edge spectra taken from the semiconductor device of FIGS. 2A-2B after the annealing steps of FIG. 1;

[0020] FIGS. 8A-8B are graphs depicting exemplary capacitance-voltage (C-V) measurements with a frequency of 1 MHz performed on the semiconductor device of FIGS. 2A-2B after the annealing steps of FIG. 1;

[0021] FIGS. 9A-9B are graphs depicting the Ohmic contact resistance (R.sub.C) and sheet resistance (R.sub.sheet) for exemplary annealing conditions in accordance with aspects of the invention;

[0022] FIGS. 10A-10D are graphs depicting exemplary device performance measurements performed on the semiconductor device of FIGS. 2A-2B;

[0023] FIG. 11 depict a comparison of a measured balanced current/power gain cutoff frequency (f.sub.T/f.sub.max) performed on the semiconductor device of FIGS. 2A-2B and reported measurements from prior art;

[0024] FIG. 12 are graphs depicting exemplary current-voltage (I-V) measurements performed on the semiconductor device of FIGS. 2A-2B;

[0025] FIGS. 13A-13C are graphs depicting exemplary balanced current/power gain cutoff frequency (f.sub.T/f.sub.max) measurements performed on the semiconductor device of FIGS. 2A-2B; and

[0026] FIG. 14 depicts an exemplary method of subjecting a semiconductor layer surface to post-metallization annealing in accordance with an embodiment of the invention.

DETAILED DESCRIPTION OF THE INVENTION

[0027] Aspects of the invention are described herein with reference to InAlN/GaN HEMT devices on a Si substrate. It will be understood by one of ordinary skill in the art that the exemplary methods described herein are not limited for use with InAlN/GaN HEMT devices on a Si substrate, but may be applicable to other known GaN-on-Si HEMT devices.

[0028] Referring now to FIG. 1, an exemplary method of fabricating a semiconductor device, such as an InAlN/GaN HEMT device on a Si substrate, in accordance with an embodiment of the invention, is depicted. Details of method 100 are set forth below with respect to the elements of semiconductor device 200 (FIGS. 2A-2B), which is discussed further below. Generally, the method, such as method 100, includes one or more steps including depositing a metal stack on the semiconductor layer surface having an epitaxial layer over a substrate; subjecting the semiconductor layer surface to an RTA system for ohmic contact annealing in FG; and subjecting the semiconductor layer surface to the RTA system for ohmic contact annealing in N.sub.2. Additionally, or optionally, no passivation process is applied to device 200.

[0029] In step 110, an epitaxial layer is deposited over a substrate to form a semiconductor layer surface. In an example, as best illustrated in FIGS. 2 and 3A-3D, epitaxial layer 226 is deposited over substrate 202 to form semiconductor layer surface 222. In an exemplary embodiment, substrate 202 comprises Si. Additionally, or optionally, epitaxial layer 226 is deposited over substrate 202 using chemical vapor deposition, such as metal organic chemical vapor deposition (MOCVD). One skilled in the art would understand from the description herein that other deposition, lithography, or thermal growth techniques may be used to form semiconductor layer surface 222.

[0030] Epitaxial layer 226 may comprise multiple layers. In an exemplary embodiment, the multiple layers may include, but are not limited to, a buffer layer and a back barrier layer. The buffer layer, such as buffer layer 204 may comprise a Group III-V semiconductor substrate. In an exemplary embodiment, buffer layer 204 comprises gallium nitride (GaN). A back barrier layer 208 is formed on the buffer layer 204. The back barrier layer 208 may comprise In.sub.yGa.sub.1−yN where y is between 0.05 and 0.2. As used herein, the term “between” when referring to a range shall be interpreted to include at least the endpoints (e.g. “between 0.05-0.2” shall be interpreted to mean “in a range of 0.05-0.2”). In an exemplary embodiment, the back barrier layer comprises In.sub.0.12Ga.sub.0.88N.

[0031] Additionally or optionally, epitaxial layer 226 includes a channel layer, such as channel layer 210 formed on the back barrier layer 208. The channel layer 210 may also comprise GaN. An interlayer 212 may be formed on the channel layer 210. In an exemplary embodiment, the interlayer 212 comprises aluminum nitride (AlN). A lattice-matched barrier layer 214 is formed on the interlayer 212. The lattice-matched barrier layer 214 comprises In.sub.xAl.sub.1-xN where x is between 0 and 0.3. In an exemplary embodiment, the lattice-matched barrier layer 214 comprises In.sub.0.17Al.sub.0.83N. Finally, epitaxial layer 226 comprises a cap layer, such as cap layer 216 formed on the lattice-matched barrier layer 214. In an exemplary embodiment, the cap layer 216 also includes GaN.

[0032] In step 120, the semiconductor layer surface is subjected to an etching process for forming at least one mesa portion. In an example, as shown in FIGS. 3A-3B, semiconductor layer surface 222 is subjected to the etching process for forming at least one mesa portion 224. In an exemplary embodiment, the at least one mesa portion 224 is formed by an etching treatment in which a portion of the epitaxial layer 226 is removed. In a non-limiting example, the at least one mesa portion 224 is formed by removing material from a portion of the buffer layer 204 of the epitaxial layer 226, such that a ledge 206 of the buffer layer 204 is formed. In an exemplary embodiment, the etching process comprises gas plasma etching, as performed by a plasma treatment apparatus configured for ion bombardment to remove material from the semiconductor layer surface 222. In a non-limiting example, the plasma treatment apparatus comprises an inductively coupled plasma (ICP) generator, such as a chlorine (Cl.sub.2)-based ICP generator. One skilled in the art would know from the description herein that other plasma treatment apparatuses may be used, including but not limited to Capacitively Coupled Plasma (CCP), Reactive Ion Etching Plasma (RIE), Magnetically Enhanced Reactive Ion Etch Plasma (MERIE), direct plasma, remote plasma, and Electron Cyclotron Resonance (ECR) plasma generators.

[0033] In step 130, metallization occurs by depositing a metal stack on the semiconductor layer surface. In an example, as best illustrated in FIGS. 2A-2B and 3C, metal stack 218 is deposited on the semiconductor layer surface 222 to form alloyed ohmic contacts. In an exemplary embodiment, metal stack 218 is planarly deposited on cap layer 216 of the semiconductor layer surface 222. Metal stack 218 may comprise titanium (Ti), Al, or a combination thereof. In particular, metal stack 218 comprises Ti, Al, nickel (Ni), gold (Au), or a combination of any two or more thereof.

[0034] In step 140, the semiconductor layer surface is subjected to a rapid thermal annealing (RTA) system for ohmic contact annealing in FG. In an exemplary embodiment, as shown in FIGS. 3A-3D, the semiconductor layer surface 222 is annealed between 700° C. and 900° C. in FG for between 10 and 50 seconds. In an example, the semiconductor layer surface 222 is annealed at 800° C. for 20 seconds in N.sub.2 or 850° C. in FG for 40 seconds. In embodiments, the FG may comprise 5% H.sub.2 and 95% N.sub.2. One skilled in the art would understand that semiconductor layer surface 222 may be subjected to additional or alternative rapid thermal processing (RTP) systems or features thereof, e.g., heating configurations, energy sources, or temperature control methods, without departing from the spirit and scope of the invention.

[0035] In step 150, the semiconductor layer surface is introduced into the RTA system for ohmic contact annealing in N.sub.2. In an exemplary embodiment, as shown in FIGS. 3A-3D, semiconductor layer surface 222 is annealed between 750° C. and 950° C. in N.sub.2 and/or for between 10 and 50 seconds. In an example, the semiconductor layer surface 222 is annealed at 850° C. in FG and for 20 or 40 seconds. Still further, in an exemplary embodiment, step 150 occurs after step 140.

[0036] In step 160, the semiconductor layer surface is subjected to an oxygen plasma treatment. In an example, the semiconductor layer surface 222 is subjected to an oxygen plasma treatment, such as for example, for preparing the semiconductor layer surface 222 for step 170. In an exemplary embodiment, step 160 of method 100 may comprise subjecting semiconductor layer surface 222 to a plasma asher, such as the Branson IPC3000 O.sub.2 Asher, as described and manufactured by Allwin21 Corp. of Morgan Hill, Calif. In an exemplary embodiment, the plasma asher is operated at 800 W for 1 min.

[0037] In step 170, a T-shaped metal gate is formed on the semiconductor layer surface. 17. In an exemplary embodiment, as shown in FIGS. 2 and 3A-3D, the T-shaped metal gate 220 is formed on the semiconductor layer surface 222. In an example, the T-shaped metal gate 220 is formed on cap layer 216. Further, the T-shaped metal gate 220 may be formed on the semiconductor layer surface 222 via electron beam lithography (EBL). One skilled in the art would understand from the description herein that various nanofabrication processes and lithography techniques, including but not limited to, optical lithography, interference lithography, X-ray lithography, and nanoimprint lithography may be used to form T-shaped metal gate 220.

[0038] In an exemplary embodiment, the T-shaped metal gate comprises Ni, Au, or a combination thereof. Still further, one skilled in the art would understand from the description herein that the term “T-shaped” may refer generally to a geometry that may be symmetrical or asymmetrical, or more particularly, a geometry with as narrow a foot-width as possible and as broad a head-width as possible for achieving high frequency performance of HEMTs.

[0039] FIG. 1 depicts an exemplary method comprising steps that are performed sequentially in the order recited. However, it should be understood from the description herein that one or more steps may be omitted and/or performed out of the described sequence of the process while still achieving the desired result. Further, additional fabrication steps of semiconductor device 200 described herein (e.g., with respect to the two-step annealing process) may be included within the steps of method 100.

[0040] Referring now to FIGS. 4 and 15, a method of subjecting a semiconductor layer surface to post-metallization annealing is disclosed. Generally, the method, such as method 300, includes one or more steps subjecting the semiconductor layer surface to a first anneal phase and a second anneal phase. Additionally or optionally, method 300 comprises a pre-anneal phase and a post-anneal phase. Details of method 300 are set forth below with respect to the elements of semiconductor device 200 (FIGS. 2A-2B), which is discussed further below.

[0041] In step 310, the semiconductor layer surface is subjected to a pre-anneal phase. The pre-anneal phase may generally be configured to reduce thermal shock from the subsequent annealing steps and/or for improving thermal stability. In an exemplary embodiment, the semiconductor layer surface 222 is subjected to a pre-anneal phase. The pre-anneal phase includes heating semiconductor layer surface 222 to a first temperature for a first predetermined duration. In an example, the first temperature is between 15° C. and 35° C. and the first predetermined duration is between 30 to 90 seconds. In an exemplary embodiment, the semiconductor layer surface 222 is heated at 25° C. for 60 seconds during the pre-anneal phase. Additionally or optionally, the semiconductor layer surface 222 is heated at 25° C. in FG.

[0042] In step 320, the semiconductor layer surface is subjected to a first anneal phase. In an exemplary embodiment, the semiconductor layer surface 222 is subjected to a first anneal phase. The first anneal phase comprises introducing the semiconductor layer surface 222 into the RTA system for ohmic contact annealing in FG. The RTA system may include a ramping rate of 50° C./s. In an exemplary embodiment, semiconductor layer surface 222 is annealed between 700° C. and 900° C. in FG and for between 10 and 50 seconds. More specifically, semiconductor layer surface 222 is annealed at 800° C. for 20 seconds or 850° C. in FG for 40 seconds during the first anneal phase.

[0043] In step 330, the semiconductor layer surface is subjected to a second anneal phase. In an exemplary embodiment, the semiconductor layer surface 222 is subjected to a second anneal phase. The second anneal phase comprises introducing the semiconductor layer surface 222 into the RTA system for ohmic contact annealing in N.sub.2. The RTA system may include a ramping rate of 50° C./s. In an exemplary embodiment, semiconductor layer surface 222 is annealed between 750° C. and 950° C. in N.sub.2 and for between 10 and 50 seconds. More specifically, semiconductor layer surface 222 is annealed at 850° C. in N.sub.2 for 20 or 40 seconds during the second anneal phase.

[0044] In an exemplary embodiment, step 330 occurs after step 320. As will be explained in the example below, FG annealing in step 320 can effectively remove native oxide from the semiconductor layer surface 222 for improving surface properties of the HEMT device. Thus, the FG annealing step 320 leads to increased 2DEG electron density, thereby leading to a decrease in Ohmic sheet resistance (R.sub.sheet). So, in an exemplary embodiment, to offset the increased Ohmic contact resistance (R.sub.C) from FG annealing in step 320, a sequential N.sub.2 annealing step 330 is applied.

[0045] In step 340, the semiconductor layer surface is subjected to a post-anneal phase. In an exemplary embodiment, the semiconductor layer surface 222 is subjected to a post-anneal phase. The post-anneal phase comprises heating to a second temperature. In an exemplary embodiment, the second temperature is between 15° C. and 35° C., and more preferably, at 25° C., during the post-anneal phase. Additionally, or optionally, the semiconductor layer surface 222 is heated at 25° C. in FG.

[0046] FIG. 14 depicts an exemplary method comprising steps that are performed sequentially in the order recited. However, it should be understood from the description herein that one or more steps may be omitted and/or performed out of the described sequence of the process while still achieving the desired result. Further, additional fabrication steps of semiconductor device 200 described herein (e.g., with respect to metallization in method 100) may be included within the steps of method 300.

[0047] Referring now to FIGS. 2A-2B and 3A-3D, an exemplary semiconductor device fabricated in accordance with one or more of the methods of FIGS. 1 and 15 is disclosed. Generally, semiconductor device 200 comprises the semiconductor layer surface 222, the at least one mesa portion 224 formed on semiconductor layer surface 222; the metal stack 218 on the semiconductor layer surface 222; and the T-shaped metal gate 220 on the semiconductor layer surface 222. Additional details of semiconductor device 200 are discussed further below.

[0048] Semiconductor layer surface 222 comprises the epitaxial layer 226 disposed over substrate 202. In an exemplary embodiment, substrate 202 comprises silicon and has a thickness between 2 and 6 inches. Epitaxial layer 226 may comprise multiple layers. The multiple layers include, but are not limited to, a buffer layer, such as buffer layer 204 comprising a Group III-V semiconductor substrate. In an example, buffer layer 204 comprises gallium nitride (GaN) and may have a thickness of between 1 μm and 3 μm. In an exemplary embodiment, buffer layer comprises a 2-μm undoped GaN buffer layer. Epitaxial layer 226 includes a back barrier layer 208 formed on the buffer layer 204. The back barrier layer 208 may comprise In.sub.yGa.sub.1−yN. In an example, back barrier layer 208 comprises In.sub.yGa.sub.1−yN where y is between 0.05 and 0.2. Back barrier layer 208 may have a thickness of between 1 nm and 7 nm. In an exemplary embodiment, back barrier layer 208 comprises a 4-nm In.sub.0.12Ga.sub.0.88N back barrier layer.

[0049] Additionally or optionally, epitaxial layer 226 may include a channel layer, such as channel layer 210 formed on the back barrier layer 208. In an example, channel layer 210 may comprise GaN. Channel layer 210 may have a thickness of between 10 nm and 20 nm. In an exemplary embodiment, channel layer 210 comprises a 15-nm GaN channel layer. An interlayer 212 may be formed on the channel layer 210. In an example, the interlayer 212 comprises aluminum nitride (AlN) and has a thickness of between 0.1 nm and 2.1 nm. In an exemplary embodiment, interlayer 212 comprises a 1-nm AlN interlayer. A lattice-matched barrier layer 214 is formed on the interlayer 212. The lattice-matched barrier layer 214 comprises In.sub.xAl.sub.1−xN. In an example, lattice-matched barrier layer 214 comprises In.sub.xAl.sub.1−xN, where x is between 0 and 0.3. Lattice-matched barrier layer 214 has a thickness of between 5 nm and 11 nm. In an exemplary embodiment, the lattice-matched barrier layer 214 comprises 8-nm lattice-matched In.sub.0.17Al.sub.0.83N barrier layer. Finally, epitaxial layer 226 comprises a cap layer, such as cap layer 216 formed on the lattice-matched barrier layer 214. In an example, the cap layer 216 also includes GaN and has a thickness of between 0 nm and 4 nm. In an exemplary embodiment, the cap layer 216 comprises a 2-nm GaN cap layer.

[0050] Further, the metal stack 218 is disposed on the semiconductor layer surface 222. As discussed above, semiconductor layer surface 222 with the metal stack 218 is sequentially annealed in FG and then in N.sub.2, each for a predetermined duration. After the two-step annealing process, the T-shaped metal gate 220 on the semiconductor layer surface 222 is formed by EBL. In particular, semiconductor layer surface 222 is formed, such that device 200 may have one or more of the following characteristics: a source-drain spacing (L.sub.sd) of between 0 and 2 μm, a gate-source spacing (L.sub.gs) between 375 nm and 575 nm, and a gate footprint (L.sub.g) between 30 nm to 70 nm. In an exemplary embodiment, source-drain spacing (L.sub.sd) is 1 μm, gate-source spacing (L.sub.gs) is 475 nm, and gate footprint (L.sub.a) is 50 nm.

[0051] Still further, in an exemplary embodiment, semiconductor device 200 comprises a 50-nm gate length InAlN/GaN HEMT on Si substrate device having improved surface properties. The improved surface properties comprise improvements in at least channel electron density, leakage current, subthreshold swing (SS), noise, or combination thereof. In particular, the improved surface properties comprise one or more of an SS of between 90 and 140 mV/dec, a transconductance (g.sub.m) peak of between 315 and 515 mS/mm, a low draw-induced barrier lowing (DIBL) of 50 and 80 mV/V, and high power gain cutoff frequency (f.sub.max) of between 200 and 340 GHz. In an exemplary embodiment, improved surface properties comprise one or more of an SS of 110 mV/dec, a transconductance (g.sub.m) peak of 415 mS/mm, a low draw-induced barrier lowing (DIBL) of 65 mV/V, and high power gain cutoff frequency (f.sub.max) of 270 GHz.

[0052] As will be discussed in the example below, exemplary InAlN/GaN HEMT devices on Si, as prepared or fabricated by the methods described above, provide improved device performance. Sequential use FG and N.sub.2 annealing steps for post-metallization annealing in InAlN/GaN HEMT devices on Si can avoid unintentional oxidation, decrease leakage current, and reduce the traps due to the hydrogen passivation. Notably, the FG annealing effectively removes surface native oxide prior to gate metal deposition.

[0053] Compared with only N.sub.2 annealing, the native oxide is removed by FG annealing (such as in step 140 of method 100 and/or step 320 of method 300), thereby increasing the two-dimensional electron gas (2DEG) electron density as determined by one or more of X-ray photoelectron spectra (XPS), energy band simulation and capacitance-voltage measurement. Transmission line measurement (TLM) showed that N.sub.2 annealing (such as in step 150 of method 100 and/or step 330 of method 300) offers a lower ohmic contact resistance (R.sub.C) while FG annealing (such as in step 140 of method 100 and/or step 320 of method 300) features a lower sheet resistance (R.sub.sheet). Thus, a method or process using FG/N.sub.2 two-step annealing (such as method 100 and/or 300) can utilize both the advantages of FG annealing and N.sub.2 annealing. Such advantages may be indicated by at least one of the following with respect to a 50-nm gate length InAlN/GaN HEMT: a subthreshold swing (SS) of 110 mV/dec, a transconductance (g.sub.m) peak of 415 mS/mm, a record low drain-induced barrier lowing (DIBL) of 65 mV/V, and a record high power gain cutoff frequency (f.sub.max) of 270 GHz.

Example

[0054] The co-inventors assessed the effect of FG and N.sub.2 annealing on the material surface properties of InAlN/GaN HEMTs on Si substrate that is fabricated in accordance with methods 100 or 300, as discussed above. For purposes of the various tests detailed below, the experimental or sample InAlN/GaN HEMTs on Si substrate comprises an epitaxial layer that was grown by metal organic chemical vapor deposition (MOCVD) on a 4-inch Si substrate. The epitaxial layer includes a 2-nm GaN cap layer, an 8-nm lattice-matched In.sub.0.17Al.sub.0.83N barrier layer, a 1-nm AlN interlayer, a 15-nm GaN channel layer, a 4-nm In.sub.0.12Ga.sub.0.88N back barrier layer, and a 2-μm undoped GaN buffer layer.

[0055] The method of fabricating the semiconductor device starts with mesa isolation using Cl2-based inductively coupled plasma etching process. A Ti/Al/Ni/Au metal stack is deposited and annealed to form alloyed ohmic contacts. A two-step annealing is used for the InAlN/GaN HEMTs. In particular, as shown in FIGS. 4 and 15, the semiconductor device is annealed at 850° C. first in FG for 20 s and then at 850° C. in N.sub.2 for 20 s. The ohmic contact rapid thermal annealing (RTA) process is carried out using Solaris 150 Rapid Thermal Processing System with a ramping rate of 50° C./s. The system temperature accuracy and stability are both ±2.5° C. and the temperature variation across the entire chamber is ±2.5° C. Following oxygen plasma treatment, a Ni/Au T-shaped metal gate with a gate width (W.sub.g) of 2×20 μm is fabricated by electron beam lithography. The devices present a source-drain spacing (L.sub.sd) of 1 μm, a gate-source spacing (L.sub.gs) of 475 nm, and a gate footprint (L.sub.g) of 50 nm, respectively. No passivation process is applied on the reported devices. The current-voltage (I-V) and capacitance-voltage (C-V) measurements are taken by using an Agilent B1500A semiconductor parameter analyzer. The resulting semiconductor device (e.g. InAlN/GaN HEMTs on Si substrate) was subjected to various testing as detailed below.

X-Ray Photoelectron Spectra (XPS) Measurement

[0056] To study the effect of FG and N.sub.2 annealing on the material surface properties, the co-inventors conducted XPS of exemplary layers of InAlN/GaN HEMT devices on Si substrate prepared in accordance with embodiments of the invention. Two annealing conditions were adopted: 850° C. for 40 s in N.sub.2; and 850° C. for 40 s in forming gas (FG: 5% H.sub.2 and 95% N.sub.2). FIG. 5 shows the XPS of (a) Ga 3d core-level, (b) N 1s core-level, and (c) O 1s core-level taken from InAlN/GaN heterostructure with 2-nm GaN cap layer after N.sub.2 annealing (top) and FG annealing (bottom), respectively. Relative percentage of fitting components is calculated from the ratio of the area under individual peak and total peak area of all components, as shown in TABLE 1 below, which summarizes fitting parameters for the Ga 3d core-level spectra, N 1s core level spectra, and O 1s (in FIG. 5) for samples after N.sub.2 and FG annealing, respectively. Relative percentage of fitting components is calculated from the ratio of the area under individual peak and total peak area of all components.

TABLE-US-00001 TABLE 1 Ga 3d N 1s O 1s Sample parameter Ga—O Ga—N Ga—Ga Ga—N Ga-LMM1 Ga-LMM2 OH Ga—O N.sub.2 Relative (%) 76 18 6 25 61 14 45 55 annealing Peak (eV) 19.81 17.91 16.01 397.21 396.21 392.61 531.91 530.91 FG Relative (%) 63 29 8 35 53 12 63 37 annealing Peak (eV) 20.11 18.46 16.41 397.26 396.36 392.76 532.36 531.36

[0057] In graph (a) of FIG. 5, the Ga 3d spectra is resolved into three peaks. The fitting peaks at 19.96±0.15, 18.19±0.27, and 16.21±0.20 eV binding energies are corresponding to Ga—O, Ga—N, and Ga—Ga bonds, respectively. See S. Yang, et. al., cited above; Mishra, S. K. T C, et. al., “Pit assisted oxygen chemisorption on GaN surfaces,” Physical Chemistry Chemical Physics, vol. 17, pp. 15201-15208, 2015, doi:10.1039/C5CP00540J; and Q. Wang, et. al., “Interface engineering of an AINO/AlGaN/GaN MIS diode induced by PEALD alternate insertion of AlN in Al 2 O 3,” RSC advances, vol. 7, pp. 11745-11751, 2017, doi:10.1039/C6RA27190A. With N.sub.2 annealing, the relative percentage of Ga—O and Ga—N bonds are 76% and 18%, which results in the ratio between Ga—O and Ga—N of 4.2. With FG annealing, the relative percentage of Ga—O and Ga—N bonds are 63% and 29%, resulting in the ratio between Ga—O and Ga—N of 2.2. The decrease of the Ga—O to Ga—N ratio (4.2 vs. 2.2) shows that the native oxide is more effectively reduced after FG annealing.

[0058] In graph (b) of FIG. 5, the N 1s core level spectra with three fitted peaks is shown. The fitting peaks at 397.24±0.02, 396.29±0.07, and 392.69±0.07 eV for Ga—N bond and two components for Ga LMM Auger features (Ga-LMM1 and GaN-LMM2, respectively). See T. Duan, et. al., “Interfacial chemistry and valence band offset between GaN and Al2O3 studied by X-ray photoelectron spectroscopy,” Applied Physics Letters, vol. 102, p. 201604, 2013, doi:https://doi.org/10.1063/1.4807736 and S. Kushvaha, et. al., “Structural, optical and electronic properties of homoepitaxial GaN nanowalls grown on GaN template by laser molecular beam epitaxy,” RSC Advances, vol. 5, pp. 87818-87830, 2015, doi:10.1039/C5RA11361J. The relative percentage of Ga—N for samples with N.sub.2 annealing and FG annealing is 25% and 35%, respectively. Because the number of Ga atoms is fixed, the Ga—N bonds increasing means the Ga—O bonds are decreasing. This is another indication that native oxide is more effectively reduced with FG annealing.

[0059] In graph (c) of FIG. 5, the O 1s spectra have been fitted using two components (Ga—O bonds with fitting peak at 531.14±0.23 eV and OH bonds with fitting peak at 532.14±0.23 eV). See Y.-J. Lin et. al., “Investigation of surface treatments for nonalloyed ohmic contact formation in Ti/AI contacts to n-type GaN,” Applied Physics Letters, vol. 77, pp. 3986-3988, 2000, doi:https://doi.org/10.1063/1.1332827 and P. Song, et. al., “Self-consistent growth of single-crystalline (201) β-Ga 2 O 3 nanowires using a flexible GaN seed nanocrystal,” CrystEngComm, vol. 19, pp. 625-631, 2017, doi:10.1039/C6CE02319C. The relative percentages of Ga—O bonds are 55% (N.sub.2 annealing) and 37% (FG annealing), which is another indication of the decreased Ga—O bonds with FG annealing. Therefore, the removal of native oxide using FG annealing is confirmed as being relatively more effective from these XPS measurement results.

[0060] A schematic of the FG annealing effect is shown in FIG. 6A. As illustrated in schematic (a) of FIG. 6A, because the semiconductor material is exposed to the air, a native oxide layer (GaO.sub.x) is formed on the surface of GaN cap layer. See S. Yang, et. al, and C. Hinkle, et. al., cited above. A difference between N.sub.2 annealing and FG annealing is the existence of H.sub.2 in the ambient. During the high temperature (850° C.) annealing process, the H atoms in H.sub.2 can combine with the O atom in the native oxide. The O atoms are extracted by the H atoms and thus the O vacancies are formed on the surface. N.sub.2 in the FG can offer nitrogen atoms to fill the O vacancies. After removing native oxide, a new nitridation layer is formed on the surface, as illustrated in schematic (b) of FIG. 6A. Hence, with FG annealing, the number of Ga—O bonds decreases while Ga—N bonds increases.

[0061] The results of the XPS measurements described above suggests that decreased Ga—O bonds are achieved with FG annealing, as indicated by the relative percentages of Ga—O bonds at 55% (N.sub.2 annealing) and 37% (FG annealing). The removal of native oxide using FG annealing is confirmed by the XPS measurement results, thereby meeting the objective of developing effective ways to remove surface native oxide prior to gate metal deposition. The removal of native oxide using FG annealing increases the 2DEG electron density, such as for example, as compared to N.sub.2 annealing.

Electron Density Simulation

[0062] FIGS. 7A and 7B show the valence band edge spectra taken from prepared samples of exemplary InAlN/GaN HEMTs on Si substrate prepared in accordance with embodiments of the invention. The valence band edge spectra shown in FIG. 7A was taken after N.sub.2 annealing and the valence band edge spectra shown in FIG. 7B was taken after FG annealing. The position of valence band maximum (VBM) is determined from the extrapolation of the solid lines 1000 in FIGS. 7A and 7B.

[0063] It turns out that VBM energy (E.sub.v) lies at 2.11 (N.sub.2 annealing) and 2.50 eV (FG annealing) below surface Fermi energy level (E.sub.f). That means that the values of (E.sub.f-E.sub.v) are 2.11 (N.sub.2 annealing) and 2.50 eV (FG annealing). Hence, the VBM positions can be obtained, confirming that E.sub.f at the material surface is lifted up with FG annealing. The lifted E.sub.f of GaN surface is believed to come from the removal of native oxide and the new nitridation layer formation.

[0064] In GaN/InAlN/GaN heterostructure, the surface donor state is treated as the source of the two-dimensional electron gas (2DEG) electrons. The lifted E.sub.f on the surface means more surface electrons, which can be transferred to the 2DEG channel via the barrier electrical field, leading to the increased 2DEG electron density.

[0065] The increased 2DEG electron density is beneficial for the improvement of the drain current and power density in GaN HEMTs, such as the exemplary InAlN/GaN HEMTs on Si substrate prepared in accordance with embodiments of the invention. To obtain the detailed 2DEG electron density, the energy band structure can be simulated using the self-consistent Poisson-Schrodinger equations.

[0066] FIGS. 7C and 7D show the simulated energy band structure and electron concentration distribution as a function of distance (z) from the material surface for both samples. The (E.sub.f-E.sub.v) of 2.11 and 2.50 eV (obtained from valence band edge spectra) are used for the energy band simulation. Considering the GaN band gap of 3.4 eV, E.sub.c-E.sub.f (E.sub.c is the conductance energy minimum) of 1.29 and 0.9 eV are obtained. Hence, the surface barrier height (φ.sub.b, here φ.sub.b=E.sub.c−E.sub.f) can be determined to be 1.29 (N.sub.2 annealing) and 0.9 eV (FG annealing), respectively. The reduction in surface barrier height can result in the increase of 2DEG density.

[0067] As shown in FIGS. 7C and 7D, the higher peak of the electron concentration (n) presents the increased 2DEG electron density. Here the 2DEG electron density (neo) can be extracted from the energy band simulation. The neo of a sample of the exemplary InAlN/GaN HEMTs on Si substrate prepared in accordance with embodiments of the invention, and is subjected to an FG annealing step is 1.91×10.sup.13 cm.sup.−2, which corresponds to a 10% percent increase as compared to that of the sample with N.sub.2 annealing (1.75×10.sup.13 cm.sup.−2). Therefore, FG annealing can effectively decrease the surface barrier height and increase 2DEG electrons in InAlN/GaN heterostructure, such as that found in the exemplary InAlN/GaN HEMTs on Si substrate prepared in accordance with embodiments of the invention.

Capacitance-Voltage (C-V) Measurements

[0068] To assess the influence of trap electrons, the capacitance-voltage measurement with a frequency of 1 MHz is performed as shown in FIG. 8A. The circular Schottky diodes are fabricated for the C-V measurement and the device schematic is shown in the insert of FIG. 8B. During the ohmic contact annealing steps (as described in methods 100 and/or 300 above), N.sub.2 annealing is applied on a sample of the exemplary InAlN/GaN HEMTs on Si substrate prepared in accordance with embodiments of the invention, and FG annealing is applied on another sample. The measured capacitance (C) under voltage of 0 V increases from 0.879 (C.sub.N2, with N.sub.2 annealing) to 0.976 μF/cm.sup.2 (C.sub.FG, with FG annealing). For the sample with N.sub.2 annealing, the native oxide can introduce an oxide capacitance. The oxide capacitance (C.sub.ox) is in series with the barrier capacitance (C.sub.b), resulting in 1/C.sub.N2=1/C.sub.ox+1/C.sub.b. The removed native oxide with FG annealing leads to C.sub.FG, with the value equal to C.sub.b. Hence, the introduced C.sub.ox can decrease the total capacitance. The 2DEG electron density can be calculated using the integration of capacitance-voltage curves and is shown in the equation below, where e is the electron charge, and A is the schottky contact area:

[00001]$n_{2d}=\frac{1}{eA}{\int }_{V_T}^{V}CdV$

[0069] FIG. 8A shows the calculated n.sub.2d as a function of voltage. At the voltage of 0 V, the 2DEG electron density are 1.82×10.sup.13 (N.sub.2) and 2.15×10.sup.13 cm.sup.−2 (FG), respectively. The increased neo with FG annealing is consistent with the results from energy band simulations. Here, both of the neo calculated with C-V curves are higher than those determined from the simulated energy bands. Although the high frequency of 1 MHz has been used during capacitance measurement, the influence of trap electrons cannot be neglected. The trap electrons will contribute to the 2DEG electrons in the capacitance integration calculation method, leading to the increased calculated n.sub.2D.

[0070] The electron concentration distribution versus the distance (z) from the material surface can also be calculated using the measured C-V curves, as calculated by the following equation below, where ε is the dielectric constant of the barrier layer:

[00002]$n=-\frac{2}{{e\epsilon A}^2}.Math.\frac{1}{d\left(1/C^2\right)/\mathrm{dV}}$

[0071] As shown in FIG. 8B, the sample with FG annealing shows a rapid decrease with z. This decrease means that most of the 2DEG electrons are confined in the potential well and a thinner channel layer is formed with FG annealing. A thinner channel is easier to be modulated by the gate voltage. Hence a stronger electron confinement can effectively improve several properties, including but not limited to, the gate control capacity, which is beneficial for decreasing the leakage current, improving I.sub.on/I.sub.off current ratio, reducing subthreshold swing (SS), and suppressing the short-channel effect in GaN HEMT devices.

[0072] In addition, to confirm the variation of 2DEG the electron system, Hall measurement (not shown) is carried out on the InAlN/GaN heterostructure with N.sub.2 and FG annealing, respectively. The results show that n.sub.2d increases from 1.60×10.sup.13 cm.sup.−2 (N.sub.2 annealing) to 1.94×10.sup.13 cm.sup.−2 (FG annealing). Due to the improved surface properties, the 2DEG electron mobility (μ.sub.2d) is also enhanced from 1242 cm.sup.2/V.Math.s (N.sub.2 annealing) to 1358 cm.sup.2/V.Math.s (FG annealing), presenting a significant influence of annealing ambient on the InAlN/GaN HEMT device characteristics.

Ohmic Contact Resistance

[0073] FIGS. 9A and 9B show the Ohmic contact resistance (R.sub.C) and sheet resistance (R.sub.sheet) for three types of annealing conditions obtained using six sets of TLM patterns. The three types of annealing conditions are: N.sub.2 annealing at 850° C. for 40 seconds; FG annealing at 850° C. for 40 seconds; and FG/N.sub.2 annealing at 800° C. for 20 seconds in FG and 850° C. in N.sub.2 for 20 seconds. The average values of R.sub.C are 0.43 Ω.Math.mm (N.sub.2 annealing), 0.92 Ω.Math.mm (FG annealing), and 0.49 Ω.Math.mm (FG/N.sub.2 annealing), respectively. The average values of R.sub.sheet are 361Ω/□ (ohms per square)(N.sub.2 annealing), 269Ω/□ (FG annealing), and 288Ω/□ (FG/N.sub.2 annealing), respectively.

[0074] N.sub.2 annealing shows the lowest R.sub.C and highest R.sub.sheet, and FG annealing presents the opposite behavior (i.e., highest R.sub.C and lowest R.sub.sheet). As discussed above, FG annealing can effectively remove the native oxide and increase the 2DEG electron density, leading to the decrease of R.sub.sheet. However, the increased R.sub.C from FG annealing can degrade the device performance. In order to benefit from the good material property due to FG annealing and the low R.sub.C due to N.sub.2 annealing, a FG/N.sub.2 two-step annealing process is applied and an improved device performance is obtained. Namely, the two-step annealing process in FG and N.sub.2 optimizes contact metal stack for source and drain contact, as both R.sub.C and R.sub.sheet are reduced, thereby minimizing total resistance and enhancing RF performance. This is consistent with the exemplary methods 100 and 300 including an FG/N.sub.2 two-step annealing process to fabricate an exemplary InAlN/GaN HEMT on Si substrate device in accordance with embodiments of the invention.

Device Performance Assessment

[0075] FIG. 10A shows the output characteristic of an exemplary InAlN/GaN HEMT on Si substrate device in accordance with embodiments of the invention. In particular, FIG. 10A shows the output characteristic of a 50-nm gate length InAlN/GaN HEMT with FG/N.sub.2 annealing. FIG. 10B shows the transfer and gate current characteristics in semi-log scale at V.sub.ds of 10 V and 3 V, respectively. At V.sub.ds=10 V, I.sub.on/I.sub.off ratio of ˜10.sup.6 and an SS of 110 mV/dec are observed. The DIBL of 65 mV/V is extracted at I.sub.d=10 mA/mm between V.sub.ds=10 V and V.sub.ds=3V. According to prior art, this is the lowest value among all GaN HEMTs on Si substrate. The breakdown voltage (BV) is 20 V as determined at I.sub.d=1 mA/mm when V.sub.gs is fixed at −8 V. FIG. 10C shows the extracted extrinsic transconductance (g.sub.m) at V.sub.ds of 10 V and a g.sub.m peak (g.sub.m,peak) of 415 mS/mm.

[0076] The RF measurement is taken with Anritsu MS4647B vector network analyzer configured to operate from 1 to 65 GHz. The network analyzer is calibrated using Line Reflect Match (LRM) calibration. On-wafer open and short structures are used to eliminate the effects of parasitic elements. After de-embedding, the current gain (|h.sub.21|.sup.2) and unilateral gain (U) as a function of frequency at V.sub.ds=10 V, V.sub.gs=−3 V are plotted in FIG. 10D. A f.sub.T/f.sub.max of 125/270 GHz is extracted using extrapolation of |h.sub.21|.sup.2 and U with a −20 dB/dec slope, resulting in f.sub.T.Math.L.sub.g of 6.25 GHz.Math.μm.

[0077] FIG. 11 shows the comparison of f.sub.T/f.sub.max of an exemplary InAlN/GaN HEMTs on Si substrate in accordance with embodiments of the invention with those from alternative or reported GaN HEMTs on Si substrate. As shown in FIG. 11, exemplary InAlN/GaN HEMTs on Si substrate prepared with an FG annealing step, as described herein, present the highest f.sub.max among the reported GaN HEMTs on Si. In an exemplary embodiment, exemplary InAlN/GaN HEMTs on Si substrate exhibit an f.sub.T of 215 GHz and/or an f.sub.max of 270 GHz.

[0078] Thus, the improved surface characteristic and 2DEG electron density with FG annealing are demonstrated by the above-described tests and results. With the developed FG/N.sub.2 ohmic contact annealing technology, the 50-nm gate length InAlN/GaN HEMT on Si exhibits an average SS of 110 mV/dec, a record low DIBL of 65 mV/V, a g.sub.m,peak of 415 mS/mm, and a record high f.sub.max of 270 GHz.

[0079] This fabrication technology for GaN HEMTs on Si yields excellent RF characteristics, which indicates the great application potential of GaN-on-Si for products, including but not limited to millimeter wave power amplifiers. Further, GaN HEMTs, such as the exemplary InAlN/GaN HEMTs on Si substrate prepared in accordance with embodiments of the invention, are excellent candidates for enhancing 5G wireless applications due to the high frequency and high power capabilities. Still further, GaN HEMTs, such as the exemplary InAlN/GaN HEMTs on Si substrate prepared in accordance with embodiments of the invention, are also compatible with complementary metal-oxide-semiconductor (COMS) technology and provide more cost effective solutions compared to HEMTs on SiC counterparts.

[0080] Referring now to FIGS. 6B, 12, and 13A-13C, additional tests of device performance is assessed. As shown in FIG. 6B, step 160 of method 100 may comprise subjecting semiconductor layer surface 222 to an oxygen plasma treatment, using a plasma asher, such as the Branson IPC3000 O.sub.2 Asher, as described and manufactured by Allwin21 Corp. of Morgan Hill, Calif. In an exemplary embodiment, the plasma asher is operated at 800 W for 1 min).

[0081] Similar to the device performance assessment discussed above with respect to FIGS. 10A-10D, graph (a) of FIG. 12 shows the output characteristic of an exemplary InAlN/GaN HEMTs on Si substrate in accordance with embodiments including the Asher surface treatment. In particular, graph (a) of FIG. 12 shows the output characteristic of a 50-nm gate length InAlN/GaN HEMT subjected to the following conditions: N.sub.2 annealing+Asher; FG annealing+Asher; and FG/N.sub.2 annealing+Asher.

[0082] Graph (b) of FIG. 12 shows the transfer and gate current characteristics in semi-log scale at V.sub.ds of 10 V. At V.sub.ds=10 V, I.sub.on/I.sub.off ratio of ˜10.sup.6.

[0083] Graph (c) of FIG. 12 shows the transfer curves in linear scale for the exemplary sample(s) of 50-nm gate length InAlN/GaN HEMT subjected to the three conditions, respectively. The exemplary sample transistor that was treated with FG annealing shows the lowest saturation current due to its high contact resistance. The exemplary sample transistor treated with the inventive FG/N.sub.2 annealing shows the highest saturation current due to its higher gate capacitance.

[0084] Graph (d) of FIG. 12 shows the extracted extrinsic transconductance (g.sub.m) at V.sub.ds of 10 V and a g.sub.m peak (g.sub.m,peak) of over 400 mS/mm for samples subjected to the following conditions: FG annealing+Asher and FG/N.sub.2 annealing+Asher. The extracted extrinsic transconductance (g.sub.m) at V.sub.ds of 10 V and a g.sub.m peak (g.sub.m,peak) of under 400 mS/mm is shown for samples subjected to N.sub.2 annealing+Asher.

[0085] Turning to FIGS. 13A-13C, the RF measurement is taken with Anritsu MS4647B vector network analyzer configured to operate from 1 to 65 GHz. The network analyzer is calibrated using Line Reflect Match (LRM) calibration. On-wafer open and short structures are used to eliminate the effects of parasitic elements. After de-embedding, the current gain (|h.sub.21|.sup.2) and unilateral gain (U) as a function of frequency at V.sub.ds=10 V, V.sub.gs=−3 V are plotted in FIGS. 13A-13C. For N.sub.2 annealing+Asher, as shown in FIG. 13A, a f.sub.T/f.sub.max of 115/205 GHz is extracted using extrapolation of |h.sub.21|.sup.2 and U with a −22.5 dB/dec slope. For FG annealing+Asher, as shown in FIG. 13B, a f.sub.T/f.sub.max of 120/210 GHz is extracted using extrapolation of |h.sub.21|.sup.2 and U with a −20 dB/dec slope. For FG/N.sub.2 annealing+Asher, as shown in FIG. 13C, a f.sub.T/f.sub.max of 125/270 GHz is extracted using extrapolation of |h.sub.21|.sup.2 and U with a −24 dB/dec slope.

[0086] Thus, various aspects of the invention include but are not limited to the following.

[0087] Aspect 1: A method of fabricating a semiconductor device, the method comprising:

[0088] (a) depositing an epitaxial layer over a substrate to form a semiconductor layer surface;

[0089] (b) subjecting the semiconductor layer surface to an etching process for forming at least one mesa portion;

[0090] (c) depositing a metal stack on the semiconductor layer surface;

[0091] (d) subjecting the semiconductor layer surface to a rapid thermal annealing (RTA) system for ohmic contact annealing in forming gas (FG), the FG comprising H2 and N2;

[0092] (e) subjecting the semiconductor layer surface to the RTA system for ohmic contact annealing in nitrogen (N2);

[0093] (f) subjecting the semiconductor layer surface to an oxygen plasma treatment; and

[0094] (g) depositing a T-shaped metal gate on the semiconductor layer surface.

[0095] Aspect 2: The method of Aspect 1, wherein the substrate comprises silicon.

[0096] Aspect 3: The method of Aspect 1 or Aspect 2, wherein the epitaxial layer is deposited over the substrate using metal organic chemical vapor deposition (MOCVP).

[0097] Aspect 4: The method of any one of the foregoing Aspects, wherein the epitaxial layer comprises:

[0098] a buffer layer comprising gallium nitride (GaN);

[0099] a back barrier layer formed on the buffer layer, the back barrier layer comprising InyGa1−yN, wherein y is between 0.05 and 0.2;

[0100] a channel layer formed on the back barrier layer, the channel layer comprising GaN;

[0101] an interlayer formed on the channel layer, the interlayer comprising AlN;

[0102] a lattice-matched barrier layer formed on the interlayer, the lattice-matched barrier layer comprising InxAl1−xN, wherein x is between 0 and 0.3; and

[0103] a cap layer formed on the lattice-matched barrier layer, the cap layer comprising GaN.

[0104] Aspect 5: The method of Aspect 4, wherein the etching treatment removes material from a portion of the epitaxial layer.

[0105] Aspect 6: The method of any one of the foregoing Aspects, comprising performing the etching treatment using an inductively coupled plasma (ICP) generator.

[0106] Aspect 7: The method of any one of the foregoing Aspects, comprising performing the etching treatment using a chlorine (C12)-based ICP generator.

[0107] Aspect 8: The method of Aspect 5, wherein the at least one mesa portion is formed by removing material from a portion of the buffer layer of the epitaxial layer, such that a ledge of the buffer layer is formed.

[0108] Aspect 9: The method of any one of the foregoing Aspects, wherein the metal stack comprises titanium (Ti), Al, or a combination thereof.

[0109] Aspect 10: The method of any one of the foregoing Aspects, wherein the metal stack comprises Ti, Al, nickel (Ni), gold (Au), or combination thereof.

[0110] Aspect 11: The method of any one of the foregoing Aspects, wherein the semiconductor layer surface is annealed between 700° C. and 900° C. in FG.

[0111] Aspect 12: The method of any one of the foregoing Aspects, wherein the semiconductor layer surface is annealed in FG for between 10 and 50 seconds.

[0112] Aspect 13: The method of any one of the foregoing Aspects, wherein the semiconductor layer surface is annealed between 750° C. and 950° C. in N2.

[0113] Aspect 14: The method of any one of the foregoing Aspects, wherein the semiconductor layer surface is annealed in N2 for between 10 and 50 seconds.

[0114] Aspect 15: The method of any one of the foregoing Aspects, wherein step (e) occurs after step (d).

[0115] Aspect 16: The method of any one of the foregoing Aspects, wherein FG comprises 5% of H2 and 95% of N2.

[0116] Aspect 17: The method of any one of the foregoing Aspects, wherein the T-shaped metal gate is formed on the semiconductor layer surface by electron beam lithography.

[0117] Aspect 18: The method of any one of the foregoing Aspects, wherein the T-shaped metal gate comprises Ni, Au, or a combination thereof, with a gate width (Wg) of 2×20 μm.

[0118] Aspect 19: The method of any one of the foregoing Aspects, wherein at least step (d) occurs before step (g).

[0119] Aspect 20: The method of any one of the foregoing Aspects, wherein the semiconductor device comprises a high electron mobility transistor (HEMT).

[0120] Aspect 21: The method of Aspect 20, wherein the semiconductor device comprises a 50-nm gate length InAlN/GaN HEMT on Si having improved surface properties.

[0121] Aspect 22: The method of Aspect 21, wherein the improved surface properties comprises improvements in at least channel electron density, leakage current, subthreshold swing (SS), noise, or combination thereof.

[0122] Aspect 23: The method of Aspect 22, wherein the improved surface properties comprise one or more of an SS of between 90 and 140 mV/dec, a transconductance (gm) peak of between 315 and 515 mS/mm, a low draw-induced barrier lowing (DIBL) of 50 and 80 mV/V, and high power gain cutoff frequency (fmax) of between 200 and 340 GHz.

[0123] Aspect 24: The method of Aspect 23, wherein the improved surface properties comprises one or more of an SS of 110 mV/dec, a transconductance (gm) peak of 415 mS/mm, a low draw-induced barrier lowing (DIBL) of 65 mV/V, and high power gain cutoff frequency (fmax) of 270 GHz.

[0124] Aspect 25: The method of any one of the foregoing Aspects, wherein no passivation process is applied to the semiconductor device.

[0125] Aspect 26. A semiconductor device having improved (radio frequency) RF performance comprising:

[0126] a semiconductor layer surface including an epitaxial layer over a substrate comprising silicon;

[0127] at least one mesa portion formed on the semiconductor layer surface;

[0128] a metal stack on the semiconductor layer surface, the metal stack being sequentially annealed in FG and then in N2, each for a predetermined duration; and a T-shaped metal gate on the semiconductor layer surface.

[0129] Aspect 27: The semiconductor device of Aspect 26, wherein the silicon substrate has a thickness between 2 and 6 inches.

[0130] Aspect 28: The semiconductor device of Aspects 26 or 27, wherein the epitaxial layer comprises:

[0131] a buffer layer comprising a group III-nitride material;

[0132] a back barrier layer formed on the buffer layer, the back barrier layer comprising at least In or Al;

[0133] a channel layer formed on the back barrier layer, the channel layer comprising a group III-nitride material;

[0134] an interlayer formed on the channel layer, the interlayer comprising Al;

[0135] a lattice-matched barrier layer formed on the interlayer, the lattice-matched barrier layer comprising InxAl1-xN; and

[0136] a cap layer formed on the lattice-matched barrier layer, the cap layer comprising a group III-nitride material.

[0137] Aspect 29: The semiconductor device of Aspect 28, wherein the group III-nitride material comprises GaN.

[0138] Aspect 30: The semiconductor device of Aspects 28 or 29, wherein the buffer layer has a thickness of between 1 μm and 3 μm.

[0139] Aspect 31: The semiconductor device of any one of Aspects 28-30, wherein the buffer layer comprises a 2-μm undoped GaN buffer layer.

[0140] Aspect 32: The semiconductor device of any one of Aspects 28-31, wherein the back barrier layer comprises InyGa1-yN and y is between 0.05 and 0.2.

[0141] Aspect 33: The semiconductor device of any one of Aspects 28-32, wherein the back barrier layer has a thickness of between 1 nm and 7 nm.

[0142] Aspect 34: The semiconductor device of any one of Aspects 28-33, wherein the back barrier layer comprises a 4-nm In0.12Ga0.88N back barrier layer.

[0143] Aspect 35: The semiconductor device of any one of Aspects 28-34, wherein the channel layer comprises GaN.

[0144] Aspect 36: The semiconductor device of any one of Aspects 28-35, wherein the channel layer has a thickness of between 10 nm and 20 nm.

[0145] Aspect 37: The semiconductor device of any one of Aspects 28-36, wherein the channel layer comprises a 15-nm GaN channel layer.

[0146] Aspect 38: The semiconductor device of any one of Aspects 28-37, wherein the interlayer comprises aluminum nitride (AlN).

[0147] Aspect 39: The semiconductor device of any one of Aspects 28-38, wherein the interlayer has a thickness of between 0.1 nm and 2.1 nm.

[0148] Aspect 40: The semiconductor device of any one of Aspects 28-39, wherein the interlayer comprises a 1-nm AlN interlayer.

[0149] Aspect 41: The semiconductor device of any one of Aspects 28-40, wherein the lattice-matched barrier layer comprises InxAl1-xN and x is between 0 and 0.3.

[0150] Aspect 42: The semiconductor device of any one of Aspects 28-41, wherein the lattice-matched barrier layer has a thickness of between 5 nm and 11 nm.

[0151] Aspect 43: The semiconductor device of any one of Aspects 28-42, wherein the lattice-matched barrier layer comprising an 8-nm lattice-matched In0.17Al0.83N barrier layer.

[0152] Aspect 44: The semiconductor device of any one of Aspects 28-43, wherein the cap layer comprises GaN.

[0153] Aspect 45: The semiconductor device of any one of Aspects 28-44, wherein the cap layer has a thickness of between 0 nm and 4 nm.

[0154] Aspect 46: The semiconductor device of any one of Aspects 28-45, wherein the cap layer comprises a 2-nm GaN cap layer.

[0155] Aspect 47: The semiconductor device of any one of Aspects 28-46, wherein the semiconductor device includes a source-drain spacing (Lsd) of between 0 and 2 μm.

[0156] Aspect 48: The semiconductor device of any one of Aspects 28-47, wherein the semiconductor device includes a gate-source spacing (Lgs) of between 375 and 575 nm.

[0157] Aspect 49: The semiconductor device of any one of Aspects 28-48, wherein the semiconductor device has a gate footprint (Lg) of between 30 and 70 nm.

[0158] Aspect 50. A method of subjecting a semiconductor layer surface to post-metallization annealing, the method comprising:

[0159] (a) subjecting the semiconductor layer surface to a pre-anneal phase, the pre-anneal phase comprising heating to a first temperature for a first predetermined duration;

[0160] (b) subjecting the semiconductor layer surface to a first anneal phase, the first anneal phase comprising subjecting the semiconductor layer surface to an RTA system for ohmic contact annealing in FG; and

[0161] (c) subjecting the semiconductor layer surface to a second anneal phase, the second anneal phase comprising subjecting the semiconductor layer surface to the RTA system for ohmic contact annealing in N2;

[0162] (d) subjecting the semiconductor layer surface to a post-anneal phase, the post-anneal phase comprising heating to a second temperature; and

[0163] wherein step (c) occurs after step (b).

[0164] Aspect 51: The method of Aspect 50, wherein the first temperature is between 15° C. and 35° C. and the first predetermined duration is between 30 to 90 seconds.

[0165] Aspect 52: The method of Aspects 50 or 51 wherein the second temperature is between 15° C. and 35° C.

[0166] Aspect 53: The method of any one of Aspects 50-52, wherein step (b) comprises annealing the semiconductor layer surface between 700° C. and 900° C. in FG.

[0167] Aspect 54: The method of any one of Aspects 50-53, wherein step (b) comprises annealing the semiconductor layer surface in FG for between 10 and 50 seconds.

[0168] Aspect 55: The method of any one of Aspects 50-54, wherein step (c) comprises annealing the semiconductor layer surface between 750° C. and 950° C. in N2.

[0169] Aspect 56: The method of any one of Aspects 50-55, wherein step (c) comprises annealing the semiconductor layer surface in N2 for between 10 and 50 seconds.

[0170] Aspect 57: The method of any one of Aspects 50-56, wherein FG comprises 5% of H2 and 95% of N2.

[0171] Aspect 58: The method of any one of Aspects 50-57, wherein step (d) comprises annealing the semiconductor layer surface in FG.

[0172] Although the invention is illustrated and described herein with reference to specific embodiments, the invention is not intended to be limited to the details shown. Rather, various modifications may be made in the details within the scope and range of equivalents of the claims and without departing from the invention.