Capacitive structure

Abstract

The invention relates to a capacitive structure comprising: first and second components, at least one component comprising a plurality of capacitive layers of a dielectric, each layer arranged between electrodes of different polarity, wherein the first and second components are arranged in a stack separated by a stress reducing layer having a supporting structure with an open mesh in which air acts to reduce the transmissibility of cracks through the stress reducing layer.

Claims

1. A capacitive structure comprising: first and second components, at least one component comprising a plurality of capacitive layers of a dielectric, each layer arranged between electrodes of different polarity, wherein the first and second components are arranged in a stack separated by a stress reducing layer having a supporting structure with an open mesh in which air acts to reduce the transmissibility of cracks through the stress reducing layer; wherein each component of the first and second components has a bulk dielectric layer forming an outer layer of the component; and wherein each component of the first and second components has an inner bulk layer adjacent the stress reducing layer.

2. A capacitive structure according to claim 1, comprising terminating caps at opposed ends of the stack, each cap extending the full depth of the stack, wherein at least some of the electrodes contact one of the terminating caps and at least some others of the electrodes contact the other of the terminating caps.

3. A capacitive structure according to claim 1, wherein the supporting structure is formed of a ceramic material.

4. A capacitive structure according to claim 3, wherein the dielectric layer is a ceramic material.

5. A capacitive structure according to claim 1, wherein the ceramic material of the supporting structure is formed of a ceramic material which is the same as a ceramic material of the dielectric.

6. A capacitive structure according to claim 5, wherein the ceramic material is an X7R dielectric material.

7. A capacitive structure according to claim 5, having a depth of between 1.6 mm and 4 mm.

8. A capacitive structure according to claim 1, wherein the first and second components have the same depth.

9. A capacitive structure according to claim 1, wherein each capacitive layer has a thickness of between 10 m and 100 m.

10. A capacitive structure according to claim 1, which has a maximum voltage of 500V and a capacitive value of 1 F.

11. A capacitive structure according to claim 10, having a width between 3.2 mm and 20.5 mm, and a length between 1.6 mm and 15.5 mm.

12. A capacitive structure according to claim 1, wherein both of the first and second components comprise a plurality of capacitive layers of dielectric, each layer arranged between electrodes of different polarity, whereby the capacitive structure forms a capacitor.

13. A capacitive structure according to claim 1, wherein the first component comprises a plurality of capacitive layers of a dielectric, each layer arranged between electrodes of different polarity, and wherein the second component has a varistor or inductive characteristic.

14. A capacitive structure according to claim 1, comprising at least one further component, separated from an adjacent one of the first and second components by a further stress reducing layer.

15. A method of making a capacitive structure comprising: forming a first electrical component comprising a plurality of capacitive layers of a dielectric, each layer arranged between electrodes of differing polarities; forming a second electrical component: providing a stress reducing layer between the first and second electrical components to form a stack, the stress reducing layer having a supporting structure with an open mesh in which air acts to reduce the transmissibility of cracks through the stress reducing layer; providing each electrical component of the first and second electrical components with a bulk dielectric layer forming an outer layer of the electrical component; and providing each electrical component of the first and second electrical components with an inner bulk layer adjacent the stress reducing layer.

16. A method according to claim 15, wherein the second electrical component comprises a plurality of capacitive layers of a dielectric, each layer arranged between electrodes of different polarities.

17. A method according to claim 15, wherein the step of providing the stress reducing layer comprises forming a blended layer of an organic particulate material and a dielectric material between the first and second electrical components and sintering the structure so as to remove the organic material thereby leaving the open mesh.

18. A method according to claim 17, wherein the organic particulate material comprises carbon.

19. A method according to claim 15, wherein each of the plurality of capacitive layers is formed by screen printing a layer of ceramic ink and allowing to dry before a subsequent capacitive layer is formed.

20. A method according to claim 15, wherein the first and second electrical components are formed in a tape process.

21. A layered structure comprising: first and second components, at least one component comprising a plurality of layers of a dielectric, each layer arranged between electrodes, wherein the first and second components are arranged in a stack separated by a stress reducing layer having a supporting structure with an open mesh in which air acts to reduce the transmissability of cracks through the stress reducing layer; wherein each component has a bulk dielectric layer forming an outer layer of the component; and wherein each component has an inner bulk layer adjacent the stress reducing layer.

22. A layered structure according to claim 21 wherein each of the first and second components is selected from a capacitive component, a varistor component and an inductive component.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) For a better understanding of the present invention and to show how the same may be carried into effect, reference will now be made by way of example, to the accompanying drawings in which:

(2) FIG. 1 illustrates a section through a known capacitive structure;

(3) FIG. 2 illustrates a section through a structure in accordance with one embodiment of the present invention;

(4) FIGS. 3 and 4 are SEM images showing the stress reducing layer having a supporting structure with an open mesh in two different magnifications;

(5) FIG. 5 is a schematic diagram of the external configuration of a capacitive part;

(6) FIG. 6 is a graph showing data for designing a capacitor;

(7) FIGS. 7 and 8 are alternate sectional capacitor designs.

(8) FIG. 2 illustrates a capacitive structure in accordance with one embodiment of the invention. The capacitor comprises ceramic capacitive layers 12a, 12b, etc., formed between pairs of electrodes 13a, 13b, 13c, etc. In this respect, the structure is somewhat similar to the structure shown in FIG. 1, and the principles of operation as a capacitor are the same. Of significant difference however is the fact that the capacitive structure of FIG. 2 comprises upper and lower components 14, 16, separated by a stress reducing layer having a supporting structure with an open mesh 18. The upper and lower parts 14, 16 are held in a common capacitive structure by end caps 15a, 15b, formed for example, of electroplated silver. If necessary, to make up the required depth of the capacitor, outer bulk layers 12e, 12f can be provided. Each component can also have an inner bulk layer 12g, 12h adjacent the stress reducing layer having a supporting structure with an open mesh 18. The stress reducing layer having a supporting structure with an open mesh 18 performs two important functions. It has sufficient physical structure to hold together the upper and lower parts, but also is sufficiently loose grained (mesh) that it can trap a sufficient quantity of air (open) to prevent cracks being transmitted and causing failure (stress reducing). Therefore, the dividing layer 18 may also be properly be referred as a stress reducing open mesh layer. This is described in more detail in the following, but it has been determined that a layer with a sponge construction is the most effective. FIG. 3 is an SEM of the stress reducing layer having a supporting structure with an open mesh 18 itself, showing how it differs from the ceramic layer on either side of it. FIG. 4 is a lower scale SEM which shows the stress reducing layer having a supporting structure with an open mesh 18 and also illustrates the ceramic layers 12a, 12b and electrodes 13a, 13b, etc.

DETAILED DESCRIPTION OF THE CERTAIN INVENTIVE EMBODIMENTS

(9) Although the precise mechanism for reducing failure due to piezoelectric/electrostrictive cracks is not completely certain, it appears that stress is absorbed by the stress reducing layer having a supporting structure with an open mesh 18 (as illustrated or shown in FIGS. 2, 3, 4, 7, and 8) so that piezoelectric stress cracks do not form through the structure such as to cause failure. Thus, the capacitive structure can withstand significantly higher voltages and deliver a higher capacitive value, without failure, than has hitherto been possible. In particular, a 500V, 1 F capacitor is now enabled in a single package, of 2220 chip size.

(10) According to one method of manufacture, the capacitive structure is formed as a sequence of layers. That is, a first layer of ceramic is put down onto a base substrate (which might involve a number of layering steps by screen printing, for example), allowed to dry, an electrode layer is formed, followed by a subsequent ceramic layer, etc. When sufficient ceramic and electrode layers have been put down to form the lower component 16 of a capacitor structure, a blended layer is put down which comprises, in one embodiment, a blend of carbon and the base ceramic material. The upper component of the capacitive structure can then be formed in a similar manner to the lower component. In a sintering step which dries the layers, the carbon is burnt off leaving a weakened ceramic spongy stress reducing layer having a supporting structure with an open mesh 18. The resulting piece can then be cut into capacitive parts of the required dimensions.

(11) The success of the above structure and technique in delivering a high voltage, high capacitance value structure which is resistant to failures is counterintuitive in that it provides a weaker layer at the centre of the capacitive structure. Nevertheless, the findings are impressive as set out in more detail later.

(12) In seeking to develop a high voltage high capacitive failure-resistant structure, the inventors developed a useful understanding of piezoelectric/electrostrictive stress cracks which are formed when a high voltage is applied to a susceptible ceramic capacitor. The ceramic material is put under stress by the application of high voltage and a characteristic crack is formed, generally through the centre of the component. If the cracked component continues to be used with applied voltage, then an electrical failure will result, where the crack crosses opposing electrodes. This results in a short circuit condition arising as metal from the electrodes, for example, migrates through the crack and thereby allows an electrical short circuit.

(13) If a part is susceptible to piezoelectric/electrostrictive cracking, then the crack can be generated at any stage of component use, i.e. at initial switch on, or during subsequent switching operations. Consequently, cracked components may not be detected at equipment test stage, but only later as field failures. Similarly, susceptible batches may be tested several times, generating widely different results, as crack formation is not always reproducible. It is thus a frustrating and hard to handle failure mechanism.

(14) Prior to development of the present invention, the effect of piezoelectric/electrostrictive cracking as a failure mechanism was not sufficiently well understood to be incorporated into the normal design rules for designing multilayer ceramic capacitors. These rules sought to apply a minimum layer thickness between electrodes, expressed in volts per micron. This rule was thought to be applicable to a wide range of chip sizes and voltages, and generally speaking parts with higher capacitance values and lower working voltages could be manufactured by increasing the chip thickness to accommodate the increased specification. Chip thickness could be increased by increasing the thickness d.sub.f of the capacitive layers, increasing the number of electrodes (and thus the number of layers), or increasing the depth of the bulk layers.

(15) It should also be understood that in addition to considering these rules, there are practical limitations imposed by the manufacture of capacitors, either by manufacturing techniques or by cost implications. For example, there is a maximum chip size that can sensibly be automatically manufactured. Attempts by the applicant to manufacture a 500V 1 F capacitor within that maximum 2220 chip size, using the conventional V/u rules resulted in a part that failed due to piezoelectric/electrostrictive cracking.

(16) Attempts were made to increase the thickness of the ceramic layers (d.sub.f), in line with what was considered standard practice to reduce the V/u rating. The inventors noticed however that parts re-made with thicker layers still suffered from similar failure levels due to piezoelectric/electrostrictive cracking. Further increases in layer thicknesses offered no improvement.

(17) Following analysis, the inventors determined that failures due to piezoelectric/electrostrictive cracking were related to chip dimensions. Consider FIG. 5, which shows a capacitor having a depth d, with w and length 1. The inventors determined that large, thicker chips (large 1, large w, large d) were significantly more prone to failure than small thinner chips (small w, 1, and d), or even large thinner chips (large w, 1; small d). The inventors also noticed that the thicker the layer between electrodes (d.sub.f) the more likely it was to induce piezoelectric/electrostrictive cracking.

(18) Thus, the conventional rules would not permit the construction of a capacitive structure for large capacitance, high voltage components which were not prone to failure by cracking.

(19) FIG. 6 illustrates a graph of maximum volts per micron (V/u) versus chip thickness in millimeters for a 2220 chip. As shown in the right-hand side of the graph, different geometrical icons represent different layer thicknesses. In order to form different overall chip thicknesses (as on the X scale of the graph), the number of electrodes, and thus the number of layers was adjusted.

(20) Consider the data for a layer thickness between 30-40 microns, at a chip thickness of around 2.7 mm. At this point, the maximum volt per micron is around 12 using conventional design rules. Similarly, consider a structure with a layer thickness of between 30-40 microns, and a chip thickness of around 3.4 mm. The maximum volt per micron is around 11.

(21) Consider now the two points marked with a star, labelled TP1 (Test Part 1) and TP2 (Test Part 2). Note that the maximum volts per micron for TP1 are around 17-18 (significantly higher than its conventional counterpart). The maximum volt per micron for TP2 is around 14, significantly greater than 12. In both cases, the part performs more like chips at least one millimeter thinner according to the conventional design strategy. More specific information on the test parts is given in the following.

(22) The test parts (2 batches TP1/TP2) had the following construction based on fired measurements:

(23) a) Ceramic layers 210/250 microns

(24) b) 34 electrode and ceramic layers of 31/37 microns

(25) c) Ceramic layers of 62/74 microns

(26) d) 12 sponge layer prints (approx 50 microns)

(27) e) Ceramic layers of 62/74 microns

(28) f) 34 electrode and ceramic layers of 31/37 microns

(29) g) Ceramic layers 210/250 microns

(30) 1. Dimensions of Chip

(31) TABLE-US-00001 Length Width Thickness Experimental parts TP1/TP2 5.7 mm 5.0 mm 2.6 mm/3.2 mm
2. Thickness of each layer;

(32) Experimental parts green layer (ceramic prior to sintering) thickness 37.5 and 44.5 microns, equates to fired layers of 31 and 37 microns approx.

(33) 3. Overall thickness of chip as above;

(34) thickness of each stacked component of the finished chip was 1.3 mm (TP1) and 1.6 mm (TP2).

(35) 4. Materials;

(36) The base ceramic (dielectric) material has BaTiO.sub.3 as the primary ingredient, and is classified as an X7R material.

(37) The stress reducing layer having a supporting structure with an open mesh 18 as present in the finished product is also made entirely of the base ceramic material (BaTiO.sub.3 for test parts). The layer was made into a sponge by mixing the ceramic ink with carbon which after sintering formed the stress reducing layer having a supporting structure with an open mesh 18.

(38) 5. Blend Percentages

(39) The ceramic sponge ink was made by blending 60% of our black coverplate ink (9.6% carbon) with 40% BaTiO.sub.3 based dielectric ink (65% solids).

(40) This gave an ink containing weight percentages 26% BaTiO.sub.3 based dielectric, 5.8% carbon, 68.2% organic solvents plus binders.

(41) The manufacturing process described above is a screen printing process.

(42) A tape process would also be capable of producing the proposed parts. The tape process involves more stages to replace the screen printing stage, but other than this, the manufacturing processes are essentially the same.

(43) FIG. 7 shows an alternate capacitor design in section. In FIG. 7, each component of the design has two sections, although 4, 6, 8, 10 and more sections are also possible. Sectional or floating electrode patterns are used for higher voltages, allowing voltage to be dropped across each section. There are many variants; according to one prior art variant, a two section screen at rated voltage 1 kV would have 500V across each section. A four section screen at 4 kV would have 1 kV across each section, etc.

(44) FIG. 8 shows a fractional capacitor design which is commonly used at mid voltages to reduce surface flashover.

(45) It will be appreciated that while certain embodiments of the invention have been described, there is no intention to limit the invention to these embodiments as many variants are possible. In particular, although the 500V/1 F/2220 part has been a part which has been particularly elusive in the industry, is readily apparent that the principles of the invention may be applied to parts of different working voltages, different capacitive values and of different dimensions. It is anticipated that the principles described herein will be widely applicable to improve the delivery of many different capacitive structures. For example, the following table gives a range of different parts to which the technique described herein can be applied.

(46) TABLE-US-00002 TABLE I Maximum capacitance values Voltage 1812 2220 3640 5550 8060 100 Vdc 22 uF 33 uF 200/250 Vdc 1.0 uF 2.2 uF 5.6 uF 10 uF 15 uF 500 Vdc 470 nF 1.2 uF 2.7 uF 3.9 uF 6.8 uF 630 Vdc 330 nF 1.0 uF 2.2 uF 3.3 uF 3.9 uF 1 kVdc 180 nF 470 nF 1.0 uF 1.2 uF 1.8 uF 1.2 kVdc 100 nF 220 nF 470 nF 820 nF 1.2 uF 1.5 kVdc 56 nF 150 nF 330 nF 560 nF 680 nF 2 kVdc N/a 100 nF 150 nF 270 nF 470 nF 2.5 kVdc 150 nF 270 nF 3 kVdc 100 nF 220 nF 4 kVdc 68 nF 100 nF

(47) Furthermore, it is anticipated that the principles of the invention can be applied in a scenario where the first and second components are of different base ceramic materials having therefore different properties. Thus, it would be possible to produce a capacitive structure in which a first component had particularly good temperature resistant properties in one range, combined with a second component having particularly good temperature resistant properties in another range. In this way it would be possible to blend the characteristics of different ceramics to achieve a capacitive structure capable of operating over a wider range of variables than is presently possible.

(48) In another variant, a lead is soldered to each termination of the capacitive structure. The structure can then be coated with a conformal coating to protect against environment/voltage.

(49) Furthermore, although the above discussion has focused on the capacitive structure, it is expected that the techniques discussed herein could be usefully extended to varistor and/or inductor structures.