COST-EFFECTIVE METHOD TO FORM A RELIABLE MEMORY DEVICE WITH SELECTIVE SILICIDATION AND RESULTING DEVICE

Abstract

A method of forming a memory device with a dielectric blocking layer and selective silicidation and the resulting device are provided. Embodiments include forming a memory stack on a substrate; forming a conformal insulating layer over sidewalls and an upper surface of the memory stack and the substrate; forming an interpoly dielectric structure adjacent to each sidewall of the insulating layer; forming a conformal polysilicon silicon layer over the insulating layer and interpoly dielectric structures; forming an optical planarization layer over the polysilicon layer; planarizing the optical planarization and polysilicon layers down to the memory stack; forming a dielectric blocking layer over the memory stack and substrate; forming a patterning stack over the dielectric blocking layer, the patterning stack covering a portion of the memory stack; and removing the dielectric blocking, optical planarization, and polysilicon layers on opposite sides of the patterning stack.

Claims

1. A device comprising: a memory stack over a substrate; a conformal insulator layer on sidewalls and on an upper surface of the memory stack and on an upper surface of the substrate; an interpoly dielectric adjacent to sidewalls of the insulating layer; a memory device over the insulator layer and adjacent to interpoly dielectric; a dielectric blocking layer covering the memory device, interpoly dielectric, and a portion of the insulating layer over the upper surface of the memory stack; and a silicide layer under a remaining portion of the insulating layer over the upper surface of the memory stack.

2. The device according to claim 1, wherein the memory stack comprises: a first silicon oxide (SiO.sub.x) layer over the substrate; a first polysilicon layer over the first SiO.sub.x layer; a dielectric layer over the first polysilicon layer; a second polysilicon layer over the oxide layer; a capping layer over a portion of the second polysilicon layer; and the silicide layer over a remaining portion of the second polysilicon layer and adjacent to the capping layer.

3. The device according to claim 1, wherein the dielectric layer comprises SiO.sub.x or a composite layer of SiO.sub.x/silicon nitride (SiN)/SiO.sub.x or SiO.sub.x/silicon oxynitride (SiON)/SiO.sub.x.

4. The device according to claim 1, wherein the capping layer comprises SiO.sub.x, SiN, or a composite layer of SiO.sub.x and SiN combinations.

5. The device according to claim 1, wherein the conformal insulating layer comprises SiO.sub.x, SiN, or a composite layer of SiO.sub.x/SiN/SiO.sub.x or SiOx/SiN.

6. The device according to claim 1, wherein the interpoly dielectric comprises SiO.sub.x, SiN, or a composite layer of SiO.sub.x/SiN/SiO.sub.x or SiO.sub.x/polysilicon/SiO.sub.x.

7. The device according to claim 1, wherein the dielectric blocking layer comprises SiN, SiO.sub.x, SiON, or a composite layer of combinations of any SiN, SiO.sub.x, and SiON layers.

8. A device comprising: a memory stack over a substrate, wherein the memory stack comprises: a first silicon oxide (SiO.sub.x) layer over the substrate; a first polysilicon layer over the first SiO.sub.x layer; a dielectric layer over the first polysilicon layer; a second polysilicon layer over the oxide layer; a capping layer over a portion of the second polysilicon layer; a conformal insulator layer on sidewalls and on an upper surface of the memory stack and on an upper surface of the substrate; an interpoly dielectric adjacent to sidewalls of the insulating layer; a memory device over the insulator layer and adjacent to a interpoly dielectric; a dielectric blocking layer covering the memory device, a interpoly dielectric, and a portion of the insulating layer over the upper surface of the memory stack; and a silicide layer under a remaining portion of the insulating layer over the upper surface of the memory stack

9. The device according to claim 8, wherein the silicide layer remains over a portion of the second polysilicon layer and adjacent to the capping layer.

10. The device according to claim 8, wherein the dielectric layer comprises SiO.sub.x or a composite layer of SiO.sub.x/silicon nitride (SiN)/SiO.sub.x or SiO.sub.x/silicon oxynitride (SiON)/SiO.sub.x.

11. The device according to claim 8, wherein the capping layer comprises SiO.sub.x, SiN, or a composite layer of SiO.sub.x and SiN combinations.

12. The device according to claim 8, wherein the conformal insulating layer comprises SiO.sub.x, SiN, or a composite layer of SiO.sub.x/SiN/SiO.sub.x or SiOx/SiN.

13. The device according to claim 8, wherein the interpoly dielectric comprises SiO.sub.x, SiN, or a composite layer of SiO.sub.x/SiN/SiO.sub.x or SiO.sub.x/polysilicon/SiO.sub.x.

14. The device according to claim 8, wherein the dielectric blocking layer comprises SiN, SiO.sub.x, SiON, or a composite layer of combinations of any SiN, SiO.sub.x, and SiON layers.

15. A device comprising: a pair of memory stacks laterally separated on a substrate; a conformal insulating layer formed on sidewalls and on an upper surface of the laterally separated memory stacks and on an upper surface of the substrate; an interpoly dielectric adjacent to sidewalls of the insulating layer; a memory device over the insulator layer and adjacent to interpoly dielectric; a dielectric blocking layer covering the memory device, interpoly dielectric, and a portion of the insulating layer over the upper surface of the laterally separated memory stacks; and a silicide layer under a remaining portion of the insulating layer over the upper surface of the laterally separated memory stacks.

16. The device according to claim 15, comprising forming each memory stack by: a first silicon oxide (SiO.sub.x) layer over the substrate; a first polysilicon layer over the first SiO.sub.x layer; a dielectric layer over the first polysilicon layer; a second polysilicon layer over the dielectric layer; and a capping layer over the second polysilicon layer.

17. The device according to claim 15, the conformal insulating layer comprising SiO.sub.x, SiN, or a composite layer of SiO.sub.x/SiN/SiO.sub.x or SiOx/SiN.

18. The device according to claim 15, the interpoly dielectric comprising SiO.sub.x, SiN, or a composite layer of SiO.sub.x/SiN/SiO.sub.x or SiO.sub.x/polysilicon/SiO.sub.x.

19. The device according to claim 15, the dielectric blocking layer comprising SiN, SiO.sub.x, SiON, or a composite layer of combinations of any SiN, SiO.sub.x, and SiON layers.

20. The device according to claim 19, wherein the dielectric blocking layer has a thickness of 50 to 1500 angstroms ().

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The present disclosure is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawing and in which like reference numerals refer to similar elements and in which:

[0016] FIGS. 1 through 7 schematically illustrate cross-sectional views of a process flow for forming a memory device with a dielectric blocking layer and selective silicidation, in accordance with an exemplary embodiment.

DETAILED DESCRIPTION

[0017] In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of exemplary embodiments. It should be apparent, however, that exemplary embodiments may be practiced without these specific details or with an equivalent arrangement. In other instances, well-known structures and devices are shown in block diagram form in order to avoid unnecessarily obscuring exemplary embodiments. In addition, unless otherwise indicated, all numbers expressing quantities, ratios, and numerical properties of ingredients, reaction conditions, and so forth used in the specification and claims are to be understood as being modified in all instances by the term about.

[0018] The present disclosure addresses and solves the current problems of interpoly dielectric breakdown and memory device dielectric breakdown due to implantation steps, non-selective silicidation on a memory device causing shorts between the memory device and an adjacent memory stack, and uneven memory device and adjacent memory stack heights attendant upon forming a memory device. The problems are solved, inter alia, by forming a dielectric blocking layer over the memory device and an adjacent portion of an adjacent memory stack.

[0019] Methodology in accordance with embodiments of the present disclosure includes forming a memory stack on a substrate. A conformal insulating layer is formed over sidewalls and an upper surface of the memory stack and the substrate. An interpoly dielectric structure is formed adjacent to each sidewall of the insulating layer, and a conformal polysilicon silicon layer is formed over the insulating layer and interpoly dielectric structures. An optical planarization layer is formed over the polysilicon layer, and the optical planarization and polysilicon layers are planarized down to the memory stack. A dielectric blocking layer is formed over the memory stack and substrate. A patterning stack is formed over the dielectric blocking layer, the patterning stack covering a portion of the memory stack, and the dielectric blocking, optical planarization, and polysilicon layers are removed on opposite sides of the patterning stack.

[0020] Still other aspects, features, and technical effects will be readily apparent to those skilled in this art from the following detailed description, wherein preferred embodiments are shown and described, simply by way of illustration of the best mode contemplated. The disclosure is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.

[0021] FIGS. 1 through 7 schematically illustrate cross-sectional views of a process flow for forming a memory device with a dielectric blocking layer and selective silicidation, in accordance with an exemplary embodiment. Adverting to FIG. 1, a memory stack 101 is formed, e.g., in one or more pairs, on a substrate 103. Each memory stack 101 is formed of a SiO.sub.x layer 105, a polysilicon layer 107, a dielectric layer 109, a polysilicon layer 111, and a capping layer 113. The polysilicon layers 107 and 111 each may be formed, e.g., to a thickness of 500 to 1500 , the dielectric layer 109 may be formed, e.g., of SiO.sub.x or a composite layer of SiO.sub.x/SiN/SiO.sub.x or SiO.sub.x/SiON/SiO.sub.x, and the capping layer 113 may be formed, e.g., of SiO.sub.x, SiN, or a composite layer of SiO.sub.x and SiN combinations, and to a thickness of 20 to 1000 . A conformal insulating layer 115 is then formed, e.g., of SiO.sub.x, SiN, or a composite layer of SiO.sub.x/SiN/SiO.sub.x or SiOx/SiN, over the sidewalls and the upper surface of each memory stack 101 and over the substrate 103. Next, interpoly dielectric structures 117 are formed, e.g., of SiO.sub.x, SiN, or a composite layer of SiO.sub.x/SiN/SiO.sub.x or SiO.sub.x/polysilicon/SiO.sub.x, adjacent to each sidewall of the insulating layer 115. Thereafter, a conformal polysilicon layer 119 is formed, e.g., to a thickness of 700 to 2500 , over the insulating layer 115 and the interpoly dielectric structures 117.

[0022] Adverting to FIG. 2, an optical planarization layer 201 is formed over the polysilicon layer 119. The optical planarization layer 201, the polysilicon layer 119, and the insulating layer 115 are then planarized, e.g., by a blanket etch or a poly chemical mechanical polishing (CMP), down to the memory stack 101, as depicted in FIG. 3. Adverting to FIG. 4, a dielectric blocking layer 401 is formed, e.g., of SiN, SiO.sub.x, SiON, or a composite of combinations of any SiN, SiO.sub.x, and SiON layers, over each memory stack 101 and the substrate 103. The dielectric blocking layer 401 may be formed, e.g., to a thickness of 50 to 1500 .

[0023] Next, patterning stacks 501 are formed, e.g., each to a width of 60 nm to 160 nm, over the dielectric blocking layer 401, each covering a portion of a memory stack 101, respectively, as depicted in FIG. 5. The dielectric blocking layer 401, optical planarization layer 201, and polysilicon layer 119 are then removed on opposite sides of the patterning stacks 501, forming the dielectric blocking layer 401 and defining each memory device 119, as depicted in FIG. 6.

[0024] During subsequent processing (not shown for illustrative convenience), the dielectric blocking layer 401 blocks implantation into the interpoly dielectric structure 117 between a memory device 119 and an adjacent memory stack 101, which improves interpoly dielectric breakdown. The dielectric blocking layer 401 also blocks implantation into the memory device 119, which improves memory device dielectric breakdown within the region 601 of the insulating layer 115. In addition, the dielectric blocking layer 401 ensures that a memory device 119 and an adjacent memory stack 101 have the same height, which provides a uniform electric field between the memory device 119 and the adjacent memory stack 101. Further, the dielectric blocking layer 401 blocks silicidation on the memory device 119 and prevents the subsequently formed silicide layer 113 (shown in FIG. 7) from forming across the entire width of the memory stack 101, thereby preventing shorts between a memory device 119 and an adjacent memory stack 101.

[0025] The embodiments of the present disclosure can achieve several technical effects including forming a cost effective highly reliable memory device with selective silicidation due to the interpoly dielectric breakdown improvement, the memory device short improvement, memory device dielectric breakdown improvement, and the improvement of electric field uniformity between a memory device and an adjacent memory stack. Embodiments of the present disclosure enjoy utility in various microcontroller applications as, for example, industrial (network, motor control, etc.), mobile phones, automotive electronics, chip cards, and consumer applications (gaming, camera, etc.). The present disclosure therefore enjoys industrial applicability in any of various types of semiconductor devices including NVM devices.

[0026] In the preceding description, the present disclosure is described with reference to specifically exemplary embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the present disclosure, as set forth in the claims. The specification and drawings are, accordingly, to be regarded as illustrative and not as restrictive. It is understood that the present disclosure is capable of using various other combinations and embodiments and is capable of any changes or modifications within the scope of the inventive concept as expressed herein.