Method of fabricating an electromechanical structure including at least one mechanical reinforcing pillar

Abstract

The invention provides a method of fabricating an electromechanical structure presenting a first substrate including a layer of monocrystalline material covered in a sacrificial layer that presents a free surface, the structure presenting a mechanical reinforcing pillar in the sacrificial layer, the method including etching a well region in the sacrificial layer to define a mechanical pillar; depositing a first functionalization layer of the first material to at least partially fill the well region and cover the free surface of the sacrificial layer around the well region; depositing a second material different from the first material for terminating the filling of the well region to thereby cover the first functionalization layer around the well region, planarizing the filler layer, the pillar being formed by the superposition of the first material and second material in the well region; and releasing the electromechanical structure by removing at least partially the sacrificial layer.

Claims

1. A method of fabricating an electromechanical structure presenting a first substrate (1) including at least one layer (1) of a monocrystalline material, said at least one layer being covered with a sacrificial layer (2), said sacrificial layer presenting a free surface, said electromechanical structure presenting at least one mechanical reinforcing pillar received in said sacrificial layer, wherein the method comprising: a) making at least one well region (35, 35.sub.1, 35.sub.2) in the sacrificial layer (2) by etching at least in the entire thickness of the sacrificial layer (2), said at least one well region defining said at least one mechanical reinforcing pillar; b) depositing a first functionalization layer (30) of a first functionalization material, relative to which the sacrificial layer is suitable for being etched selectively, and a second functionalization layer (31) of a second functionalization material, wherein said first functionalization material is conductive, and said second functionalization material is insulating, said first functionalization layer (30) filling said at least one well region (35) at least partially and covering the free surface of the sacrificial layer (2) such that said first functionalization layer is localized at least around said at least one well region, said sacrificial layer being suitable for being etched selectively to said first functionalization material and said second functionalization material; b) depositing a filler layer (32) of a filler material different from the first functionalization material and said second functionalization material for terminating the filling of said at least one well region, said filler layer (32) covering the first functionalized layer and said second functionalization layer (30, 31) at least in a part around said at least one well region (35), and planarizing the filler layer (32), such that at least a part of only the filler layer is removed, said at least one mechanical reinforcing pillar being formed and defined by a superposition of at least the first functionalization material or the second functionalization material and also of the filler material in said at least one well region (35).

2. The method according to claim 1, wherein the monocrystalline material is selected from Si, Ge, quartz, or a perovskite.

3. The method according to claim 1, wherein said filler layer is subsequently planarized by using a chemical-mechanical planarization.

4. The method according to claim 1, wherein the first functionalization material is selected from: silicon nitride; doped or polycrystalline Si or a metal.

5. The method according to claim 1, wherein the filler material is selected from: silicon oxide; doped or insulating polycrystalline Si; or a polymer.

6. The method according to claim 1, wherein said first functionalization material, forms a first interconnection level which serves to make an electrical connection between said at least one layer of the monocrystalline material and said first functionalization layer.

7. The method according to claim 6, wherein the sacrificial layer is covered by both the first functionalization layer and the second functionalization layer, together.

8. The method according to claim 1, wherein said second functionalization material is selected from: silicon nitride or insulating polysilicon Si.

9. The method according to claim 1, wherein the filler material of the filler layer is selected to be identical to a material of the sacrificial layer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The invention can be better understood on reading the following description with reference to the accompanying drawings, in which:

(2) FIGS. 1a to 1f show a method of the invention that serves in preferred manner to make two-material reinforcements or pillars, FIG. 1d showing an advantageous variant of the method;

(3) FIGS. 2a to 2d show a variant of the method of the invention in which there are so-called conductive or insulating pillars, and FIGS. 2c1, 2c2, and 2d show an implementation having a second level of interconnection;

(4) FIGS. 3a to 3d show a variant of the method of the invention enabling interconnection levels to be made using planar technology, with FIGS. 3c1 to 3c8 constituting an implementation with a plurality of interconnect levels; and

(5) FIG. 4 shows, by way of example, a pressure sensor made with the method of FIGS. 1a to 1f.

MORE DETAILED DESCRIPTION

(6) FIGS. 1a to 1f show a preferred implementation of the method of the invention, serving to enable insulating pillars to be made from wide trenches (e.g. several tens of m and more precisely 50 m for example). The method starts with a substrate 1 presenting at least one monocrystalline layer 1 (e.g. of monocrystalline Si), coated in a sacrificial layer 2 (e.g. SiO.sub.2). The layer 1 may occupy all of the substrate (thick Si substrate) or only a portion thereof (e.g. the top layer of an SOI substrate or some other type of substrate presenting an etching stop layer). Preferably, the initial substrate is a silicon substrate including a monocrystalline SiGe stop layer (not shown in the figure) and a monocrystalline silicon layer 1. The layer 2 may be an oxide deposited by low pressure chemical vapor deposition (LPCVD) or by plasma-enhanced CVD (PECVD), or it may be made by thermally oxidizing the layer 1. Its thickness may lie in the range 200 nanometers (nm) to 5 m (typically in the range 2 m to 3 m).

(7) A layer 3 of photosensitive resin is exposed to enable one or more zones such as 5.sub.1 to be made in the layer 2 (FIG. 1a), these zones providing recesses for making the reinforcing region(s). The reinforcing regions may be open zones or they may be closed zones, e.g. annular or polygonal, as applies to a pressure sensor.

(8) After removing the resin 3, a functionalization layer 4 is deposited on the layer 2, e.g. a silicon nitride layer having thickness lying for example in the range 10 nm to 500 nm, thereby providing a layer 4.sub.1 on the side walls of the zone(s) 5.sub.1, and a layer 4.sub.2 on the bare face of the substrate 1 (FIG. 1b) (note: 4.sub.1 and 4.sub.2 can be seen in FIGS. 1b and 1e). The nitride may be deposited by chemical vapor deposition, in particular LPCVD or PECVD or by using atomic layer CVD (ALCVD). The layer 4 may also be made of optionally doped polysilicon, or of a metal, or of a metal and semiconductor alloy. It needs to present etching selectivity relative to the sacrificial layer. This layer does not necessarily cover the entire surface of the sacrificial layer (it may be etched locally). It enables insulating or conductive pillars to be made depending on the nature of the material constituting the functionalization layer 4, acting as etching stops for the sacrificial layer and as electrical contacts leading to the mechanical layer 1 when the pillars are conductive.

(9) Alternatively, the region 4.sub.2 of the layer 4 may be anchored in the layer 1 by using the technique described in French patent application FR 2 859 201. That involves continuing etching the zone 5.sub.1 in the Si so as to be able subsequently to anchor the pillar in a shallow depth (e.g. 100 nm to 500 nm) by means of the region 4.sub.2, but without the pillar going through said layer 1. The etched zones in the sacrificial layer makes it possible to provide functional structures in the mechanical layer that are locally independent of the support.

(10) The non-etched zones of the sacrificial layer make it possible to make so-called anchor zones or mechanical reinforcement zones (or pillars). The layer 4 is referred to as the functionalization layer since it enables functions to be added to the sacrificial layer: pillars made with etching stops, electrodes under the sacrificial layer, electrical connections between the mechanical layer and said electrodes, or between portions of the mechanical layer that are not interconnected.

(11) Another insulating or non-insulating layer 6 referred to as a filler layer and made of a material that is different from the layer 4, e.g. of SiO.sub.2, is then made (e.g. by LPCVD or by PECVD) so as to fill the zone(s) 5.sub.1 and so as to cover all or part of the layer 4 covering the layer 2 (FIG. 1c). In particular, after providing total coverage as shown in FIG. 1c, it is possible to etch the layer 6 locally so that only a portion 6 remains surrounding the region(s) 5.sub.1 (see Schiltz and Pons Two-layer planarization process, J. Electrochem. Soc. 133: 178-181 (1986)). If the filler layer is made of the same material as the sacrificial layer, as in the example shown, then the layer 2 must cover the entire surface.

(12) Thereafter, starting from the configuration of FIG. 1c, the filler layer 6 or 6 is planarized to terminate the mechanical reinforcement zone(s) or pillars 9 constituted by the regions 4.sub.1, 4.sub.2, 6.sub.1 (FIGS. 1d and 1d). The method used for this purpose is chemical mechanical planarization (CMP), for example. This planarization may be carried out so as to remove only a fraction of the thickness of the layer 6 (FIG. 1d), or as shown in FIG. 1d, it may be continued and come to an end at the layer 4 of silicon nitride, allowing a substantially plane face to appear at the pillar (4.sub.1, 4.sub.2, 6.sub.1). Thereafter, a thin bonding layer 7 is deposited, e.g. an oxide layer (optionally followed by CMP), thereby making it possible subsequently to add on a substrate 8 of monocrystalline Si by molecular bonding (molecular bonding between Si and SiO.sub.2), optionally oxidized at its surface that comes into contact with the layer 7 (molecular bonding SiO.sub.2 and SiO.sub.2) (FIG. 1e). This deposit is optional when only a portion of the thickness of the layer 6 is removed (FIG. 1d). It may also be omitted from the configuration of FIG. 1d, but that leads to bonding via a heterogeneous interface, thereby giving rise, other things being equal, to bonding energies that are smaller.

(13) An important reason for selecting SiO.sub.2 as a filler is its ability to be deposited as a thick layer with little mechanical stress relative to the other materials such as silicon nitride or polysilicon, and also because of its suitability for being planarized with the thoroughly-mastered CMP technique. Furthermore, when the sacrificial layer is also made of SiO.sub.2, that makes it possible to limit non-uniformities of the sacrificial layer after functionalization; the layer is made for the great majority out of a single material. The filler layer is thus preferably made out of the same material as the sacrificial layer.

(14) In order to obtain a silicon substrate 1 of thickness suitable for making an MEMS (e.g. 5 m to 50 m thick), it is general practice to begin with a starting substrate that is thicker than the single layer 1, with this substrate subsequently being thinned to the desired thickness after the substrate 8 has been molecular bonded thereto. Such thinning may be performed by rectification followed by CMP.

(15) When the layer 1 is made of monocrystalline silicon grown on the SiGe stop layer, the silicon portion of the initial substrate is rectified to a thickness of about 10 m. The thickness is determined by the accuracy that is available for this rectification step and also in such a manner that the layer 1 does not include any work-hardened zones, which zones are created during the rectification step. It is thus a function in particular of the desired speed of rectification.

(16) The thickness of the remaining Si of the initial substrate is subsequently removed by chemical etching, stopping at the SiGe stop layer. Various methods are known for etching Si and stopping on SiGe. Mention can be made of wet etching methods (mixtures of the tetramethylammonium hydroxide (TMAH) or of the KOH type, cf. bibliography on selecting etching) or dry etching (Japanese Journal of Applied Physics, Vol. 43, No. 6B, 2004, pp. 3964-3966, 2004 The Japan Society of Applied Physics). The stop layer is subsequently removed by chemical etching stopping at the Si of the layer 1.

(17) Various known methods exist for etching SiGe and stopping on Si. Mention can be made of high temperature HCl etching methods (Selective chemical vapor etching of Si.sub.1-xGe.sub.x versus Si with gaseous HCl, by Y. Bogumilowicz, H. M. Hartmann, J. M. Fabri, and T. Bilon, in Semicond. Sci. Technol. 21, No. 12 (December 2006), pp. 1668-1674, chemical etching methods based on mixtures of the hydrofluoric acid, nitric acid, and acetic acid (HNA) type, and dry etching methods (see above-mentioned article in Japanese Journal of Applied Physics). This use of a starting substrate made up of a layer of SiGe on thick silicon provides better control over the final thickness of the layer 1.

(18) Depositing the layer 7 is optional, it being possible for the substrate 8 to be added by the technique described in patent application WO 2006/035031. That technique enables molecular bonding to be established between the substrate 8 and the surface made up of two different materials, in particular silicon nitride and SiO.sub.2.

(19) The method continues (FIG. 1e) in the upside-down position, as in the prior art method described in the introduction to the present description.

(20) Then, the process according to the invention further comprises a step of releasing the electromechanical structure by removing at least partially the sacrificial layer 2. The removal of the sacrificial layer can be done by etching openings 10, but also by any other means.

(21) The Si layer 1 is etched to make one or more openings 10 (FIG. 1f). These openings 10 may also serve to define the MEMS structure in the layer 1 and they are used to remove the sacrificial layer 2 by forming one or more cavities 2.sub.1 with the help of hydrofluoric acid in the liquid phase or the vapor phase, when etching a layer of SiO.sub.2, such that the active structure of FIG. 1 is held by the pillar(s) (4.sub.1, 4.sub.2, 6.sub.1). The pillar materials are selected so as to be selective relative to the solution used for etching the sacrificial layer. The mechanical structure is thus made in the layer 1 which can be referred to as a mechanical layer.

(22) It can be seen that the interface zone 8 between the substrate 8 fitted by molecular bonding and the layer 7 is protected from any chemical etching when making the opening(s) 10 and when releasing the MEMS structure by using HF acid to remove the sacrificial layer 2.

(23) FIGS. 2a to 2d show a variant embodiment in which the pillars include a conductive layer, here made of polycrystalline Si, thus enabling contacts to be made, and indeed multiple interconnection levels by combining conductive pillars and insulating pillars.

(24) As in FIG. 1a, FIG. 2a shows wells 35 being made in the sacrificial layer 2, e.g. made of SiO.sub.2, on a substrate 1 comprising in particular a layer 1, e.g. made of monocrystalline Si.

(25) FIG. 2b shows localized deposition (deposition over the entire surface and then localized etching) of an insulating first functionalization layer 31 made of silicon nitride, in particular on well zones where the insulating pillars are to be made. This nitride layer serves to provide insulating pillars and to isolate the polycrystalline Si layer (see description below) chemically from the mechanical layer 1 and the sacrificial layer 2 of the filler layer when made of the same material as the sacrificial layer such that the sacrificial layer 2 presents a free surface 2.

(26) FIG. 2c shows the localized deposition (in particular by deposition of the entire surface followed by localized etching) of a conductive second functionalization layer 30, e.g. of doped polycrystalline Si in well regions 35.sub.1 where it is desired to make pillars that also perform a conductive function, in particular for making contact with the layer 1 (mechanical layer). Outside well regions, this layer may also serve to make a first interconnection level or electrodes. The other wells 35.sub.2 may have no deposit of polycrystalline Si in order to limit capacitive coupling at the insulating pillars. This does not apply if, for reasons of topology, an electrical connection needs to be passed through an insulating pillar as shown in the wells 35.sub.1. It should be observed that the insulating functionalization layer 31 may be deposited after the conductive functionalization layer 30. However if the materials of the layers 1 and 30 cannot be etched selectively, then etching the functionalization layer in the wells needs to be performed in two stages: the functionalization layer is etched in the wells 35.sub.1, and then after the layer 30 has been made, the functionalization layer is etched in the wells 35.sub.2.

(27) FIG. 2d shows deposition of a filler layer 32, e.g. of SiO.sub.2, for filling the wells 35. This deposition is subsequently planarized by using a thinning technique, e.g. the CMP method.

(28) The pillars thus have either an external conductive layer 31 made of polycrystalline Si, or else an insulating layer 30 at a layer 32, e.g. of SiO.sub.2, constituting the core thereof. Depending on circumstances, the pillars are therefore made of two materials or of three materials.

(29) FIGS. 2c1, 2c2, and 2d show an embodiment including a second level of interconnection layer, here made by polycrystalline Si.

(30) This second level of interconnection layer enables tracks to be made that electrically interconnect two conductive zones 30 made of polycrystalline Si (conductive pillars or electrodes) that are not interconnected by the first level, for topological reasons.

(31) FIG. 2c1 shows an insulating layer 34 (nitride or oxide) being deposited for the purpose of insulating the interconnection layers. This layer is etched locally with etching stopping at the layer 30, thereby enabling electrical accesses (aa) to be provided on the zones 30 for connection.

(32) FIG. 2c2 shows a second localized conductive layer being made that serves to interconnect the electrical accesses (aa) in application of the interconnection scheme. Vias are thus provided between the first and second interconnection levels.

(33) These operations (depositing the insulating layer with openings, localized deposition of polycrystalline Si) can be repeated so as to make multiple interconnection levels using additional conductive and insulating functionalization layers.

(34) In particular, a last layer can be made as a layer that covers the entire component, optionally being connected to one or more tracks of the lower layers, and acting as a ground plane for the MEMS system.

(35) Depending on circumstances, the ground plane may also be made at the same level as the last track, in which case it covers part of the surface only.

(36) Finally, FIG. 2d shows a filler and bonding layer 40, e.g. made of silicon oxide, being deposited on the structure obtained in FIG. 2c2.

(37) FIGS. 3a to 3d show another variant of the method enabling the topology due to the various deposited layers to be limited: each localized deposition increases the topology of the final stack initially created by making zones such as 5.sub.1 in the sacrificial layer.

(38) FIG. 3a shows the substrate after layers of nitride 31 and of polycrystalline Si 30 have been deposited in succession using a method such as that described with reference to FIGS. 2a to 2c. To obtain a plane reference surface, the SiN layer 31 is made over the entire substrate apart from the zones of the polycrystalline Si pillars (layer 30). In the same manner, the polycrystalline Si layer is made over the entire surface of the layer 2, removing only the zones that serve to insulate those zones that need to be insulated.

(39) FIG. 3b shows an additional layer 35 made of SiN being deposited that serves as a reference for rectifying the filler layer.

(40) FIG. 3c shows deposition of the filler layer 36 made of SiO.sub.2 after chemical mechanical planarizing (CMP) stopping at the SiN layer 35.

(41) FIG. 3d shows deposition and planarizing of a second bonding layer 37, e.g. made of SiO.sub.2, serving to achieve bonding.

(42) It is also possible to make multiple interconnection levels using the so-called double damascene principle. After the steps of FIG. 3c, an additional oxide layer is made (FIG. 3c1) for use as insulation. This layer is locally etched to make openings (FIG. 3c2) corresponding to electrical connections between interconnection tracks. A polycrystalline Si layer is deposited on the entire plate, followed by CMP, stopping at the oxide, thereby leaving polycrystalline Si 39 only in the openings 39 (FIG. 3c3).

(43) FIG. 3c4 shows nitride and oxide layers 50 and 51 being deposited in succession. Openings 52 are made by successively etching the oxide 51 (stop on nitride) and then the nitride 50 (stop on oxide) that corresponds to the interconnection tracks (FIG. 3c5). The tracks 53 are made (FIG. 3d6) by depositing doped polycrystalline Si with CMP and stopping on the oxide constituting the layer 51.

(44) If an additional interconnection level is needed, the same principle can be repeated: an oxide layer 54 is made with Openings 55 being created therein (stop at the polycrystalline Si of the tracks 53) for the electrical connections (FIG. 3c7). These openings are filled with doped polycrystalline Si 56 by full wafer deposition, followed by CMP stopping at the oxide of the layer 54. The steps described in FIGS. 3c4 to 3c6 are repeated.

(45) Starting from the steps of FIG. 3c3, it is possible to replace the polycrystalline Si with a metal, such as copper, for example.

(46) Under such circumstances, it is possible to replace the substrate 8 with a substrate having CMOS circuits and terminated by a layer of Cu areas in a matrix of SiO.sub.2. In this variant, the bonding layer of FIG. 3d is not added since it is the combined oxide and Cu layer that acts as the bonding layer. This bonding serves to provide electrical connections between the MEMS substrate and the associated CMOS circuit substrate. Only a fraction of the metal areas needs to serve as electrical connections between the MEMS and the CMOS circuit, with the remainder being made to increase the effective bonding area. Under such circumstances, the electrical connection with the MEMS and CMOS circuit assembly take place via contacts made at the surface of the MEMS.

(47) It should be observed that the principle of bonding a CMOS circuit from an array of metal areas can be implemented even if the method used for making interconnections it not planar. For example, starting from the substrate of FIG. 2d, it is possible to make a plane of contact areas by adding a nitride layer and an oxide layer and then by making the array of areas using the method described Starting from FIG. 3c4.

(48) The plane of contact areas may be replaced by a continuous metal plane connected to a limited number of MEMS connection tracks and enabling electrical contacts to be established between the support and the MEMS ground.

(49) By way of example, FIG. 4 shows a pressure sensor made in accordance with the method of FIGS. 1a to 1f. An opening 10 is made through the substrate 1 within the perimeter of a pillar 9 (4.sub.1, 4.sub.1, 6.sub.1) of annular shape, and this opening is used for removing the sacrificial layer 2 within this perimeter so as to form a cavity 21. The opening 10 is then recovered in conventional manner, e.g. with polycrystalline silicon phosphosilicate glass (PSG). The region 22 of the substrate 1 that is situated in the perimeter of the pillar 9 forms the diaphragm of the pressure sensor and it is mechanically supported by the pillar.

(50) It is naturally possible to define one or more openings 10 for making MEMS of more complicated structure, e.g. including one or more fixed-end beams.

(51) Although the examples given essentially illustrate making a substrate in which the monocrystalline layer is made of silicon associated with a sacrificial layer made of SiO.sub.2, the invention enables substrate variants to be made, in particular a substrate with a layer of monocrystalline germanium associated with a sacrificial layer of SiO.sub.2, or indeed a substrate with a layer of monocrystalline perovskite associated with a sacrificial layer of polycrystalline Si or of SiO.sub.2.