NAND flash memory and status output method in NAND flash memory

Abstract

The present application provides a status output method in NAND flash memory, including, setting ALE signal, CLE signal and WE#, signal wherein ALE and/or CLE signal is set to be 1 and WE# signal is set to be 1; when a falling edge of the RE# is detected, outputting LUN status signal of the NAND flash memory. Further, there is provided a NAND flash memory, including I/O signal pins, which includes an ALE signal pin, an CLE signal pin, a WE# signal pin, and a RE# signal pin; wherein when the ALE signal output by the ALE pin and/or CLE signal output by the CLE pin is 1, and WE# signal output by the WE# pin is 1, once a falling edge of the RE# is detected, the LUN status signal of the NAND flash memory is detected.

Claims

1. A status output method in NAND flash memory, comprising: setting an address latch enable (ALE) signal, a command latch enable (CLE) signal and a write enable (WE#) signal, wherein the address latch enable (ALE) signal and/or the command latch enable (CLE) signal is set to be 1 and the write enable (WE#) signal is set to be 1; when a falling edge of a read enable (RE#) is detected, outputting a logic unit (LUN) status signal of the NAND flash memory; wherein, when the address latch enable (ALE) signal and/or the command latch enable (CLE) signal is detected to be 1, storing the logic unit (LUN) status signal in a storage area of the NAND flash memory.

2. The status output method according to claim 1, wherein the storage area is a register.

3. A NAND flash memory, comprising: I/O signal pins, including an address latch enable (ALE) pin, a command latch enable (CLE) pin, a write enable (WE#) pin, and a read enable (RE#) pin; wherein when an ALE signal outputted by the address latch enable (ALE) pin and/or a CLE signal outputted by the command latch enable (CLE) pin is 1, and a WE# signal outputted by the write enable (WE#) pin is 1, once a falling edge of the read enable (RE#) pin is detected, a logic unit (LUN) status signal of the NAND flash memory is detected; wherein the NAND flash memory further comprises a storage for storing the logic unit (LUN) status signal of the NAND flash memory.

4. The NAND flash memory according to claim 3, wherein the storage is a register.

5. The NAND flash memory according to claim 3, wherein the NAND flash memory is a multi-die package NAND flash memory.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Through reading the detailed description of the following preferred embodiments, various other advantages and benefits will become apparent to those of ordinary skills in the art. Accompanying drawings are merely included for the purpose of illustrating the preferred embodiments and should not be considered as limiting of the application. Further, throughout the drawings, like elements are indicated by like reference numbers.

(2) FIG. 1 is a schematic diagram showing the control signals for obtaining the status of the NAND flash memory in the prior art.

(3) FIG. 2 is a schematic diagram showing the control signals for obtaining the status of the NAND flash memory according to an embodiment of the present application.

(4) FIG. 3 is a schematic diagram showing the control signals for obtaining the status of the NAND flash memory according to another embodiment of the present application.

(5) FIG. 4 is a schematic diagram showing the control signals for obtaining the status of the NAND flash memory according to still another embodiment of the present application.

(6) FIG. 5 is a chart showing the signal level of each control signal and the corresponding functions.

(7) FIG. 6 is a schematic diagram showing the method for obtaining the status of each chip in the multi-chip package according to an embodiment of the present application.

(8) FIG. 7 is a flow chart showing the method for obtaining the status of the present application.

DETAILED DESCRIPTION OF THE INVENTION

(9) Exemplary embodiments of the present application will be described in detail with reference to the accompanying drawings hereinafter.

(10) As shown in FIG. 2, it is a schematic diagram showing the control signals for obtaining the status of the NAND flash memory according to an embodiment of the present application. As shown in FIG. 2, in time t1, the ALE signal and CLE signal are set to be 1, which means command latch is enabled and address latch is enabled, the current status of NAND flash memory may be written in storage area of the NAND flash memory such as register. Then, in time t2, the RE# signal is toggled to be 0, which means read is enabled, and the NAND flash memory can read data from I/O bus. When the NAND flash memory detects the toggle of RE# in time t2, it obtains the current status from the storage area such as register, and output the current status via the I/O bus.

(11) As shown in FIG. 3, it is a schematic diagram showing the control signals for obtaining the status of the NAND flash memory according to another embodiment of the present application. As shown in FIG. 3, in time t1, the ALE signal is set to be 1, which means address latch is enabled, the current status of NAND flash memory may be written in storage area of the NAND flash memory such as register. Then, in time t2, the RE# signal is toggled to be 0, which means read is enabled, and the NAND flash memory can read data from I/O bus. When the NAND flash memory detects the toggle of RE# in time t2, it obtains the current status from the storage area such as register, and output the current status via the I/O bus.

(12) As shown in FIG. 4, it is a schematic diagram showing the control signals for obtaining the status of the NAND flash memory according to still another embodiment of the present application. As shown in FIG. 4, in time t1, the CLE signal is set to be 1, which means command latch is enabled, the current status of NAND flash memory may be written in storage area of the NAND flash memory such as register. Then, in time t2, the RE# signal is toggled to be 0, which means read is enabled, and the NAND flash memory can read data from I/O bus. When the NAND flash memory detects the toggle of RE# in time t2, it obtains the current status from the storage area such as register, and output the current status via the I/O bus.

(13) FIG. 5 is a chart showing the signal level of each control signal and the corresponding functions. As shown in last three lines of the chart in FIG. 5: when the RE# signal is 0, ALE signal is 1, CLE signal is 1, WE# signal is 1, WP# signal is 1, the corresponding function is read output, the current status can be output; when the RE# signal is 0, ALE signal is 1, CLE signal is 0, WE# signal is 1, WP# signal is 1, the corresponding function is read output, the current status can be output; when the RE# signal is 0, ALE signal is 0, CLE signal is 1, WE# signal is 1, WP# signal is 1, the corresponding function is read output, the current status can be output.

(14) As shown in FIG. 6, the application is also adapted to a multi-die package. As each flash memory (also called chip or die) in the package has independent control signals, the output status of each die is also independent. In the embodiment in FIG. 6, with respect to the Target 0 and Target 1, the output R/B_0# and R/B_1# are independent. A skilled person in the art may change the number of dies according to different situations, which may be 4 dies, 8 dies, 16 dies, and the application is not limited thereto.

(15) As shown in FIG. 7, it is a flow chart showing the status output method for NAND flash memory according to an embodiment of the present application, in FIG. 7, the method may include steps as follows: S701, setting ALE signal, CLE signal and WE#, signal wherein ALE signal and/or CLE signal is set to be 1 and WE# signal is set to be 1; S702, when a falling edge of the RE# is detected, outputting LUN status signal of the NAND flash memory.

(16) In an embodiment, prior to the step S701, the method may further include the following step: S700, when the ALE signal and/or CLE signal is detected to be 1, storing LUN status signal in a storage area of the NAND flash memory. The storage area may be a register.

(17) The application further discloses a NAND flash memory, comprising: I/O signal pins, which includes an ALE signal pin, an CLE signal pin, a WE# signal pin, and a RE# signal pin: wherein when the ALE signal output by the ALE pin and/or CLE signal output by the CLE pin is 1, and WE# signal output by the WE# pin is 1, once a falling edge of the RE# is detected, the LUN status signal of the NAND flash memory is detected.

(18) In an embodiment of the present application, the NAND flash memory further comprises a storage for storing LUN status signal of the NAND flash memory.

(19) In an embodiment of the present application, the storage is a register.

(20) In an embodiment, the NAND flash memory is a multi-die package NAND flash memory.

(21) The an embodiment, embodiments or one or more embodiments mentioned in the disclosure means that the specific features, structures or performances described in combination with the embodiment(s) would be included in at least one embodiment of the present application. Moreover, it should be noted that, the wording in an embodiment herein may not necessarily refer to the same embodiment.

(22) Many details are discussed in the specification provided herein. However, it should be understood that the embodiments of the disclosure may be implemented without these specific details. In some examples, the well-known methods, structures and technologies are not shown in detail so as to avoid an unclear understanding of the description.

(23) In the application, there is provided a status output method and NAND flash memory thereof, in which the status is output faster than that in the conventional technology and the system performance is improved, and the speed for waiting for status signal should be improved.

(24) It should be noted that the above-described embodiments are intended to illustrate but not to limit the present application, and alternative embodiments may be devised by the person skilled in the art without departing from the scope of claims as appended. In the claims, any reference symbols between brackets form no limit of the claims. The wording include does not exclude the presence of elements or steps not listed in a claim. The wording a or an in front of an element does not exclude the presence of a plurality of such elements. The disclosure may be realized by means of hardware comprising a number of different components and by means of a suitably programmed computer. In the unit claim listing a plurality of devices, some of these devices may be embodied in the same hardware. The wordings first, second, and third, etc. do not denote any order. These wordings may be interpreted as a name.

(25) Also, it should be noticed that the language used in the present specification is chosen for the purpose of readability and teaching, rather than explaining or defining the subject matter of the present application. Therefore, it is obvious for an ordinary skilled person in the art that modifications and variations could be made without departing from the scope and spirit of the claims as appended. For the scope of the present application, the publication of the inventive disclosure is illustrative rather than restrictive, and the scope of the present application is defined by the appended claims.