METHOD FOR MANUFACTURING LOW-TEMPERATURE POLY-SILICON THIN FILM TRANSISTOR

Abstract

Disclosed is a method for manufacturing a low-temperature poly-silicon thin film transistor, which relates to the technical field of display panel. The method comprises steps of: forming a gate layer, an active layer, a source-drain contact layer and a source-drain electrode in sequence on a substrate. The step of forming the source-drain contact layer includes sub steps of: forming a channel protection layer; depositing an ohmic contact layer using a reaction gas containing diborane and through a plasma enhanced chemical vapor deposition method; and patterning the ohmic contact layer to form the source-drain contact layer. During deposition of the ohmic contact layer, boron ions can enter into the source-drain contact layer. According to this method, a mask is not needed to define an implanted region of boron ions. Therefore, a procedure of implanting the boron ions can be saved; the manufacturing procedure can be simplified; and the manufacturing cost can be reduced.

Claims

1. A method for manufacturing a low-temperature poly-silicon thin film transistor, comprising steps of: S11: forming a gate layer on a substrate; S12: forming an active layer; S13: forming a source-drain contact layer; and S14: forming a source-drain electrode layer, wherein the step of forming the source-drain contact layer comprises sub steps of: forming a channel protection layer; depositing an ohmic contact layer through a plasma enhanced chemical vapor deposition method, wherein a reaction gas contains diborane; and patterning the ohmic contact layer to form the source-drain contact layer.

2. The method according to claim 1, wherein the reaction gas further comprises silane and hydrogen.

3. The method according to claim 1, wherein a material used in the step of depositing the ohmic contact layer comprises P.sup.+a-Si.

4. The method according to claim 2, wherein a material used in the step of depositing the ohmic contact layer comprises P.sup.+a-Si.

5. The method according to claim 1, wherein the step of forming the channel protection layer comprises sub steps of: depositing an etching barrier layer on the active layer; and hydrotreating the etching barrier layer through heating, and patterning the etching barrier layer to form the channel protection layer.

6. The method according to claim 2, wherein the step of forming the channel protection layer comprises sub steps of: depositing an etching barrier layer on the active layer, and hydrotreating the etching barrier layer through heating, and patterning the etching barrier layer to form the channel protection layer.

7. The method according to claim 5, wherein the etching barrier layer comprises at least one of a silicon oxide layer and a silicon nitride layer.

8. The method according to claim 6, wherein the etching barrier layer comprises at least one of a silicon oxide layer and a silicon nitride layer.

9. The method according to claim 1, wherein the step of forming the active layer comprises sub steps of: depositing a gate insulating layer on an entire surface of the substrate; depositing an amorphous silicon layer; transforming the amorphous silicon layer to a poly-silicon layer through an excimer laser annealing procedure; and patterning the poly-silicon layer to form the active layer.

10. The method according to claim 1, wherein the step of forming the gate layer comprises sub steps of: depositing a first metal layer on an entire surface of the substrate; and patterning the first metal layer to form the gate layer.

11. The method according to claim 10, wherein a buffer layer is manufactured on the entire surface of the substrate before the first metal layer is deposited thereon.

12. The method according to claim 11, wherein the buffer layer comprises at least one of a silicon oxide layer and a silicon nitride layer.

13. The method according to claim 10, wherein a material of the gate layer comprises at least one selected from a group consisting of molybdenum, tantalum, aluminum and tungsten.

14. The method according to claim 11, wherein a material of the gate layer comprises at least one selected from a group consisting of molybdenum, tantalum, aluminum and tungsten.

15. The method according to claim 12, wherein a material of the gate layer comprises at least one selected from a group consisting of molybdenum, tantalum, aluminum and tungsten.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The present disclosure will be illustrated in detail hereinafter with reference to the embodiments and the accompanying drawings. In the drawings:

[0033] FIG. 1 is a flow chart of a method for manufacturing a low-temperature poly-silicon thin film transistor according to the present disclosure;

[0034] FIG. 2 schematically shows a structure after a gate layer is formed;

[0035] FIG. 3 schematically shows a structure after an active layer is formed;

[0036] FIG. 4 schematically shows a structure after a source-drain contact layer is formed;

[0037] FIG. 5 schematically shows a structure after a source-drain electrode layer is formed; and

[0038] FIG. 6 schematically shows a structure of an array substrate comprising the low-temperature poly-silicon thin film transistor according to the present disclosure.

[0039] In the drawings, the same components are represented by the same reference signs, and the size of each component does not represent the actual size of the corresponding component.

DETAILED DESCRIPTION OF THE EMBODIMENTS

[0040] The present disclosure will be described in detail hereinafter with reference to the accompanying drawings. The terms upper, lower, right, and left in the following text are directions relative to the directions shown in the drawings, and should not be construed as limiting the scope of the disclosure.

Embodiment 1

[0041] FIG. 1 shows a method for manufacturing a low-temperature poly-silicon thin film transistor according to the present embodiment. The method comprises steps of:

[0042] in step S11, a gate layer is formed on a substrate;

[0043] in step S12, an active layer is formed;

[0044] in step S13, a source-drain contact layer is formed; and

[0045] in step S14, a source-drain electrode layer is formed.

[0046] Each step will be described in detail below.

[0047] In step S11, the gate layer is formed on the substrate. As shown in FIG. 2, first, a buffer layer 112 is manufactured on an entire surface of a substrate 111, and the buffer layer 112 comprises a silicon nitride layer 1121 and a silicon oxide layer 1122. Of course, according to other embodiments, the buffer layer 112 can comprise only the silicon nitride layer 1121 or the silicon oxide layer 1122. Then, a first metal layer is deposited on the buffer layer 112. Preferably, a material that constitutes the first metal layer is molybdenum. According to other embodiments, the material of the first metal layer can be at least one selected from a group consisting of molybdenum, tantalum, aluminum and tungsten. The first metal layer is patterned through a photographic etching technology to form a gate layer 113.

[0048] A degree of adherence between the gate layer 113 and the substrate 111 can be improved by the buffer layer 112. Meanwhile, metal ions in the substrate 111 can be prevented from diffusing to the gate layer 113 by the buffer layer 112, and thus a leakage current can be reduced.

[0049] Of course, according to other embodiments, a procedure of forming the buffer layer may not be contained in the procedure of forming the gate layer 113.

[0050] In step S12, the active layer is formed. As shown in FIG. 3, a gate insulating layer 121 is deposited on the gate layer 113. Preferably, a material of the gate insulating layer 121 is silicon oxide. Then, an amorphous silicon layer is deposited on the gate insulating layer 121, and the amorphous silicon layer is processed by an excimer laser annealing procedure and transformed to a poly-silicon layer. Next, the poly-silicon layer is patterned to form the active layer 122.

[0051] During the procedure, the poly-silicon layer is obtained through the excimer laser annealing procedure. In this manner, the problem that the entire substrate heated by the excimer laser annealing procedure affects a flexible display device can be avoided, which is conducive to realization of flexible display. Besides, lattice integrity of poly-silicon can be improved by local hyperthermia of the excimer laser annealing procedure, so that a performance of the TFT can be improved.

[0052] In step S13, the source-drain contact layer is formed. As shown in FIG. 4, an etching barrier layer is deposited on an entire surface of the active layer 122 on the substrate 111. Preferably, the etching barrier layer comprises a silicon oxide layer and a silicon nitride layer. According to other embodiments, the etching barrier layer can comprise only the silicon oxide layer or the silicon nitride layer. The etching barrier layer is hydrogenated through heating, and patterned through the photographic etching technology to form a channel protection layer 131. Since the etching barrier layer in the embodiment comprises the silicon oxide layer and the silicon nitride layer, the channel protection layer 131 comprises a first channel protection layer 1311 and a second channel protection layer 1312.

[0053] An ohmic contact layer is deposited on the channel protection layer 131 using a reaction gas containing diborane and through a PECVD method. A material of the ohmic contact layer is preferably P+a-Si, and the reaction gas is preferably a mixture of silane, hydrogen and diborane. Here, the ohmic contact layer is also patterned through the photographic etching technology to form a source-drain contact layer 132. When the reaction gas used therein contains diborane, boron ions can enter into the ohmic contact layer during deposition of the ohmic contact layer through the PECVD method, so that the formed source-drain contact layer contains the boron ions. Therefore, an impedance of the source-drain contact layer can be reduced, and the contact impedances thereof with the source and the drain become smaller. According to this method, a mask is not needed to define an implanted region of boron ions. Therefore, a process of implanting the boron ions can be saved; the manufacturing procedure can be simplified; and the manufacturing cost can be reduced.

[0054] When a material of the ohmic contact layer is P.sup.+a-Si, the thin film transistor manufactured therein is a P-type transistor. Of course, the material of the ohmic contact layer can also be N.sup.+a-Si, and accordingly, the thin film transistor manufactured therein is an N-type transistor.

[0055] In step S14, the source-drain electrode layer is formed. As shown in FIG. 5, a second metal layer is deposited on the source-drain contact layer 132. Preferably, a material of the second metal layer comprises at least one of molybdenum and aluminum. The second metal layer is patterned through the photographic etching technology to form the source-drain electrode layer 141.

[0056] The present disclosure further provides a low-temperature poly-silicon thin film transistor which is manufactured by the aforesaid method.

Embodiment 2

[0057] While manufacturing an array substrate containing the low-temperature poly-silicon thin film transistor manufactured by the aforesaid method, a step S15 is further comprised. As shown in FIG. 6, an organic photoresist planar insulating layer 151 is manufactured on the source-drain electrode layer 141, and then an Anode electrode layer 152 is manufactured. Then a pixel-defining layer (PDL) and a pillar spacer (PS) layer are manufactured.

[0058] Finally, it should be noted that, the above embodiments are only used to explain the technical solution of the present disclosure and shall not be construed as limitation.

[0059] Although the present disclosure has been described in detail with reference to preferred embodiments, ordinary people skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present disclosure. In particular, as long as there are no structural conflicts, the technical features disclosed in each and every embodiment of the present disclosure can be combined with one another in any way, and the combined features formed thereby are within the protection scope of the present disclosure. As long as the technical solutions do not depart from the scope and spirit of the disclosure, all of them shall fall within the scope of the claims.