INSULATING SELF-DEVELOPING RESIST FOR ELECTRONIC DEVICES AND QUANTUM POINT CONTACTS

Abstract

Methods for utilizing irradiation to selectively transform insulating self-developing resists, such as metal fluorides, into electrically conductive metals are described. The disclosed methods enable the fabrication of electrical components and structures with critical dimensions below 5 nanometers. Selective irradiation induces the conversion of insulating metal fluoride compounds into metals in predefined regions. Examples of applications include miniature wiring, quantum point contacts, miniature electroplating and via-holes fabrication by using fluoride as etching mask.

Claims

1. A method of fabricating a miniature quantum point contact comprising: providing a first layer, the first layer including metal; depositing a second layer on top of the first layer, the second layer comprising an insulating electron beam resist, and exposing the second layer to an electron beam to generate a miniature quantum point contact, the miniature quantum point contact having a constriction width of less than 7 nm.

2. The method of claim 1, wherein the electron beam resist comprises metal fluoride.

3. The method of claim 2, wherein the metal fluoride is selected from one of AlF.sub.3, LiF, YbF.sub.2, CuF.sub.2, AgF, NbF5, CeF3, CaF2, MgF2, PbF2, or BiF3.

4. The method of claim 2, wherein the metal of the first layer comprises a pre-deposited metal or highly conducting semiconductor, such as gold, copper, aluminum, silicon, iron, nickel, chromium, platinum, or graphite.

5. A method of fabricating a miniature wire comprising: providing a first layer comprising an insulated layer with two metal contacts on top; depositing a second layer on top of the first layer, the second layer comprising an insulating electron beam resist; exposing the second layer to an electron beam going from one metal contact to another metal contact of the two metal contacts, across an exposure line, thereby forming the miniature wire that connects the two metal contacts, the miniature wire having a width of less than 7 nm.

6. The method of claim 5, wherein the electron beam resist comprises metal fluoride.

7. The method of claim 6, wherein the metal fluoride is selected from one of AlF.sub.3, LiF, YbF.sub.2, or CuF.sub.2, AgF, NbF5, CeF3, CaF2, MgF2, PbF2, or BiF3.

8. The method of claim 6, wherein the miniature wire comprises the metal making up the fluoride, such as copper, aluminum gold, platinum, niobium or ytterbium.

9. A method of via-hole fabrication comprising: providing a first layer serving as a substrate; depositing a second layer on top of the first layer, the second layer comprising a electron beam resist; exposing the second resist layer with an electron beam to generate a miniature hole inside the second layer; the miniature hole having a constriction width of less than 7 nm; and by using the second layer as an etch mask, etching through the first layer, to generate a via through the miniature hole and inside the first layer, the via having with a width of less than 7 nm.

10. The method of claim 8, wherein the electron beam resist comprises metal fluoride.

11. The method of claim 9, wherein the metal fluoride is selected from one of AlF.sub.3, LiF, YbF.sub.2, CuF.sub.2, SrF2, BaF2, CaF2, MgF2, NaF, or alloys using these fluorides.

12. A method of generating interconnects comprising: providing a first layer serving as a substrate; depositing a second layer on top of the first layer, the second layer comprising an electron beam resist; exposing the second layer with an electron beam to generate miniature trenches inside the second layer, based on an interconnection scheme, the miniature trenches having widths of less than 7 nm, and electroplating metal into the second layer along the miniature trenches.

13. The method of claim 12, wherein the electron beam resist comprises metal fluoride.

14. The method of claim 13, wherein the metal fluoride is selected from one of AlF.sub.3, LiF, YbF.sub.2, or CuF.sub.2, SrF2, BaF2, NaF, AgF, NbF5, CeF3, CaF2, MgF2, PbF2, or BiF3.

15. The method of claim 6, further comprising depositing an oxidation barrier layer on top of the second layer to cover the miniature wire, thereby protecting the miniature wire from oxidation.

16. A method of fabricating an array of miniature quantum points contacts, comprising: providing a first layer, the first layer including metal; depositing a second layer on top of the first layer, the second layer comprising an electron beam resist, and exposing the second layer to an array of electron beams to generate the array of miniature quantum point contacts, the miniature quantum point contacts having each a constriction width of less than 7 nm.

17. A method of fabricating a miniature conducting point contact comprising: providing a first layer, the first layer including metal; depositing a second layer on top of the first layer, the second layer comprising an insulating electron beam resist, and exposing the second layer to an electron beam to generate a miniature conducting point contact, the miniature conducting point contact having a constriction width of less than 7 nm.

18. The method of claim 17, wherein the miniature conducting point contact comprises a metal point contact.

Description

DESCRIPTION OF THE DRAWINGS

[0021] FIG. 1 shows a schematic plot of point-contact conductance as a function of gate voltage.

[0022] FIG. 2A shows an exemplary layered structure including miniature QPC according to an embodiment of the present disclosure.

[0023] FIG. 2B shows an exemplary method and the fabrication steps to generate an array of miniature QPCs according to an embodiment of the present disclosure.

[0024] FIGS. 3-4 show exemplary arrays of QPCs fabricated according to the teachings of the present disclosure.

[0025] FIGS. 5A-5D show an exemplary method of fabricating a miniature wire according to an embodiment of the present disclosure.

[0026] FIG. 6 shows an exemplary fabrication method according to the teachings of the present disclosure where fluoride is used as self-developing resist for etching mask.

[0027] FIG. 7 shows an exemplary fabrication method according to the teachings of the present disclosure where fluoride is used as self-developing resist for electroplating mask.

DETAILED DESCRIPTION

[0028] Throughout this document, the term miniature, when used to describe a device or structure, is defined as having a width less than 7 nanometers (nm). As an example, a miniature (QPC) would indicate a QPC with a constriction width on the order of less than 7 nm, e.g., 2 nm. Other examples include a miniature wire, referring to a conductive wire with a width below 7 nm, or a miniature gap, signifying a separation between two surfaces, structures, or features that is less than 5 nm wide.

[0029] Throughout this document the term electron beam resist refers to materials, such as metal fluorides (e.g., AlF.sub.3, LiF, YbF.sub.2, or CuF.sub.2, SrF2, BaF2, NaF, AgF, NbF5, CeF3, CaF2, MgF2, PbF2, or BiF3 etc.). Such materials can be changed by irradiation with an electron beam. Upon exposure, fluorine can evaporate from the exposed area, leaving the metal behind. According to the teachings of the present disclosure, this kind of process can occur at the nanoscale level and, as a result, features with dimensions of less than 7 nm, e.g. 1 nm, can be made when a well-focused electron beam is used to expose the electron beam resist, e.g., fluoride.

[0030] FIG. 2A shows a layered structure (200) including a miniature QPC (204), the figure illustrating an exemplary method to fabricate a miniature QPC (204) according to an embodiment of the present disclosure. FIG. 2B shows an exemplary method and the fabrication steps to generate an array of miniature QPCs (204) in accordance with the teachings of the present disclosure. The method comprises providing a first layer (201), depositing a second layer (202) on top of first layer (201), exposing layer (202) to an array of tightly focused electron beams (205) to produce point contacts (204) at the irradiated spot. This will be followed by depositing a third layer (203) on top of layer (202). The embodiment of FIG. 2B is an exemplary application of the teachings of the present disclosure. Such embodiment essentially demonstrates how to use, for example, fluoride as self-developing resist for point contact array fabrication. With reference to FIG. 2A, according to an embodiment of the present disclosure, the constriction width of QPC (204) as indicated by arrows (250), can be less than 7 nm, e.g. 1 nm, as indicated in the figure. With continued reference to FIGS. 2A-2B, the first layer (201) may be made of a metallic material, such as a pre-deposited metal or highly conducting semiconductor, such as gold, copper, aluminum, silicon, iron, nickel, chromium, platinum, or graphite.

[0031] On the other hand, the second layer (202) could be an electron beam resist, composed of various materials, such as fluoride-based materials including, for example, AlF.sub.3, LiF, YbF.sub.2, or CuF.sub.2, SrF2, BaF2, NaF, AgF, NbF5, CeF3, CaF2, MgF2, PbF2, or BiF3. Serving as the top contact, the third layer (203), may also be a metal. In an exemplary embodiment where second layer (202) comprises metal fluoride, during electron irradiation, the fluoride loses its fluorine and converts into metal. The self-developing fluoride layer, with resistivities above 10 ohm.Math.cm, offers excellent electronic isolation. A point contact (204) is formed at the irradiated spot. In an exemplary fabrication process where the electron beam may be focused to, for example, 0.12 nm or less, the resulting point contacts can be between 0.5 and 2 nm in diameter. The embodiments of FIGS. 2A-2B are just examples demonstrating the disclosed teachings in the context of quantum point contacts. However, the disclosed teachings can be used to apply, generally, conducting contacts. Such conducting contacts may include metal point contacts and quantum point contacts.

[0032] Various miniature features have been fabricated to show the feasibility of the disclosed teachings. As an example, FIG. 3 shows 1.5 nm QPCs (304) defined in 30 nm thick YbF.sub.2 with a 160 kV electron beam. In this image, the lattice image of a crystal in the YbF mask is used to characterize the diameter of an etched hole in Si3N4 to be 1.5 nm. One challenge is to deposit metal into the hole formed by the electron beam. In an embodiment, optimized methods for vacuum deposition or electroplating into fluoride layers without enlarging the QPC structure may be used. Methods of depositing noble metals such as Au, Cu or ferromagnets such as Ni, Co can enable the formation of dense arrays of optically or magnetically switchable point contacts. FIG. 4 shows an example of such array of QPCs (404) fabricated using the disclosed teachings.

[0033] QPCs can be used as extremely sensitive charge detectors. Since the conductance through the contact strongly depends on the size of the constriction, any potential fluctuation (for instance, created by light, magnetic fields, or other electrons) in the vicinity will influence the current through the QPC. It is possible to detect single electrons with such a scheme. In solid-state systems, QPCs can be used as readout devices for the state of quantum bits, as switches, or as transistors. Unlike previous QPC systems, the disclosed devices can be directly integrated into silicon CMOS electronic circuits. This will enable the harnessing of ballistic electron transport through essentially one-dimensional nanometer-scale channels and develop a compelling alternative to 2 DEG heterostructures, quantum wires or nanotubes made from materials systems that are difficult to integrate into silicon circuits.

[0034] Using the disclosed teachings, direct writing of miniature wire connecting to metal contacts is made possible. FIGS. 5A-5D illustrate an example of different steps to be taken to fabricate a miniature wire. A first layer comprising an insulated layer (501) with two metal contacts (502) on top is first provided. A second layer (503), comprising, for example, metal fluoride is then deposited on top of the first layer. The resulting structure is then exposed to electron beam going from one metal contact (502) to another, as indicated by the exposure line (505) of FIG. 5C, thereby writing a miniature wire (506) (FIG. 5D) that connects the metal contacts (502). In an embodiment, second layer (503) comprises metal fluoride. As a result of irradiation (504), the metal fluoride will lose fluorine and convert into metal along exposure line (505) which connects the two metal contacts (502). Examples of metals that can be used as part of the metal fluoride are aluminum and copper. In accordance with the teachings of the present disclosure, miniature wire (506) may be made with a width of less than 7 nm.

[0035] With continued reference to FIGS. 5A-5D, an optional step to the fabrication process may be added to protect the formed miniature wire (506) from oxidation. Such step includes the addition of an oxidation barrier layer (not shown) on top of second layer (503) to cover the miniature wire (506). In an embodiment, second layer (503) comprises AlF.sub.3, while the optional oxidation barrier layer comprises BaF.sub.2.

[0036] FIG. 6 shows an exemplary via-hole fabrication method according to the teachings of the present disclosure. The method essentially demonstrates how to use, for example, fluoride as self-developing resist for etch masking. A first layer (601) is first provided, the layer serving as a substrate. A second layer (602) is then deposited on top of first layer (601). The second layer (602) can be composed of various materials, such as fluoride-based materials including, for example, AlF.sub.3, LiF, YbF.sub.2, or CuF.sub.2, SrF2, BaF2, NaF, AgF, NbF5, CeF3, CaF2, MgF2, PbF2, or BiF3. The structure is then exposed with electron beams (605) to generate miniature holes (610). The second layer (602) is subsequently used as an etch mask to generate vias (611).

[0037] FIG. 7 shows an exemplary fabrication method according to the teachings of the present disclosure. The method essentially demonstrates how to use, for example, fluoride as self-developing resist for an electroplating mask. A first layer (701) is first provided, the layer serving as a substrate. A second layer (702) is then deposited on top of first layer (701). The second layer (702) can be composed of various materials, such as fluoride-based materials including, for example, AlF.sub.3, LiF, YbF.sub.2, CuF.sub.2. The structure is then exposed with electron beams (705) to generate miniature trenches (710). This is followed by electroplating metal (720) into second layer (702). This process can be used, for example, to form the wiring (interconnects) between transistors and other components in an integrated circuit, based on a desired interconnection scheme.

[0038] In the past, vacuum diodes and triodes with emitter-anode dimensions down to 7 nm have been developed. Same devices with emitter-anode dimensions of less than 7 nm, e.g. 2 nm, can be fabricated based on the described methods. The existing field emission triodes have been limited by the high impedance of the devices, a direct result of the work function of the emitters that limit the minimum operating voltage to above 5V. Several approaches have been adopted to overcome this limitation, including using multi-tip emitters and coating the emitters with low work function materials, but the emission voltage can still not be reduced to below 3V using the existing solutions.

[0039] The enhanced lithographic fabrication techniques disclosed herein allow for the construction of structures with, for example, 2 nm electrode spacing, enabling access to the metal-vacuum-metal (MVM) tunneling mechanism. As a result, the construction of MVM triodes and multi-terminal tunnel devices having low impedances becomes feasible. Such devices can exhibit superior performance compared to conventional semiconductor transistors. Furthermore, their robustness is ensured, as MVM tunneling relies on well-established physics-that is used in scanning tunneling microscopes (STM), a common surface characterization technique. The essential dimensions required to implement these devices are readily accessible through the utilization of state-of-the-art silicon fabrication lines.