TRANSISTOR, ELECTRONIC DEVICE, AND METHOD FOR MANUFACTURING TRANSISTOR

Abstract

What is provided is a transistor including a gate electrode, a gate insulating film, a semiconductor film, a source electrode, and a drain electrode, in which the gate insulating film is a laminated film in which a SiO.sub.x film and a SiC.sub.yN.sub.z film are alternately formed, the total number of films constituting the laminated film is 3 or more and 18 or less, and the thickness of each film constituting the laminated film is 25 nm or more and 150 nm or less.

Claims

1. A transistor comprising: a gate electrode; a gate insulating film; a semiconductor film; a source electrode; and a drain electrode, wherein the gate insulating film is a laminated film in which a SiOx film and a SiCyNz film are alternately formed, a total number of films constituting the laminated film is 3 or more and 18 or less, and a thickness of each film constituting the laminated film is 25 nm or more and 150 nm or less.

2. The transistor according to claim 1, wherein x in the SiOx film is 1.7 or more and 2.4 or less.

3. The transistor according to claim 1, wherein y in the SiCyNz film is 1.0 or more and 3.5 or less, and z is more than 0 and 1.0 or less.

4. The transistor according to claim 1, wherein a total thickness of the laminated film is 500 nm or less.

5. The transistor according to claim 1, wherein in the laminated film, a layer that is in contact with the semiconductor film is the SiOx film.

6. The transistor according to claim 1, wherein a thickness of each film constituting the laminated film is substantially the same.

7. The transistor according to claim 1, wherein the transistor is formed on a flexible substrate.

8. The transistor according to claim 1, wherein the transistor is formed on a substrate made of a resin material.

9. An electronic device comprising the transistor according to claim 1.

10. A method for manufacturing the transistor according to claim 1, the method comprising: a gate insulating film forming step of alternately forming the SiOx film and the SiCyNz film by a plasma CVD method to form the gate insulating film, wherein in the gate insulating film forming step, a film formation temperature is a temperature lower than a softening point of a material constituting a substrate.

11. The method for manufacturing the transistor according to claim 10, further comprising: an annealing step of performing annealing at the temperature lower than the softening point after the gate insulating film forming step.

12. The transistor according to claim 2, wherein y in the SiCyNz film is 1.0 or more and 3.5 or less, and z is more than 0 and 1.0 or less.

13. The transistor according to claim 2, wherein a total thickness of the laminated film is 500 nm or less.

14. The transistor according to claim 2, wherein in the laminated film, a layer that is in contact with the semiconductor film is the SiOx film.

15. The transistor according to claim 2, wherein a thickness of each film constituting the laminated film is substantially the same.

16. The transistor according to claim 2, wherein the transistor is formed on a flexible substrate.

17. The transistor according to claim 2, wherein the transistor is formed on a substrate made of a resin material.

18. An electronic device comprising the transistor according to claim 2.

19. A method for manufacturing the transistor according to claim 2, the method comprising: a gate insulating film forming step of alternately forming the SiOx film and the SiCyNz film by a plasma CVD method to form the gate insulating film, wherein in the gate insulating film forming step, a film formation temperature is a temperature lower than a softening point of a material constituting a substrate.

20. The method for manufacturing the transistor according to claim 19, further comprising: an annealing step of performing annealing at the temperature lower than the softening point after the gate insulating film forming step.

Description

BRIEF DESCRIPTION OF DRAWINGS

[0008] FIG. 1 is a schematic cross-sectional view of an example of a thin film transistor according to the present embodiment.

[0009] FIG. 2 is a diagram showing transistor characteristics of the thin film transistor manufactured in Example 1.

[0010] FIG. 3 is a diagram showing transistor characteristics of the thin film transistor manufactured in Example 2.

[0011] FIG. 4 is a diagram showing transistor characteristics of the thin film transistor manufactured in Example 3.

[0012] FIG. 5 is a diagram showing transistor characteristics of the thin film transistor manufactured in Example 4.

[0013] FIG. 6 is a diagram showing transistor characteristics of the thin film transistor manufactured in Comparative Example 1.

[0014] FIG. 7 is a diagram showing transistor characteristics of the thin film transistor manufactured in Comparative Example 2.

DESCRIPTION OF EMBODIMENTS

[0015] <Thin Film Transistor>

[0016] The present embodiment is a thin film transistor including a gate electrode, a gate insulating film, a semiconductor film, a source electrode, and a drain electrode.

[0017] In the present embodiment, the gate insulating film is a laminated film in which a SiO.sub.x film and a SiC.sub.yN.sub.z film are alternately laminated.

[0018] A thin film transistor 1 shown in FIG. 1 is a bottom-gate type thin film transistor formed on a surface of a substrate 11. The thin film transistor 1 includes a gate electrode 12, a gate insulating film 13, a semiconductor film 14, a source electrode 15a, and a drain electrode 15b.

[0019] Hereinafter, each configuration thereof will be described.

[0020] <<Substrate>>

[0021] Examples of a material of the substrate 11 include metals, crystalline materials, amorphous materials, conductors, semiconductors, insulators, fibers, glass, ceramics, zeolites, plastics, and thermosetting and thermoplastic materials. In addition, the substrate 11 may be an optical element, a coated substrate, a film, or the like.

[0022] Examples of the crystalline material include a single crystalline material, a polycrystalline material, or a partially crystalline material.

[0023] Examples of the thermoplastic material include polyacrylate, polycarbonate, polyurethane, polystyrene, cellulose polymer, polyolefin, polyamide, polyimide, polyester, polyphenylene, polyethylene, polyethylene terephthalate, polyethylene naphthalate, polypropylene, ethylene vinyl copolymer, and polyvinyl chloride. These materials may be doped.

[0024] In the present embodiment, polyimide or polyethylene naphthalate is preferable as the material of the substrate 11.

[0025] The softening point of the polyimide is 290° C. The softening point of polyethylene naphthalate is 120° C.

[0026] In the present embodiment, the substrate 11 is preferably a flexible substrate.

[0027] Here, the “flexibility” refers to a property that allows the substrate 11 to bend even when a force roughly equal to its own weight is applied to the substrate 11 without disconnecting or breaking.

[0028] In addition, the property of allowing the substrate 11 to be curved by the force roughly equal to its own weight is also included in the concept of flexibility. In the present embodiment, the flexibility of the substrate 11 varies depending on the material, size, thickness, environment such as temperature, and the like of the substrate 11.

[0029] As the flexible substrate 11, a substrate made of a resin material is preferable.

[0030] As the substrate 11, a long substrate can be used. Further, in the present embodiment, the substrate 11 may be formed in a long shape by connecting a plurality of unit substrates.

[0031] <<Gate Electrode>>

[0032] The gate electrode 12 is formed on the surface of the substrate 11. The gate electrode 12 has conductivity. A material constituting the gate electrode 12 is not particularly limited. In the present embodiment, examples of the material of the gate electrode 12 include Al, Mo, Cu, Ti, Au, and Ni.

[0033] The gate electrode 12 may be a laminate in which these materials are used alone or a laminate in which two or more materials are used in combination.

[0034] Further, an alloy containing these materials may be used. Examples of the alloy used for the gate electrode 12 include an alloy of nickel and phosphorus.

[0035] A shape of the gate electrode 12 is not particularly limited, but is preferably a square shape in a plan view which is a channel length direction and a channel width direction of the thin film transistor, from the viewpoint of controllability of the channel length and channel width.

[0036] A size of the gate electrode 12 may be any size as long as it can secure the channel length and channel width of the thin film transistor.

[0037] Here, the channel length direction of the thin film transistor is a facing direction of the source electrode 15a and the drain electrode 15b of the thin film transistor.

[0038] Further, the channel width direction of the thin film transistor is a direction orthogonal to the channel length direction of the thin film transistor and parallel to the surface of the substrate 11.

[0039] An average thickness of the gate electrode 12 is, for example, 50 nm or more and 500 nm or less, and 100 nm or more and 400 nm or less.

[0040] In order to improve coverage of the gate insulating film 13, a cross section of the gate electrode 12 in a thickness direction may have a tapered shape that expands toward the substrate 11. When the gate electrode 12 has the tapered shape, the taper angle is preferably 30° or more and 40° or less.

[0041] <<Gate Insulating Film>>

[0042] The gate insulating film 13 is formed on one surface of the substrate 11 so as to cover the gate electrode 12. In the present embodiment, the surface of the substrate 11 on which the gate electrode 12 is formed is referred to as an upper main surface. In the present embodiment, the gate insulating film 13 is a laminated film in which a SiO.sub.x film and a SiC.sub.yN.sub.z film are alternately laminated.

[0043] The x of the SiO.sub.x film is preferably 1.7 or more and 2.4 or less, and more preferably 1.9 or more and 2.1 or less.

[0044] The y of the SiC.sub.yN.sub.z film is preferably 1.0 or more and 3.5 or less, and more preferably 1.0 or more and 2.0 or less.

[0045] The z of the SiC.sub.yN.sub.z film is preferably more than 0 and 1.0 or less, and more preferably 0.2 or more and 0.7 or less.

[0046] The total number of films constituting the laminated film is 3 or more and 18 or less, preferably 4 or more and 16 or less. In the present embodiment, the total number of films constituting the laminated film may be an odd number or an even number, but more preferably an even number.

[0047] When the total number of films constituting the laminated film is an odd number, a layer in contact with the semiconductor film 14 is preferably formed to be the SiO.sub.x film. That is, the laminated film preferably includes the SiO.sub.x film, the SiC.sub.yN.sub.z film, and the SiO.sub.x film in this order from a side of the substrate 11.

[0048] The laminated film preferably has the SiC.sub.yN.sub.z film and the SiO.sub.x film which are alternately formed on the gate electrode 12. In addition, the layer in contact with the semiconductor film 14 is preferably formed to be the SiO.sub.x film.

[0049] That is, in a case of the bottom-gate type, the uppermost layer of the laminated film on the semiconductor film 14 side is preferably formed to be the SiO.sub.x film.

[0050] That is, in a case of a top-gate type, the lowermost layer of the laminated film on the semiconductor film 14 side is preferably formed to be the SiO.sub.x film.

[0051] The SiO.sub.x film has a barrier property against impurities that affect thin film transistor characteristics, such as water (H.sub.2O) and hydrogen (H.sub.2). In the present embodiment, an interface of the SiO.sub.x film is increased by forming the laminated film with the layer configuration described above. These impurities are trapped at each interface. Therefore, the barrier property is improved, and the impurities are less likely to diffuse to the semiconductor film. As a result, a highly reliable device can be realized. Further, flexibility is imparted because the laminated film has the SiC.sub.yN.sub.z film, and a device having improved resistance against stress can be obtained.

[0052] As a conventional method for forming a SiO.sub.2-based thin film by a plasma CVD apparatus, a method for forming a film at a high temperature of about 200° C. to 300° C. is an exemplary example, from the viewpoint of improved insulating property of the gate insulating film. In addition, a method for essentially performing a post-annealing treatment at a high temperature is an exemplary example.

[0053] When a heat treatment at a high temperature is essential as in the conventional method, selectivity of the material of the substrate is lowered, resulting in a problem that a resin substrate cannot be used and the like.

[0054] According to the present embodiment, it is possible to obtain a gate insulating film with a high quality at a treatment temperature of, for example, lower than 200° C. by forming a composite insulating film in which the SiC.sub.yN.sub.z film and the SiO.sub.x film are alternately formed, without undergoing the heat treatment at a high temperature.

[0055] Moreover, by forming the laminated film with the layer configuration described above, it is possible to reduce a stress of the gate insulating film. Therefore, the laminated film can be applied to a flexible substrate that can be repeatedly bent.

[0056] The thickness of each film constituting the laminated film is 25 nm or more and 150 nm or less, preferably 26 nm or more and 90 nm or less, and more preferably 27 nm or more and 80 nm or less.

[0057] When the thickness of each film constituting the laminated film is the lower limit value or more, a high insulating property can be exhibited. In addition, when the thickness of each film constituting the laminated film is the upper limit value or less, the hysteresis can be made smaller or eliminated, and a highly reliable device can be obtained.

[0058] In the present embodiment, the total thickness of the laminated film is preferably 500 nm or less. In addition, the thickness of each film constituting the laminated film is preferably substantially the same. The thickness of each layer may be appropriately adjusted according to the total number of films. In the present embodiment, the thickness of each film constituting the laminated film is preferably substantially the same.

[0059] A shape of the gate insulating film 13 is not limited as long as the gate electrode 12 is covered, and for example, the gate insulating film 13 may cover the entire surface of the substrate 11.

[0060] The gate insulating film is a laminated film in which SiO.sub.x films and SiC.sub.yN.sub.z films are alternately formed, and confirmation can be made by the following method that the total number of films constituting the laminated film is 3 or more and 18 or less, and the thickness of each film constituting the laminated film is 25 nm or more and 150 nm or less.

[0061] The concentration of oxygen atoms in each layer constituting the gate insulating film can be measured by composition analysis using Rutherford backscattering spectrometry and hydrogen forward scattering spectrometry. The Rutherford backscattering spectrometry may be abbreviated as “RBS” and the hydrogen forward scattering spectrometry may be abbreviated as “HFS”.

[0062] The silicon atom concentration and the carbon atom concentration in each layer constituting the gate insulating film can also be measured by the RBS or HFS.

[0063] The concentration of hydrogen atoms, which are impurities present in each layer constituting the gate insulating film, can be measured by the HFS.

[0064] In the RBS, an object to be measured is irradiated with high-speed ions (He.sup.+, H.sup.+, and the like), and measures the energy and yield of scattered ions for a part of incident ions that are subjected to be elastically scattered (Rutherford scattered) by atomic nuclei of the object to be measured. The energy of scattered ions varies depending on the mass and position (depth) of the target atom. Therefore, an element composition of the object to be measured in the depth direction can be obtained from the energy and yield of the scattered ions.

[0065] In the HFS, the object to be measured is irradiated with the high-speed ions (He.sup.+ and the like) to utilize hydrogen in the object to be measured which is scattered forward by elastic recoil and obtain depth distribution in the element from the energy and yield of the recoiled hydrogen.

[0066] The presence of the SiO.sub.x film can be confirmed by measuring the silicon atom concentration and the oxygen atom concentration by the RBS or HFS. In addition, the presence of the SiC.sub.yN.sub.z film can be confirmed by measuring the silicon atom concentration, the carbon atom concentration, and a nitrogen atom concentration by the RBS or HFS. By confirming these distributions, it can be confirmed whether or not the laminated film has the SiO.sub.x film and the SiC.sub.yN.sub.z film which are alternately formed. In addition, the total number of films constituting the laminated film can be confirmed.

[0067] <<Semiconductor Film>>

[0068] As a semiconductor material constituting the semiconductor film 14, IGZO (In—Ga—Zn—O-based) having high carrier mobility and relative easiness of film formation, and a transparent amorphous oxide semiconductor (TAOS), zinc oxide (ZnO), nickel oxide (NiO), tin oxide (SnO.sub.2), titanium oxide (TiO.sub.2), vanadium oxide (VO.sub.2), indium oxide (In.sub.2O.sub.3), and strontium titanate (SrTiO.sub.3) can be exemplary examples.

[0069] Further, an organic semiconductor may be used as the semiconductor material constituting the semiconductor film 14. As a material of the organic semiconductor, a p-type semiconductor, fullerene, or an n-type semiconductor can be used.

[0070] Examples of the p-type semiconductor include copper phthalocyanine (CuPc), pentacene, rubrene, tetracene, and poly(3-hexylthiophene-2,5-diyl (P3HT)).

[0071] As the fullerene, C60 is an exemplary example.

[0072] As the n-type semiconductor, a perylene derivative such as N,N′-dioctyl-3,4,9,10-perylene terracarboxylic dimide (PTCDI-C8H) is an exemplary example.

[0073] Among the semiconductor materials constituting the semiconductor film 14, soluble pentacene and an organic semiconductor polymer are soluble in an organic solvent. Therefore, a semiconductor film can be formed in a wet process. An example of the soluble pentacene includes 6,13-bis(triisopropylsilylethynyl) (TIPS) pentacene.

[0074] Examples of the organic semiconductor polymer includes oly(3-hexylthiophene-2,5-diyl) (P3HT) and the like.

[0075] Toluene is preferably used as the organic solvent.

[0076] <<Source Electrode and Drain Electrode>>

[0077] The source electrode 15a and the drain electrode 15b cover a part of the gate insulating film 13, and are electrically connected to the semiconductor film 14 at both ends of a channel of the thin film transistor 1.

[0078] A drain current of the thin film transistor 1 flows between the source electrode 15a and the drain electrode 15b according to a voltage between the gate electrode 12 and the source electrode 15a and a voltage between the source electrode 15a and the drain electrode 15b.

[0079] A material constituting the source electrode 15a and the drain electrode 15b is not particularly limited as long as it has conductivity, and for example, the same material as the gate electrode 12 can be used.

[0080] Examples of an average thickness of the source electrode 15a and the drain electrode 15b include 100 nm or more and 400 nm or less, and 150 nm or more and 300 nm or less.

[0081] Examples of a facing distance between the source electrode 15a and the drain electrode 15b, that is, the channel length of the thin film transistor 1 include 5 μm or more and 50 μm or less, and 10 μm or more and 30 μm or less.

[0082] Examples of a length in the channel width direction between the source electrode 15a and the drain electrode 15b, that is, the channel width of the thin film transistor 1 is 100 μm or more and 300 μm or less, and 150 μm or more and 250 μm or less.

[0083] Although a case of the bottom-gate type thin film transistor has been described as the thin film transistor 1, the top-gate type thin film transistor may be used as another embodiment.

[0084] (Characteristics of Thin Film Transistor)

[0085] A lower limit of a threshold voltage of the thin film transistor in the present embodiment is preferably −1 V, and more preferably 0 V. On the other hand, an upper limit of the threshold voltage of the thin film transistor is preferably 3 V, and more preferably 2 V.

[0086] <Electronic Device>

[0087] The present embodiment is an electronic device including the thin film transistor of the present embodiment described above. As the electronic device, a display element such as a liquid crystal display element is an exemplary example.

[0088] <Method for Manufacturing Thin Film Transistor>

[0089] The present embodiment relates to a method for manufacturing a thin film transistor.

[0090] The method for manufacturing a thin film transistor of the present embodiment includes a gate insulating film forming step of alternately forming a SiO.sub.x film and a SiC.sub.yN.sub.z film by a plasma CVD method to form a gate insulating film.

[0091] In the gate insulating film forming step, a film formation temperature is a temperature of lower than the softening point of the material that constitutes the substrate.

[0092] The method for manufacturing a thin film transistor of the present embodiment preferably includes a gate electrode film forming step, a gate insulating film forming step, a semiconductor film forming step, a source and drain electrode-film forming step, and an annealing step in this order.

[0093] <Gate Electrode Film Forming Step>

[0094] In the gate electrode film forming step, a film of the gate electrode 12 is formed on the surface of the substrate 11.

[0095] Specifically, first, a conductive film is formed on the surface of the substrate 11 by a known method, for example, a sputtering method so as to have a desired thickness. Conditions for forming the conductive film by the sputtering method are not particularly limited, but for example, conditions can be set, such as a substrate temperature of 20° C. or higher and 50° C. or lower, a film formation power density of 3 W/cm.sup.2 or more and 4 W/cm.sup.2 or less, a pressure of 0.1 Pa or more and 0.4 Pa or less, and a carrier gas of Ar.

[0096] Next, the gate electrode 12 is formed by patterning the conductive film. The patterning method is not particularly limited, and for example, a method for performing wet etching after performing photolithography can be used. In this case, it is preferable to etch a cross section of the gate electrode 12 into a tapered shape that expands toward the substrate 11 so as to improve coverage of the gate insulating film 13.

[0097] <Gate Insulating Film Forming Step>

[0098] In the gate insulating film forming step, the gate insulating film 13 is formed on a surface side of the substrate 11 so as to cover the gate electrode 12.

[0099] Specifically, first, a SiC.sub.yN.sub.z film forming step of forming a SiC.sub.yN.sub.z film on the substrate 11 and a SiO.sub.x film forming step of forming a SiO.sub.x film on the SiC.sub.yN.sub.z film are performed in this order. By alternately repeating the SiC.sub.yN.sub.z film forming step and the SiO.sub.x film forming step, a laminated film in which the SiC.sub.yN.sub.z film and the SiO.sub.x film are alternately laminated can be formed.

[0100] The SiC.sub.yN.sub.z film and the SiO.sub.x film can be formed by a chemical vapor deposition (CVD) method using, for example, a film forming apparatus described in Japanese Patent No. 5967983.

[0101] [SiC.sub.yN.sub.z Film Forming Step]

[0102] In the SiC.sub.yN.sub.z film forming step, a raw material gas is used to form the SiC.sub.yN.sub.z film on the substrate 11 by the plasma CVD method. As the raw material gas used in the SiC.sub.yN.sub.z film forming step, a raw material gas composed of an organosilicon compound and a compound containing a hydrogen atom is an exemplary example. Specifically, a raw material gas containing hexamethyldisilazane can be used. Hexamethyldisilazane is abbreviated as “HMDS”.

[0103] Specifically, for example, the SiC.sub.yN.sub.z film is formed by introducing a mixed gas of a hydrogen gas and an argon gas and the raw material gas such as HMDS into a film forming chamber. An example of the introduction speed of the raw material gas is 3 sccm or more and 100 sccm or less.

[0104] The mixed gas and the raw material gas are preferably introduced into the film forming chamber at the same time. An example of the introduction speed of the mixed gas is 20 sccm or more and 1,000 sccm or less.

[0105] By generating plasma while introducing the mixed gas and the raw material gas, a surface reaction proceeds on the surface of the substrate 11, and the SiC.sub.yN.sub.z film is formed on the substrate 11.

[0106] [SiO.sub.x Film Forming Step]

[0107] In the SiO.sub.x film forming step, a raw material gas is used to form SiO.sub.x on the SiC.sub.yN.sub.z film by the plasma CVD method. As the raw material gas used in the SiO.sub.x film forming step, a raw material gas composed of an organosilicon compound and a compound containing an oxygen atom is an exemplary example. Specifically, a raw material gas containing hexamethyldisilazane can be used. Hexamethyldisilazane is referred to as “HMDS”.

[0108] Specifically, for example, an oxygen gas and the raw material gas such as HMDS are introduced into the film forming chamber to form the SiO.sub.x film. An example of the introduction speed of the raw material gas is 3 sccm or more and 20 sccm or less.

[0109] An example of the introduction speed of the oxygen gas is 20 sccm or more and 1,000 sccm or less.

[0110] By generating plasma while introducing the oxygen gas and the raw material gas, a surface reaction proceeds on the surface of the SiC.sub.yN.sub.z film, and the SiO.sub.x film is formed on the SiC.sub.yN.sub.z film.

[0111] Before forming the SiC.sub.yN.sub.z film on the substrate 11, a base film may be formed on the substrate 11 as an optional step. When forming the base film, adhesion between the gate electrode and the SiC.sub.yN.sub.z film and the substrate and the SiC.sub.yN.sub.z film can be improved.

[0112] In the present embodiment, as the base film that may be formed as an arbitrary step, a film formed by the plasma CVD method and containing at least a silicon atom and an oxygen atom is an exemplary example. The base film preferably has a concentration of oxygen atoms of 10 to 35 element %.

[0113] In the present embodiment, the gate insulating film forming step is performed at a temperature lower than the softening point of the material constituting the substrate.

[0114] Specifically, a temperature lower than the softening point of the material constituting the substrate by 20° C. or higher is preferable, and a temperature lower than the softening point of the material constituting the substrate by 40° C. or higher lower is more preferable.

[0115] In the present embodiment, the composite insulating film in which the SiC.sub.yN.sub.z film and the SiO.sub.x film are alternately formed is obtained, and a low-temperature film at a temperature lower than the softening point of the material constituting the substrate can thus be formed.

[0116] <Semiconductor Film Forming Step>

[0117] In the semiconductor film forming step, the semiconductor film 14 is formed on the surface of the gate insulating film 13 and directly on the gate electrode 12.

[0118] Specifically, the semiconductor film 14 is formed by forming a semiconductor layer on the surface of the gate insulating film 13 and then patterning the semiconductor layer.

[0119] (Formation of Semiconductor Layer)

[0120] Specifically, first, a semiconductor layer is formed on the surface of the gate insulating film 13 by the sputtering method using, for example, a known sputtering apparatus. The semiconductor layer having excellent in-plane uniformity of its components or thickness can be easily formed using the sputtering method.

[0121] As a sputtering target used in the sputtering method, an oxide target (IGZO target) containing In, Ga, and Zn can be an exemplary example.

[0122] Conditions for forming the semiconductor layer by the sputtering method are not particularly limited, but for example, conditions can be set, such as a substrate temperature of 20° C. or higher and 50° C. or lower, a film formation power density of 2 W/cm.sup.2 or more and 3 W/cm.sup.2 or less, a pressure of 0.1 Pa or more and 0.3 Pa or less, and a carrier gas of Ar. Further, it is preferable to contain oxygen in the atmosphere as an oxygen source. A content of oxygen in the atmosphere can be 3 vol % or more and 5 vol % or less.

[0123] The method for forming the semiconductor layer is not limited to the sputtering method, and a chemical film forming method such as a coating method may be used.

[0124] (Patterning)

[0125] Next, the semiconductor film 14 is formed by patterning the semiconductor layer. The method for patterning a semiconductor layer is not particularly limited, and for example, a method for performing wet etching after performing photolithography can be used.

[0126] <Source and Drain Electrode Film Forming Step>

[0127] In the source and drain electrode film forming step, the source electrode 15a and the drain electrode 15b that are electrically connected to the semiconductor film 14 are formed at both ends of the channel of the thin film transistor.

[0128] Specifically, first, a conductive film is formed on the surface of the substrate 11 by a known method, for example, a sputtering method so as to have a desired thickness. Conditions for forming the conductive film by the sputtering method are not particularly limited, but for example, conditions can be set, such as a substrate temperature of 20° C. or higher and 50° C. or lower, a film formation power density of 3 W/cm.sup.2 or more and 4 W/cm.sup.2 or less, a pressure of 0.1 Pa or more and 0.4 Pa or less, and a carrier gas of Ar.

[0129] Next, the source electrode 15a and the drain electrode 15b are formed by patterning the conductive film. The patterning method is not particularly limited, and for example, a method for performing wet etching after performing photolithography can be used.

[0130] <Annealing Step>

[0131] The method for manufacturing a thin film transistor preferably further includes an annealing step of annealing at 300° C. or lower after forming the gate insulating film.

[0132] The annealing temperature is more preferably 200° C. or lower.

[0133] The annealing step is preferably performed for 10 minutes or longer and 8 hours or shorter at the temperature described above.

EXAMPLES

[0134] Hereinafter, the present invention will be specifically described with reference to Examples, but the present invention is not limited to the following Examples.

Example 1

[0135] [Gate Electrode Film Forming Step]

[0136] A polyimide film having a thickness of 125 μm (softening point: 290° C.) was used as a substrate 11. A metal mask (SUS430 having a thickness of 0.08 mm) having a pattern corresponding to the gate electrode was placed on one surface of the cleaned substrate 11, and a conductive film (Al film: 50 nm), which was a material for forming a gate electrode 12, was formed by a resistance heating vacuum deposition method. As a result, the gate electrode 12 was formed on the substrate 11.

[0137] [Gate Insulating Film Forming Step]

[0138] Next, a gate insulating film 13 was formed on the entire upper main surface of the substrate 11 so as to cover the gate electrode 12. The gate insulating film 13 had a SiO.sub.x film and a SiC.sub.yN.sub.z film which are alternately formed by the following steps using a chemical vapor deposition (CVD) method.

[0139] [Gate Insulating Film Forming Step]

[0140] In a gate insulating film forming step, the gate insulating film 13 was formed on a surface side of the substrate 11 so as to cover the gate electrode 12.

[0141] The SiC.sub.yN.sub.z film and the SiO.sub.x film were formed by the chemical vapor deposition (CVD) method using a film forming apparatus described in Japanese Patent No. 5967983.

[0142] [SiC.sub.yN.sub.z Film Forming Step]

[0143] A raw material gas was used to form the SiC.sub.yN.sub.z film on the substrate 11 by a plasma CVD method. In a SiC.sub.yN.sub.z film forming step, a HMDS gas was used as the raw material gas.

[0144] A mixed gas of a hydrogen gas and an argon gas and the HMDS gas were introduced into a film forming chamber to form the SiC.sub.yN.sub.z film. An introduction speed of the raw material gas was 3 to 100 sccm.

[0145] The mixed gas and the raw material gas were introduced into the film forming chamber at the same time. An introduction speed of the mixed gas was 20 to 1,000 sccm.

[0146] The SiC.sub.yN.sub.z film was formed on the substrate 11 by generating plasma while introducing the mixed gas and the raw material gas. The plasma was generated with a plasma power of 1 to 20 kW until the SiC.sub.yN.sub.z film had a predetermined thickness.

[0147] [SiO.sub.x Film Forming Step]

[0148] The raw material gas was used to form the SiO.sub.x film on the SiC.sub.yN.sub.z film by the plasma CVD method. In the SiO.sub.x film forming step, the HMDS gas was used as the raw material gas.

[0149] An oxygen gas and the HMDS gas were introduced into the film forming chamber to form the SiO.sub.x film. An introduction speed of the HMDS gas was 10 to 100 sccm.

[0150] An introduction speed of the oxygen gas was 20 to 1,000 sccm.

[0151] The SiO.sub.x film was formed on the SiC.sub.yN.sub.z film by generating plasma while introducing the oxygen gas and the raw material gas. The plasma was generated with a plasma power of 1 to 20 kW until the SiO.sub.x film had a predetermined thickness.

[0152] A film formation temperature in the gate insulating film forming step was 82° C.

[0153] In Example 1, one set of the SiC.sub.yN.sub.z film forming step and the SiO.sub.x film forming step was counted as one time, and was performed twice to form a four-layered gate insulating film. Here, one time of performing the SiC.sub.yN.sub.z film forming step and the SiO.sub.x film forming step was counted as one time.

[0154] When the four-layered gate insulating film 13 manufactured in Example 1 was analyzed by RBS or HFS, it was found that y was 1.0 or more and 2.0 or less and z was 0.2 or more and 0.7 in the formed SiC.sub.yN.sub.z film. In the formed SiO.sub.x film, x was 1.9 or more and 2.1 or less.

[0155] When the four-layered gate insulating film 13 manufactured in Example 1 was analyzed by the RBS or HFS, it was found that it is configured in four layers of a SiC.sub.yN.sub.z film having a thickness of 100 nm, a SiO.sub.x film having a thickness of 100 nm, a SiC.sub.yN.sub.z film having a thickness of 100 nm, and a SiO.sub.x film having a thickness of 100 nm, from the side of the gate electrode 12.

[0156] [Semiconductor Film Forming Step]

[0157] Next, a semiconductor film 14 was formed on the gate insulating film 13.

[0158] An oxide semiconductor film, which was the material for forming the semiconductor film 14, was formed by a sputtering method using an InGaZNO target [In.sub.2O.sub.3.Ga.sub.2O.sub.3.(ZnO).sub.2] which has an atomic composition ratio In:Ga:Zn of 2:2:1. The semiconductor film 14 was patterned using a metal mask in the same manner as the gate electrode 12.

[0159] As a result, an InGaZnO film having a thickness of 20 nm was formed.

[0160] [Source Electrode and Drain Electrode Film Forming Step]

[0161] Next, a conductive film (Al film: 50 nm), which was a material of a source electrode 15a and a drain electrode 15b, was formed by the resistance heating vacuum deposition method. The film formation of the source electrode and the drain electrode was performed via the metal mask to obtain the source electrode 15a and the drain electrode 15b having a desired pattern shape.

[0162] The source electrode 15a and the drain electrode 15b were each formed to overlap the gate insulating film 13 and the semiconductor film 14.

[0163] A part of the semiconductor film 14 was formed to be exposed between the source electrode 15a and the drain electrode 15b.

[0164] [Annealing Step]

[0165] After forming the gate insulating film, an annealing step was further performed at 105° C. or lower for 8 hours. As a result, a thin film transistor of Example 1 was obtained.

Example 2

[0166] A thin film transistor was manufactured in the same manner as in Example 1, except that one set of the SiC.sub.yN.sub.z film forming step and the SiO.sub.x film forming step was counted as one time, and performed four times, thereby forming, from the side of the gate electrode 12, an eight-layered gate insulating film 13 of a SiC.sub.yN.sub.z film having a thickness of 50 nm, a SiO.sub.x film having a thickness of 50 nm, a SiC.sub.yN.sub.z film having a thickness of 50 nm, a SiO.sub.x film having a thickness of 50 nm, a SiC.sub.yN.sub.z film having a thickness of 50 nm, a SiO.sub.x film having a thickness of 50 nm, a SiC.sub.yN.sub.z film having a thickness of 50 nm, and a SiO.sub.x film having a thickness of 50 nm.

Example 3

[0167] A thin film transistor was manufactured in the same manner as in Example 1, except that one set of the SiC.sub.yN.sub.z film forming step and the SiO.sub.x film forming step was counted as one time, and performed seven times, thereby forming a fourteen-layered gate insulating film 13 obtained by alternately forming, from the side of the gate electrode 12, SiC.sub.yN.sub.z films having a thickness of 30 nm and SiO.sub.x films having a thickness of 30 nm in this order.

Example 4

[0168] A thin film transistor was manufactured in the same manner as in Example 1, except that the SiO.sub.x film forming step, the SiC.sub.yN.sub.z film forming step, and the SiO.sub.x film forming step were performed in this order, thereby forming a three-layered gate insulating film 13 of a SiO.sub.x film having a thickness of 50 nm, a SiC.sub.yN.sub.z film having a thickness of 300 nm, and a SiO.sub.x film having a thickness of 50 nm, from the side of the gate electrode 12.

Comparative Example 1

[0169] A thin film transistor was manufactured in the same manner as in Example 1, except that the gate insulating film 13, which was a SiC.sub.yN.sub.z film having a thickness of 400 nm, was formed.

Comparative Example 2

[0170] A thin film transistor was manufactured in the same manner as in Example 1, except that one set of the SiC.sub.yN.sub.z film forming step and the SiO.sub.x film forming step was counted as one time, and performed ten times, thereby forming a twenty-layered gate insulating film 13 obtained by alternately forming, from the side of the gate electrode 12, SiC.sub.yN.sub.z films having a thickness of 20 nm and SiO.sub.x films having a thickness of 20 nm in this order.

[0171] <Evaluation of Thin Film Transistor Characteristics>

[0172] Characteristics of the thin film transistors manufactured in Examples 1 to 4 and Comparative Examples 1 and 2 were evaluated.

[0173] The thin film transistors manufactured in Examples 1 to 4 and Comparative Examples 1 and 2 were evaluated for a transistor performance using a semiconductor parameter analyzer (4200A-SCS, manufactured by Keithley).

[0174] A voltage Vds between the source and drain electrodes was set to 10 V, and a gate voltage was changed from Vg=−10 V to +20 V to evaluate current-voltage characteristics (transmission characteristics).

[0175] The results thereof are shown in FIGS. 2 to 7, and the results of Examples 1 to 4 are each shown in FIGS. 2 to 5. The results of Comparative Examples 1 and 2 are each shown in FIGS. 6 and 7.

[0176] In FIGS. 2 to 7, a vertical axis represents the drain current, and a horizontal axis represents the gate voltage.

[0177] In Examples 1 to 4 shown in FIGS. 2 to 5, a lower limit value of the threshold voltage was near 0 V, and negative shift of the threshold voltage was suppressed. Further, in Examples 1 to 4 shown in FIGS. 2 to 5, good thin film transistor characteristics with small hysteresis were obtained.

[0178] Among them, it was confirmed that in Example 2 shown in FIG. 3 and Example 3 shown in FIG. 4, hysteresis did not occur and reliability of the initial characteristics was enhanced.

[0179] On the other hand, in Comparative Example 1, the lower limit value of the threshold voltage was shifted to the minus side, as shown in FIG. 6. Further, Comparative Example 2 shown in FIG. 7 had a malfunction. It is considered that this is because the thickness of each layer constituting the gate insulating film was too thin.

REFERENCE SIGNS LIST

[0180] 1: Thin film transistor [0181] 11: Substrate [0182] 12: Gate electrode [0183] 13: Gate insulating film [0184] 14: Semiconductor film (oxide semiconductor) [0185] 15a: Source electrode [0186] 15b: Drain electrode