Integrated circuit comprising an NLDMOS transistor

Abstract

An integrated circuit includes an N-type laterally diffused metal-oxide semiconductor (NLDMOS) transistor including an active semiconductor substrate region having P-type conductivity. The integrated circuit further includes a buried semiconductor region having N+-type conductivity underneath the active substrate region. The buried semiconductor region is more heavily doped than the active semiconductor substrate region.

Claims

1. An integrated circuit including an N-type laterally diffused metal-oxide semiconductor (NLDMOS) transistor, comprising: a P-type semiconductor substrate; a semiconductor well with N-type conductivity over said P-type semiconductor substrate; wherein said semiconductor well includes a trench extending through a thickness of said semiconductor well; a buried semiconductor region having N+-type conductivity located at a bottom of said trench; an additional region made of an epitaxial material with N-type conductivity situated within the trench and over said buried semiconductor region; an active semiconductor body region of said NLDMOS transistor having P-type conductivity situated within the trench and over said additional region; wherein an at./cm.sup.3 dopant concentration in the buried semiconductor region is greater than an at./cm.sup.3 dopant concentration in the active semiconductor body region; wherein the buried semiconductor region is situated at an interface between the P-type semiconductor substrate and the additional region; a source region of said NLDMOS transistor having an N-type conductivity in said active semiconductor body region; and a drain region of said NLDMOS transistor having an N-type conductivity contained within said semiconductor well.

2. The circuit according to claim 1, further comprising: an NPN-type bipolar transistor; and a buried semiconductor layer having N-type conductivity located underneath the NPN-type bipolar transistor; wherein the buried semiconductor layer underneath the NPN-type bipolar transistor and the buried semiconductor region at the bottom of said trench are situated at a same depth and have a same dopant concentration.

3. An integrated circuit transistor including a source region, a body region and a drain region, comprising: a semiconductor substrate doped with a first conductivity type; a semiconductor well doped with a second conductivity type over said semiconductor substrate, wherein said semiconductor well supports said drain region, and wherein said semiconductor well includes a trench extending through a thickness of said semiconductor well; an active semiconductor substrate region doped with the first conductivity type located within said trench, wherein said active semiconductor substrate region provides the body region and supports the source region; a buried semiconductor region doped with the second conductivity type and located at a bottom of said trench level with an interface between the semiconductor substrate and the semiconductor well; and an additional region doped with the second conductivity type situated within said trench between the active semiconductor substrate region and the buried semiconductor region.

4. The integrated circuit of claim 3, wherein the semiconductor well and the buried semiconductor region preclude direct physical contact between the additional region and the semiconductor substrate.

5. The integrated circuit of claim 3, wherein an at./cm.sup.3 dopant concentration in the buried semiconductor region is greater than an at./cm.sup.3 dopant concentration in the active semiconductor substrate region.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Other advantages and features of the invention will become apparent on examining the detailed description of completely non-limiting modes of implementation and embodiments and the appended drawings, in which:

(2) FIG. 1 shows a structure of a known NLDMOS transistor;

(3) FIG. 2 shows an integrated circuit comprising an NLDMOS transistor;

(4) FIG. 3 shows an example of a method for manufacturing an integrated circuit such as shown in FIG. 2;

(5) FIG. 4 shows an integrated circuit comprising an NPN-type bipolar transistor and an NLDMOS transistor 21 having a structure identical to that shown in FIG. 2; and

(6) FIG. 5 shows an example of a method for manufacturing.

DETAILED DESCRIPTION

(7) FIG. 2 shows an integrated circuit 20 according to one embodiment comprising an N-type laterally diffused metal-oxide semiconductor transistor, called NLDMOS transistor 21.

(8) The NLDMOS transistor 21 is formed on a semiconductor substrate 22 having P-type conductivity. For example, the semiconductor substrate 22 has a dopant concentration of the order of 10.sup.15 at./cm.sup.3.

(9) More particularly, the NLDMOS transistor 21 is formed in a well 24 with N-type conductivity that is incorporated into the P-type semiconductor substrate 22. For example, the well 24 has a dopant concentration of the order of 10.sup.17 at./cm.sup.3. The well 24 extends downwards from a front face 23.

(10) More particularly, the NLDMOS transistor 21 comprises a drain region 25 with N-type conductivity. The drain region 25 is heavily doped in order to make it easier to create contact.

(11) The NLDMOS transistor 21 further comprises an N.sup.+-doped source region 29 and a P-type active substrate region (body) 27 and a P.sup.+-doped substrate contact zone 31 formed in the active substrate region 27. For example, the active substrate region 27 has a dopant concentration of the order of 10.sup.17 at./cm.sup.3. The source region 29 and substrate regions 27, 31 are connected together by a metallization 32.

(12) The NLDMOS transistor 21 also comprises two gate regions 33, 35 on top of the front face 23.

(13) The integrated circuit 20 also comprises an additional region 37 with N-type conductivity, situated underneath the active substrate region 27. This additional region 37 is laterally surrounded by the well 24. More particularly, this additional region 37 has a dopant concentration of the order of 10.sup.17 at./cm.sup.3.

(14) The additional region 37 extends downwards from the active substrate region 27 of the NLDMOS transistor 21 to a buried semiconductor region 38 with N-type conductivity, situated underneath said additional region 37. The buried semiconductor region 38 is doped with a dose of the order of 2×10.sup.19 at./cm.sup.3. The buried region 38 is therefore situated at the interface between the region 37 and the substrate 22.

(15) The buried N.sup.+-type region 38 makes it possible to increase the triggering voltage of the stray PNP bipolar transistor effect to a level high enough not to impair high-voltage operation of the NLDMOS transistor 21. In particular, the buried N.sup.+-type region 38 makes it possible to considerably reduce the current gain of the stray PNP structure (between the active substrate region 27 of the NLDMOS transistor 21 and the P-type semiconductor substrate 22). The buried N.sup.+-type region 38, due to its high doping, is thus used to reduce the stray PNP bipolar transistor effect, or even to prevent this stray PNP bipolar transistor effect from triggering when the NLDMOS transistor 21 is used in a high side driver.

(16) FIG. 3 shows an example of a method for manufacturing an integrated circuit 20 such as the one shown in FIG. 2. This manufacturing method comprises, after forming the well 24 in the substrate 22 in a conventional and known manner, a step 50 of forming a trench 39 in the well 24 by etching until reaching the substrate 22.

(17) The manufacturing method then comprises a step 51 of forming the buried semiconductor region 38 by implanting dopants in the substrate 22 at the bottom of the trench.

(18) The manufacturing method then comprises a step 52 of forming the additional region 37 through epitaxy.

(19) The manufacturing method then comprises a step 53 of forming the source, substrate and drain regions through dopant implantation.

(20) The manufacturing method then comprises a step 54 of forming the gate regions of the NLDMOS transistor 21.

(21) FIG. 4 shows an integrated circuit 20 comprising an NPN-type bipolar transistor 40 and an NLDMOS transistor 21 having a structure identical to the one described in FIG. 2. In particular, the bipolar transistor 40 and the NLDMOS transistor 21 are formed on the same semiconductor substrate 22 having a common region with P-type conductivity, such as the one described above. The NLDMOS transistor 21 is separated from the bipolar transistor 40 by a deep trench isolation (DTI) 48.

(22) The bipolar transistor 40, as is conventional, has an N.sup.+-type emitter region 44, a P.sup.+-doped extrinsic base region 43, a P-doped intrinsic base region 42, an extrinsic collector region 41 and an intrinsic collector region 45.

(23) The bipolar transistor 40 also has a buried layer 46 situated at the interface between the intrinsic collector 45 and the underlying substrate 22.

(24) The buried layer 46 of the bipolar transistor 40 and the buried region 38 of the NLDMOS transistor 21 are situated at the same depth with respect to a front face 23 and have the same dopant concentration.

(25) Specifically, as illustrated schematically in FIG. 5, in step 510, the buried semiconductor layer 46 underneath the bipolar transistor 40 and the buried semiconductor region 38 underneath each NLDMOS transistor 21 are formed at the same time.

(26) Forming the buried region 38 underneath the active substrate region 27 of the NLDMOS transistor 21 therefore does not require a dedicated additional step. Forming the buried region 38 underneath the active substrate region 27 of the NLDMOS transistor 21 is therefore inexpensive.

(27) Furthermore, the intrinsic collector region 45 of the bipolar transistor 40 and the additional region 37 situated underneath the NLDMOS transistor 21 are formed simultaneously.