Method for the nanoscale etching of a germanium-tin alloy (GeSn) for a FET transistor

Abstract

A method for the nanoscale etching of a layer of Ge.sub.1-xSn.sub.x on a carrier for a FET transistor, x being the concentration of tin in the GeSn alloy, the etching method includes a step of plasma-etching the layer of Ge.sub.1-xSn.sub.x using a mixture comprising dichlorine (Cl.sub.2) and dinitrogen (N.sub.2) and under an etching pressure lower than or equal to 50 mTorr, preferably lower than or equal to 10 mTorr. A method for producing a conduction channel on a carrier for a FET transistor, comprising a step of forming a layer of Ge.sub.1-xSn.sub.x on the carrier, the layer being produced by epitaxial growth, and a step of etching the layer of Ge.sub.1-xSn.sub.x according to the etching method. A conduction channel made of Ge.sub.1-xSn.sub.x for a FET transistor, the channel being obtained according to the production method, and a FET transistor comprising a plurality of conduction channels made of Ge.sub.1-xSn.sub.x.

Claims

1. A method for performing nanoscale etching of a layer of Ge.sub.1-xSn.sub.x on a carrier for a FET transistor, x being a concentration of tin and being higher than 10% and lower than 30%, the method comprising: a step of removing a chemical or native oxide from the tin; and a step of plasma-etching said layer of Ge.sub.1-xSn.sub.x using a mixture comprising dichlorine (Cl.sub.2) and dinitrogen (N.sub.2) and under an etching pressure lower than or equal to 50 mTorr, preferably lower than or equal to 10 mTorr; said step of removing being anterior to said step of plasma-etching.

2. The method according to claim 1, the etching pressure being lower than or equal to 5 mTorr.

3. The method according to claim 2, the etching pressure being lower than or equal to 2 mTorr for a concentration x of tin higher than or equal to 15%.

4. The method according to claim 1, the mixture further comprising dioxygen (O.sub.2).

5. The method according to claim 1, the step of removing consisting of an acid chemical attack, the acid preferably being hydrofluoric acid (HF) or hydrochloric acid (HCl).

6. The method according to claim 1, further comprising a step of depositing a mask on the layer of Ge.sub.1-xSn.sub.x, preferably a hard mask, for example a mask made of hydrogen silsesqwoxane (HSQ) resin, said deposition step coming before the step of plasma-etching the Ge.sub.1-xSn.sub.x.

7. The method according to claim 6, further comprising a step of removing the mask, said step of removing the mask coming after the step of plasma-etching the Ge.sub.1-xSn.sub.x.

8. A method for producing at least one conduction channel on a carrier for a FET transistor, said method comprising the following steps: a step of forming a layer of Ge.sub.1-xSn.sub.x on said carrier, said layer being produced by epitaxial growth; and a step of etching the layer of Ge.sub.1-xSn.sub.x produced according to the method described in claim 1.

9. The method according to claim 8, the carrier comprising a free surface, the free surface comprising a layer of Ge such that the layer of Ge.sub.1-xSn.sub.x is formed on the layer of Ge, the method further comprising a step of selectively plasma-etching the layer of Ge, said selective plasma-etching step preferably being performed using carbon tetrafluoride (CF.sub.4) and coming after the step of etching the Ge.sub.1-xSn.sub.x.

10. A conduction channel made of Ge.sub.1-xSn.sub.x for a FET transistor, the conduction channel being obtained according to the method of claim 8, the carrier comprising an etch bottom, the etch bottom around the etched layer of Ge.sub.1-xSn.sub.x being smooth, i.e. exhibiting a surface roughness lower than 2 nanometres, preferably lower than 0.5 nanometre.

11. The conduction channel made of Ge.sub.1-xSn.sub.x according to claim 10 forming horizontal fins arranged one above the other.

12. The conduction channel made of Ge.sub.1-xSn.sub.x according to claim 10 forming nanowires.

13. A FET transistor comprising a plurality of conduction channels made of Ge.sub.1-xSn.sub.x that are chosen according to claim 10.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Other features and advantages of the invention will become apparent through the description which follows by way of non-limiting illustration, given with reference to the appended figures, in which:

(2) FIG. 1A shows vertical nanowires made of Ge.sub.1-xSn.sub.x with x equal to 6% exhibiting etch flanks of high roughness.

(3) FIG. 1B shows vertical nanowires made of Ge.sub.1-xSn.sub.x with x equal to 6% exhibiting a non-smooth etch bottom comprising spikes.

(4) FIG. 1C shows vertical nanowires made of Ge.sub.1-xSn.sub.x with x equal to 6% exhibiting etch flanks of low roughness and an etch bottom without spikes, which are obtained according to a first embodiment of the invention.

(5) FIG. 2A shows vertical nanowires made of Ge.sub.1-xSn.sub.x with x equal to 10% exhibiting etch flanks of high roughness and an etch bottom without spikes.

(6) FIG. 2B shows vertical nanowires made of Ge.sub.1-xSn.sub.x with x equal to 10% exhibiting etch flanks of low roughness and an etch bottom without spikes, which are obtained according to a second embodiment of the invention.

(7) FIG. 3A shows vertical nanowires made of Ge.sub.1-xSn.sub.x with x equal to 15% exhibiting etch flanks of high roughness and an etch bottom with spikes.

(8) FIG. 3B shows vertical nanowires made of Ge.sub.1-xSn.sub.x with x equal to 15% exhibiting etch flanks of low roughness and an etch bottom without spikes, which are obtained according to a third embodiment of the invention.

(9) FIG. 3C shows vertical nanowires made of Ge.sub.1-xSn.sub.x with x equal to 15% exhibiting etch flanks of low roughness and an etch bottom without spikes, which are obtained according to a fourth embodiment of the invention.

(10) FIGS. 4A-4E show a method for producing horizontal nanowires or horizontal fins.

DETAILED DESCRIPTION

(11) Producing Vertical Nanowires

(12) The production method generally depends on the percentage x of Sn in the Ge.sub.1-xSn.sub.x alloy.

(13) For the four embodiments presented below, prior to etching, a layer of Ge.sub.1-xSn.sub.x is formed on a layer of germanium (Ge). The layer of Ge.sub.1-xSn.sub.x s formed by epitaxial growth, in particular by chemical vapour deposition or molecular-beam epitaxy. Next, a step of depositing a mask is carried out on the Ge.sub.1-xSn.sub.x, preferably a hard mask. For example, it may involve depositing hydrogen silsesquioxane (HSQ) resin, deposited using a “spin-coating” method. Once the etching process has ended, the resin is removed, for example by immersing in hydrofluoric acid (HF) diluted to a few percent or in a “buffered-oxide-etch” or “BOE” solution (for example a solution with a ratio by volume of ammonium fluoride to hydrofluoric acid of 6:1).

(14) The flow rate of the gases is given in sccm, i.e. in cm.sup.3/min, under standard temperature and pressure conditions.

(15) In all of the embodiments presented below, the temperature is generally ambient temperature.

(16) According to a first embodiment, applicable in particular when the percentage x of Sn in the Ge.sub.1-xSn.sub.x alloy is higher than 2% and lower than 8%, for example equal to 6%, a plasma etch is carried out with a chemistry comprising a mixture of dichloride (Cl.sub.2), of dinitrogen (N.sub.2) and of dioxygen (O.sub.2) at a pressure lower than or equal to 10 mTorr.

(17) The etch is carried out for example in an ICP-RIE (“inductively coupled plasma-reactive-ion etching”) chamber. In this case, the pressure given corresponds to the pressure in the chamber.

(18) The flow rates of Cl.sub.2, N.sub.2 and O.sub.2 are between 15 and 20 sccm, 4 and 8 sccm and 10 and 15 sccm, respectively.

(19) The bias power and plasma-generation power with ICP are between 30 and 60 watts and 30 and 60 watts, respectively.

(20) An etch rate of between 2 and 4 nanometres/second is obtained.

(21) This makes it possible to obtain vertical nanowires 2 made of Ge.sub.1-xSn.sub.x such as shown in FIG. 1C, with straight, very vertical flanks, without a difference in etching between layer 1 of Ge and layer 2 of Ge.sub.1-xSn.sub.x, and which closely follow the etch profile dictated by the mask 3 made of HSQ resin. Furthermore, the etch bottom 4 is free of spikes.

(22) According to a second embodiment, applicable in particular when the percentage x of Sn in the Ge.sub.1-xSn.sub.x alloy is higher than or equal to 8% and lower than 15%, for example equal to 10%, a plasma etch is carried out with a chemistry comprising a mixture of dichloride (Cl.sub.2), of dinitrogen (N.sub.2) and of dioxygen (O.sub.2) at a pressure lower than or equal to 5 mTorr.

(23) The etch is carried out for example in an ICP-RIE (“inductively coupled plasma-reactive-ion etching”) chamber. In this case, the pressure given corresponds to the pressure in the chamber.

(24) The flow rates of Cl.sub.2, N.sub.2 and O.sub.2 are between 15 and 20 sccm, 4 and 8 sccm and 10 and 15 sccm, respectively.

(25) The bias power and plasma-generation power with ICP are between 30 and 60 watts and 30 and 60 watts, respectively.

(26) An etch rate of between 2 and 4 nanometres/second is obtained.

(27) This makes it possible to obtain vertical nanowires 2 made of Ge.sub.1-xSn.sub.x such as shown in FIG. 2B, with straight, vertical flanks, without a difference in etching between layer 1 of Ge and layer 2 Ge.sub.1-xSn.sub.x, and which follow the etch profile dictated by the mask 3 made of HSQ resin. Furthermore, the etch bottom 4 is free of spikes. Decreasing the pressure to 5 mTorr makes it possible to have a less gradated profile, in comparison with the profile shown in FIG. 2A.

(28) According to a third embodiment, applicable in particular when the percentage x of Sn in the Ge.sub.1-xSn.sub.x alloy is higher than or equal to 15%, it is possible to carry out a plasma etch with a chemistry comprising a mixture of dichloride (Cl.sub.2) and of dinitrogen (N.sub.2), i.e. without dioxygen (O.sub.2), at a pressure of between 2 mTorr and 5 mTorr, advantageously equal to 2 mTorr.

(29) The etch is carried out for example in an ICP-RIE (“inductively coupled plasma-reactive-ion etching”) chamber. In this case, the pressure given corresponds to the pressure in the chamber.

(30) The flow rates of Cl.sub.2 and N.sub.2 are between 15 and 20 sccm and between 4 and 8 sccm, respectively.

(31) The bias power and plasma-generation power with ICP are between 30 and 60 watts and 30 and 60 watts, respectively.

(32) An etch rate of between 2 and 4 nanometres/second is obtained.

(33) This makes it possible to obtain vertical nanowires 2 made of Ge.sub.1-xSn.sub.x such as shown in FIG. 3B, with straight, very vertical flanks. Furthermore, the etch bottom 4 is free of spikes. Removing the dioxygen from the plasma chemistry makes it possible to have a less gradated profile, in comparison with the profile shown in FIG. 3A.

(34) According to a fourth embodiment, applicable in particular when the percentage x of Sn in the Ge.sub.1-xSn.sub.x alloy is higher than or equal to 15%, it is possible to carry out a plasma etch with a chemistry comprising a mixture of dichloride (Cl.sub.2), of dinitrogen (N.sub.2) and of dioxygen (O.sub.2), at a pressure of between 2 mTorr and 5 mTorr, advantageously equal to 2 mTorr. Additionally, prior to plasma etching, the Ge.sub.1-xSn.sub.x alloy is treated with acid in order to preferentially remove the chemical or native oxide from the tin.

(35) The flow rates of Cl.sub.2, N.sub.2 and O.sub.2 are between 15 and 20 sccm, 4 and 8 sccm and 10 and 15 sccm, respectively.

(36) The bias power and ICP power are between 30 and 60 watts and 30 and 60 watts, respectively.

(37) An etch rate of between 2 and 4 nanometres/second is obtained.

(38) This makes it possible to obtain vertical nanowires 2 made of Ge.sub.1-xSn.sub.x such as shown in FIG. 3C, with straight, vertical flanks, without a difference in etching between layer 1 of Ge and layer 2 of Ge.sub.1-xSn.sub.x, and which follow the etch profile dictated by the mask 3 made of HSQ resin. Furthermore, the etch bottom 4 is free of spikes. Carrying out a pretreatment with acid makes it possible to have an even less gradated profile, in comparison with the profile shown in FIG. 3A.

(39) Exemplary Implementation According to the Fourth Embodiment, with x Equal to 15%.

(40) The Ge.sub.1-xSn.sub.x alloy is exposed to hydrochloric acid (HCl), for example by immersing it in a bath of HCl at ambient temperature and at atmospheric pressure for a few minutes (for example 3 minutes), with light stirring.

(41) Next, during the plasma etch, the temperature is 20° C. The bias power is 50 W. The ICP power is 50 W. The etch pressure is 2 mTorr. The flow rate of Cl.sub.2 is 18 sccm. The flow rate of O.sub.2 is 5 sccm. The flow rate of N.sub.2 is 13 sccm.

(42) The etch rate obtained is of the order of 2.5 nanometres/second.

(43) Producing Horizontal Nanowires or Horizontal Fins

(44) An exemplary method for horizontal nanowires or horizontal fins is presented in FIGS. 4A to 4E.

(45) Prior to etching, a layer of Ge.sub.1-xSn.sub.x is formed on Ge. The layer of Ge.sub.1-xSn.sub.x is formed by epitaxial growth, in particular by chemical vapour deposition or molecular-beam epitaxy.

(46) Next, a step of depositing a mask is carried out on the Ge.sub.1-xSn.sub.x, preferably a hard mask. For example, it may involve depositing hydrogen silsesquioxane (HSQ) resin using electron-beam lithography.

(47) Typically, what is obtained is a structure of the type presented in FIG. 4A with a layer 1′ of Ge with a thickness of the order of 1.2 μm, on which is arranged a layer 2′ of Ge.sub.1-xSn.sub.x with a thickness of the order of 50 nm and a mask 3′ made of HSQ which comprises in particular the desired shape of the fin 31′.

(48) A first plasma etch is carried out according to the etching method of the invention, in particular according to one of the four embodiments described above. The etch conditions described above (embodiments, exemplary implementation) may also be applied. In particular, the bias power and plasma-generation power with ICP may be equal to 50 watts.

(49) Thus, what is obtained is a structure of the type presented in FIG. 4B in which layer 2′ of Ge.sub.1-xSn.sub.x has been etched to form a fin 21′ made of Ge.sub.1-xSn.sub.x. On the layer of Ge.sub.1-xSn.sub.x thus etched, the mask 3′ made of HSQ with the shape of the fin 31′ is still present, and all of the layer of Ge.sub.1-xSn.sub.x is still in contact with layer 1′ of Ge.

(50) A second plasma etch is then carried out using CF.sub.4. This second etch may be referred to as a “selective etch” in that it aims etch the germanium (Ge) and not the GeSn.

(51) According to one exemplary implementation, a flow rate of CF.sub.4 equal to 100 sccm, at a pressure of 50 mTorr, at ambient temperature, an ICP power of 500 watts and a bias power of 5 watts may be chosen in order to preferentially etch the germanium (Ge) while leaving the GeSn intact.

(52) What is obtained is a structure of the type presented in FIG. 4C in which layer 1′ of Ge has been etched beneath the fin 21′ made of Ge.sub.1-xSn.sub.x. A portion of layer 2′ of Ge.sub.1-xSn.sub.x is thus no longer in contact with layer 1′ of Ge, more precisely at the location of the fin 21′ made of Ge.sub.1-xSn.sub.x. The mask 3′ made of HSQ with the shape of the fin 31′ of the mask is still present.

(53) Lastly, the resin made of HSQ is removed, for example using a bath of hydrofluoric acid (HF) or in a “buffered-oxide-etch” solution as described above.

(54) What is obtained is a structure of the type presented in FIG. 4D in which the mask made of HSQ has been removed.

(55) The present invention is not limited to the embodiments described above but rather extends to any embodiment that comes within the scope of the claims.

(56) The invention makes it possible to produce vertical or horizontal nanowires or fins based on GeSn with dimensions of the order of ten nanometres to a few tens of nanometres.

(57) The invention applies in particular to the production of conduction channels for FinFET (fin field-effect transistor) transistors, GAAFET (gate-all-around field-effect transistor) transistors, or tunnel FET (TFET) transistors.

(58) In general, the invention applies to the production of FET transistors that are advantageously intended for high-performance and low-consumption logic applications in microelectronics, and/or may be used for “IoT” (Internet of things) applications.