Package with interconnections having different melting temperatures

Abstract

A package comprising at least one electronic chip, a first heat removal body on which the at least one electronic chip is mounted by a first interconnection, a second heat removal body mounted on or above the at least one electronic chip by a second interconnection, and an encapsulant encapsulating at least part of the at least one electronic chip, part of the first heat removal body and part of the second heat removal body, wherein the first interconnection is configured to have another melting temperature than the second interconnection.

Claims

1. A method of manufacturing a package, wherein the method comprises: mounting at least one electronic chip on a first heat removal body by a first interconnection; mounting at least one spacer body on the at least one electronic chip by a second interconnection; mounting a second heat removal body on the spacer body by a third interconnection; wherein one of the first interconnection, the second interconnection, and the third interconnection has a melting temperature different from the other two of the first interconnection, the second interconnection, and the third interconnection; wherein the second heat removal body is mounted on the at least one spacer body before mounting the at least one spacer body on the at least one electronic chip.

2. The method according to claim 1, wherein the at least one electronic chip is mounted on the first heat removal body before mounting the at least one spacer body on the at least one electronic chip.

3. The method according to claim 1, wherein forming the last of the first interconnection, the second interconnection, and the third interconnection is carried out at a low enough interconnection temperature that the other two previously formed interconnections are prevented from melting or re-melting during forming the last interconnection.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The accompanying drawings, which are included to provide a further understanding of exemplary embodiments and constitute a part of the specification, illustrate exemplary embodiments.

(2) In the drawings:

(3) FIG. 1 shows a cross-sectional view of a double-sided cooling package according to an exemplary embodiment.

(4) FIG. 2 is an image showing a cross-sectional view of a package according to an exemplary embodiment.

(5) FIG. 3 is an image showing a cross-sectional view of a package according to another exemplary embodiment.

(6) FIG. 4 shows a schematic view of a vehicle with a package according to an exemplary embodiment.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

(7) The illustration in the drawing is schematically.

(8) Before describing further exemplary embodiments in further detail, some basic considerations of the present inventors will be summarized based on which exemplary embodiments have been developed which provide for an electronically reliable package with low loss during operation.

(9) According to an exemplary embodiment of the invention, a double-sided cooling package implementing interconnect layers with different properties is provided.

(10) A package or module may be composed of a lower Direct Copper Bonding substrate (DCB substrate) forming a first heat removal body, a first solder layer (forming a first interconnection), at least one electronic chip, a second solder layer (constituting a second interconnection), a third solder layer, and an upper DCB as an embodiment of a second heat removal body. However, it has turned out that the conventional approach of using identical materials for the three interconnections (i.e. the above-mentioned first, second and third solder layer) involves reliability issues.

(11) The present inventors have found that the mentioned three interconnections of the same material may involve problems during a system soldering procedure. Such a system soldering procedure relates to the formation of an arrangement of lower DCB, chip, spacer and upper DCB. When all three interconnections melt or re-melt at the same temperature, undesired effects may occur. These can be recesses or void areas below the electronic chip, undefined positioning or floating of the spacer bodies, undesired formation of connections of solder material around the spacer, etc. Such effects may conventionally reduce the reliability of the manufactured package.

(12) Moreover, solder material has only limited thermal conductivity so that the thermal performance of such a conventional module may be not sufficient for high performance power applications. Moreover, the space consumption resulting from the floating of the spacer bodies onto a front side of an electronic chip may deteriorate the thermal performance, since the size of the spacer may need to be manufactured lower than the emitter pad.

(13) In order to overcome the above-mentioned and other shortcomings, an exemplary embodiment of the invention provides a package in which the different interconnections are configured so that at least one of the interconnections has a higher melting point than remaining interconnections. This can for instance be accomplished by the implementation of high temperature melting solder material (such as J-Alloy or High Lead). Also the implementation of one or more sinter layers substituting the conventional solder structures is an advantageous measure. Furthermore, welding may be implemented as interconnection technique for any of the interconnections of the package, but highly preferred for the uppermost one.

(14) In a preferred embodiment, at least one of the three mentioned interconnections is embodied as a material with lower melting temperature, since the entire height of the module or chip may be realized with a so-called Solder Jig during system soldering. Tolerances of PCB, chip and spacer can be at least partially equilibrated by adjusting bridging properties of interconnect material (for instance provided by SnAg solder material). What concerns an interconnect below an electronic chip, this may improve the thermal conductivity with regard to the lower DCB. Furthermore, the positional accuracy of the electronic chip(s) may be improved, since floating may be reliably prevented. This also increases the compactness of the device. Moreover, the reliability can be improved by taking the described measure.

(15) The interconnection between electronic chip and spacer body may be configured so that the thermal conductivity with regard to the spacer body is improved. The positional accuracy of the spacer body can be significantly improved, since floating effects may be suppressed. This allows also to configure the spacer body with a larger size, which again further increases the thermal performance of the package.

(16) What concerns the interconnection between spacer body and upper heat removal body, it may be configured so that the thermal conductivity towards the spacer body may be improved. It may be advantageous to form this interconnection from a low melting material.

(17) According to an exemplary embodiment of the invention, a double-sided cooling module for power semiconductor applications is provided which has an electric isolation integrated in the package or module. The interconnections of such a package may be configured so that one of the three interconnections has a higher melting or re-melting point than the remaining interconnect layers. It is also advantageous that two of the three interconnections have a higher melting or re-melting point than the remaining interconnection.

(18) In particular for the third interconnection, welding has turned out as an interesting alternative to soldering or sintering. Welding does not necessarily involve a separate interconnection material, but simply connects the two constituents to be connected when the local temperature in between is sufficiently high to make one or both of the constituents melt.

(19) The following Table 1 shows different embodiments of the invention in terms of configuration of the various interconnections (first interconnection between first heat removal body and at least one electronic chip, second interconnection between at least one electronic chip and at least one spacer body, third interconnection between at least one spacer body and second heat removal body):

(20) TABLE-US-00001 TABLE 1 First Second Third Embodiment Interconnection Interconnection Interconnection Embodiment A sinter solder solder Embodiment B solder sinter solder Embodiment C solder solder sinter Embodiment D solder sinter sinter Embodiment E sinter solder sinter Embodiment F sinter sinter solder Embodiment G solder solder weld Embodiment H solder sinter weld Embodiment I sinter solder weld Embodiment J sinter sinter weld

(21) The following Table 2 provides further embodiments of the invention in terms of melting or re-melting temperatures of the various interconnections. In this Table 2, the three mentioned melting or re-melting temperatures X, Y, Z meet the condition X>Y>Z. referring to Table 2, each of the first interconnection, second interconnection and third interconnection may be freely selected from the group of sintering, soldering, and welding.

(22) TABLE-US-00002 TABLE 2 First Second Third Embodiment Interconnection Interconnection Interconnection Embodiment I X Y Y Embodiment II Y X Y Embodiment III Y Y X Embodiment IV X X Y Embodiment V X Y X Embodiment VI Y X X Embodiment VII X Y Z Embodiment VIII X Z Y Embodiment IX Y X Z Embodiment X Y Z X Embodiment XI Z X Y Embodiment XII Z Y X

(23) In the following, three specifically preferred embodiments will be described in more detail:

(24) In a first preferred embodiment, the first interconnection is embodied as a solder interconnection (for instance using Sb-based solder material), the second interconnection is embodied as solder interconnection using the same solder material as the first interconnection, and the third interconnection is embodied as a welding connection.

(25) In a second preferred embodiment, the first interconnection is embodied as a solder interconnection (for instance using diffusion solder material), the second interconnection is embodied as solder interconnection using another solder material (for instance a ductile high-melting solder material such as SnSb-solder or Pb-solder) than the first interconnection, and the third interconnection is embodied as a welding connection.

(26) In a third preferred embodiment, the first interconnection is embodied as a solder interconnection (for instance using SnAg-based solder material), the second interconnection is embodied as solder interconnection using the same solder material as the first interconnection, and the third interconnection is embodied as yet another solder connection (for instance SnSb-based solder).

(27) In all three embodiments, mounting of the spacer bodies on the upper DCB is possible without re-melting of the chips and the lower DCB.

(28) FIG. 1 shows a cross-sectional view of a double-sided cooling package 100 according to an exemplary embodiment.

(29) The package 100 according to FIG. 1 comprises two electronic chips 102 which are here embodied as power semiconductor chips. The electronic chip 102 shown on the left hand side of FIG. 1 may be a diode chip, whereas the electronic chip 102 shown on the right-hand side of FIG. 1 may be an IGBT (Insulated Gate Bipolar Transistor) chip.

(30) A first heat removal body 104, which is here embodied as Direct Copper Bonding (DCB) substrate, is thermally and mechanically coupled to a first main surface of the electronic chips 102 and forms part of an exterior surface of the package 100. The first heat removal body 104 is configured for removing thermal energy from the electronic chips 102 during operation of the package 100 to a package external cooling body and/or cooling fluid (not shown). The first heat removal body 104 comprises a central electrically insulating and thermally conductive layer 110, here made of ceramic material, having a first main surface covered by a first electrically conductive layer 112, which is here embodied as a copper layer, and having an opposing second main surface covered by a second electrically conductive layer 114, which is here embodied as a further copper layer. The electronic chips 102 are mounted and soldered or sintered on the first heat removal body 104 and are electrically connected with the first electrically conductive layer 112 by bond wires 176. Hence, the first heat removal body 104 functions as a chip carrier and as a heat sink. The second electrically conductive layer 114 of the first heat removal body 104 forms part of an exterior surface of the package 100 and thereby significantly contributes to the heat removal from the electronic chips 102 during operation of the package 100.

(31) Optional electrically conductive and thermally conductive spacer bodies 126, which may be embodied as copper blocks, are soldered or sintered onto upper main surfaces of the electronic chips 102.

(32) Moreover, a second heat removal body 106 is thermally coupled to a second main surface of the electronic chips 102 via the spacer bodies 126. Also the second heat removal body 106 comprises a central electrically insulating and thermally conductive layer 110, which may be made of ceramic, having a first main surface covered by a first electrically conductive layer 112, which is here embodied as a copper layer, and having an opposing second main surface covered by a second electrically conductive layer 114, which is here embodied as a further copper layer. The first electrically conductive layer 112 of the second heat removal body 106 is soldered or sintered or welded onto the spacer bodies 126. The second electrically conductive layer 114 of the second heat removal body 106 forms part of an exterior surface of the package 100 and thereby significantly contributes to the heat removal from the electronic chips 102 during operation of the package 100. As a whole, the second heat removal body 106 is configured as a heat sink for removing thermal energy from the electronic chips 102.

(33) An electrically conductive contact structure 118, here embodied as a leadframe, extends partially within and partially outside of the encapsulant 108 and is electrically coupled with the electronic chips 102 via a solder or sinter connection with the patterned first electrically conductive layer 112 of the first heat removal body 104 and via the bond wires 176.

(34) Furthermore, the package 100 comprises a mold-type encapsulant 108 encapsulating the electronic chips 102, the spacer bodies 126, only part of the electrically conductive contact structure 118, only part of the first heat removal body 104 and only part of the second heat removal body 106. The part of the electrically conductive contact structure 118 encapsulated by the encapsulant 108 serves for electrically contacting the electronic chips 102, whereas another part of the electrically conductive contact structure 118 exposed from the encapsulant 108 provides one or more leads for connection with an electronic periphery device (not shown). Since the electrically conductive contact structure 118 extends partially within and partially outside of the encapsulant 108 and is electrically coupled with the electronic chips 102, it is capable of providing an electric coupling between an exterior and an interior of the package 100.

(35) The package 100 may be manufactured as follows: The heat removal bodies 104, 106 as well as the electrically conductive contact structure 118 may be roughened by etching. Thereafter, the electronic chips 102 may be soldered or sintered onto the first heat removal body 104. After that, connection of the electrically conductive contact structure 118 with the first heat removal body 104 may be accomplished by soldering or sintering, wire bonding, etc. Then, the optional spacer bodies 126 may be soldered or sintered on top of the electronic chips 102. This can be followed by a solder or sinter or welding connection of the second heat removal body 106 on the spacer bodies 126. After that, encapsulation by molding may be carried out so that the encapsulant 108 fills the gaps between the mentioned constituents and keeps external surfaces of the heat removal bodies 104, 106 uncovered.

(36) The electronic chips 102 are mounted on the patterned first electrically conductive layer 112 of the first heat removal body 104 by a first interconnection 170. The spacer bodies 126 are mounted on the electronic chips 102 by a second interconnection 172. The first electrically conductive layer 112 of the second heat removal body 106 is mounted on the spacer bodies 126 and above the electronic chips 102 by third interconnection 174. Each of the first interconnection 170, the second interconnection 172 and the third interconnection 174 may be a solder structure or a sinter structure or may be formed by welding.

(37) The first interconnection 170 can be configured to have another melting or re-melting temperature than the second interconnection 172 and the third interconnection 174. Advantageously, the materials of the first interconnection 170, the second interconnection 172 and the third interconnection 174 may be different from one another, in particular may have different melting points. For instance, the first interconnection 170 may be made of a material having another melting temperature than a material of which the second interconnection 172 is made. It is also possible that the third interconnection 174 is made of a material having a lower melting temperature than a material of at least one of the first interconnection 170 and the second interconnection 172. The third interconnection 174 may however also be a welding interconnection which does not involve an additional material. Advantageously, one of the first interconnection 170, the second interconnection 172 and the third interconnection 174 is made of a material having a higher melting temperature than the other two of the first interconnection 170, the second interconnection 172 and the third interconnection 174. It is in particular possible that two of the first interconnection 170, the second interconnection 172 and the third interconnection 174 are made of a material having a higher melting temperature than the remaining one of the first interconnection 170, the second interconnection 172 and the third interconnection 174.

(38) By configuring the interconnections 170, 172, 174 in the described way, the package 100 may be manufactured with high reliability. In particular, spatial accuracy of the electronic chips 102 and of the spacer bodies 126 may be high, because undefined floating due to a simultaneous melting of all interconnections 170, 172, 174 may be prevented. Furthermore, undesired reflow of solder material onto undefined surfaces of the spacer bodies 126 may be prevented. Also, the formation of fjord-shaped recesses or unfilled volumes beneath the electronic chips 102 may be safely prevented.

(39) FIG. 2 is an image showing a cross-sectional view of a package 100 according to an exemplary embodiment.

(40) FIG. 2 shows an embodiment in which the electronic chip 102 is sintered on a lower DCB (Direct Copper Bonding substrate) as first heat removal body 104. Spacer bodies 126 are soldered onto a front side of the electronic chip 102. Furthermore, the spacer bodies 126 may be soldered onto an upper DCB as second heat removal body 106. A very high reliability can be obtained with this type of package 100.

(41) FIG. 3 is an image showing a cross-sectional view of a package 100 according to another exemplary embodiment.

(42) Referring to the embodiment of FIG. 3, the electronic chip 102 has been sintered on a lower DCB as first heat removal body 104. The spacer bodies 126 are sintered on the front side of the electronic chip 102. The spacer bodies 126 are furthermore soldered onto an upper DCB as second heat removal body 106.

(43) Also with the embodiment of FIG. 3, a very high reliability may be achieved.

(44) FIG. 4 shows a schematic view of a vehicle 122 with a package 100 according to an exemplary embodiment.

(45) More specifically, the power package 100 may form part of a control block 152 controlling operation of engine/battery block 154. Hence, a package 100 or power module according to an exemplary embodiment of the invention may be used for an automotive application. A preferred application of such a power package 100 is an implementation as an inverter circuit or inverted rectifier for vehicle 122 which may be an electrically driven vehicle or which may be a hybrid vehicle. Such an inverter may transfer a direct current (DC) of the battery into an alternating current (AC) for driving the electric engine of vehicle 122. In a hybrid vehicle, it is also possible to at least partially recover mechanical energy and to transfer it, by the inverter, back into electric energy to recharge the battery. In such an automotive inverter application, extreme amounts of heat are generated during operation of the power package 100. This heat can be efficiently removed by the double-sided cooling concept described above. However, it should be said that, in other embodiments, also single-sided cooling may be sufficient.

(46) It should be noted that the term comprising does not exclude other elements or features and the a or an does not exclude a plurality. Also elements described in association with different embodiments may be combined. It should also be noted that reference signs shall not be construed as limiting the scope of the claims. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.