Method to Synchronize Integrated Circuits Fulfilling Functional Safety Requirements

Abstract

In accordance with aspects of the present invention, a method of synchronizing two integrated circuits is presented. A method of synchronizing two integrated circuits can include sending a first pulse from a master IC to a slave IC over a SYNC bus; receiving a second pulse on the SYNC bus from the slave IC; checking the second pulse; triggering an interrupt if a failure is detected; and initiating measurement if synchronization is detected.

Claims

1. A method of synchronizing a master IC with a slave IC, comprising: sending a first pulse from the master IC to the slave IC over a SYNC bus; receiving a second pulse on the SYNC bus from the slave IC; checking the second pulse; triggering an interrupt if a failure is detected in the width or delay of the second pulse; initiating measurement if synchronization is detected.

2. The method of claim 1, wherein sending the first pulse includes setting a master output enable signal; sending the first pulse; checking the first pulse; and releasing the master output enable signal.

3. The method of claim 1, wherein checking the second pulse includes checking the pulse width.

4. The method of claim 1, wherein checking the second pulse includes checking the delay.

5. The method of claim 1, wherein initiating measurement includes setting the master output enable signal.

6. A method of synchronizing a master IC with a slave IC, comprising: receiving a pulse from the master IC; checking the width of the pulse; setting a slave output enable; providing an answer pulse; and releasing the slave output enable.

7. A system performing functional safety requirements, comprising: a master IC, the master IC including a master clock input, a sync bus, and an output enable; a slave IC coupled to the master IC, the slave IC including a slave clock input, the sync bus, and the output enable, wherein the slave clock input and the master clock input are coupled to a clocking source, and wherein the master IC checks synchronization with the slave IC by sending a first pulse from the master IC to the slave IC over a SYNC bus; receiving a second pulse on the SYNC bus from the slave IC; checking the second pulse; triggering an interrupt if a failure is detected in the width or delay of the second pulse; initiating measurement if synchronization is detected.

8. The system of claim 7, wherein sending the first pulse includes setting a master output enable signal; sending the first pulse; checking the first pulse; and releasing the master output enable signal.

9. The system of claim 7, wherein checking the second pulse includes checking the pulse width.

10. The system of claim 7, wherein checking the second pulse includes checking the delay.

11. The system of claim 7, wherein initiating measurement includes setting the master output enable signal.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0010] FIG. 1 illustrates a control circuit with a pair of ICs that are coupled to perform synchronization.

[0011] FIG. 2 further illustrates the synchronization process.

[0012] FIG. 3 illustrates the signals associated with the synchronization process illustrated in FIG. 2.

DETAILED DESCRIPTION

[0013] In the following description, specific details are set forth describing some embodiments of the present invention. It will be apparent, however, to one skilled in the art that some embodiments may be practiced without some or all of these specific details. The specific embodiments disclosed herein are meant to be illustrative but not limiting. One skilled in the art may realize other elements that, although not specifically described here, are within the scope and the spirit of this disclosure.

[0014] This description and the accompanying drawings that illustrate inventive aspects and embodiments should not be taken as limitingthe claims define the protected invention. Various changes may be made without departing from the spirit and scope of this description and the claims. In some instances, well-known structures and techniques have not been shown or described in detail in order not to obscure the invention.

[0015] Two integrated circuits (ICs) are often operating at a high clock frequency generated by an internal phase-locked-loop (PLL). Especially in safety situations, the two integrated circuits need to operate and cycle accurately in order to safely fulfill its requirements. Consequently, if the two ICs are not synchronized, there may be safety issues.

[0016] FIG. 1 illustrates a system 100 that includes two chips (master 102 and slave 104) that are involved in functional safety operations and which are to be synced to facilitate the safety functions of system 100. System 100 can be any system, for example a controller system, that includes fulfills a functional safety requirement. Although system 100 illustrates one master/slave pair, one skilled in the art would recognize that there may be multiple slaves 104 coupled to master 102 in order that system 100 may be synchronized.

[0017] As illustrated in FIG. 1, master 102 is coupled to slave 104 by a SYNC line. ICs 102 and 104 may also exchange enable signals OE_M and OE_S signals on an enable line. Further, each of ICs 102 and 104 receive a clock signal CLK that can be generated by a phase-locked-loop (PLL) 106 coupled to clock 108. Clock signals can also be generated internally to master 102 and slave 104. As is further illustrated, other signal lines are also coupled between master 102 and slave 104. Such lines may include instructions and data that are exchanged between master 102 and slave 104.

[0018] As is illustrated in FIG. 1, synchronization is accomplished using a bidirectional single wire interface, SYNC. A synchronous pulse is generated by master IC 102 and received by slave IC 104. After receiving and checking, slave IC 104 answers with a similar pulse. Master IC 102 checks the timing of the received answer from slave IC 104 (the Feedback signal) to judge if the synchronization was successful.

[0019] FIGS. 2 and 3 illustrate operation of master 102 and slave 104 according to some embodiments of the present invention. As illustrated in FIG. 3, master IC 102 receives clock 302 and slave IC 104 receives clock 304. Similarly, master IC 102 receives a SYNC signal 310 and slave IC 104 receives SYNC signal 312. As indicated, clock signal 302 and clock signal 304 are out of phase.

[0020] FIG. 2 illustrates a synchronization check algorithm 200 operated on master 102 and on slave 104. Master 102 executes algorithm 240 while slave 104 operates algorithm 242. Signals are sent between master 102 and slave 104 as illustrated in interface 244. Algorithm 200 starts in master 102 at start function 202. Start 202 may be initiated periodically throughout operation of system 100 in order to insure synchronization.

[0021] From start 202, master 102 exerts the OE_M signal to take control of the bus and, in step 206, sends the pulse 306 on the SYNC line. In step 208, master 102 checks the pulse width and the timing according to its clock signal 302 for accuracy. If the pulse is found to be good, then algorithm 240 proceeds to step 210 where master 102 releases the bus by resetting OE_M. As illustrated in FIG. 3, the signal on the SYNC line goes high because of a weak pull-up.

[0022] At slave 104, in step 212, the pulse on the SYNC line from master 102 is received. In step 214, slave 104 checks the pulse width using its clock signal 304. If the pulse width does not agree with what has been expected, then algorithm 242 proceeds to step 222 to indicate a faulty pulse width and algorithm 242 stops. If the pulse width does check out, the algorithm 242 proceeds to step 216 where slave 104 exerts an output enable signal OE_S to take over the bus. In step 218, slave 104 provides an answering pulse 308 and then proceeds to step 220 to release OE_S.

[0023] In algorithm 240 of master 102, answering pulse 308 is received in step 226. In step 228, master 102 checks answering pulse 308 with respect to width and delay in comparison with pulse 306. If the pulse is correct, the algorithm 240 proceeds to step 230 to set OE_M and then to step 234 to initiate measurement or normal activity. In algorithm 242, if step 234 is initiated in master 102, then slave 104 proceeds to step 236 to provide normal operation.

[0024] If the pulse is not correct, then algorithm 240 proceeds to step 230 to set OE_M and then to step 232 to initiate a failure interrupt so that system 100 can recover and proceed to a safe state. In the event that no pulse is received by master 102, algorithm 240 initiates step 238. From step 238, algorithm 240 proceeds to step 230 to set OE_M and then to step 232 to initiate a failure interrupt so that system 100 can recover and proceed to a safe state.

[0025] In summary, as indicated in FIGS. 2 and 3, the synchronization timing includes 1) Master 102 sending a pulse to slave 104; 2) Master 102 checking the pulse width and timing on the SYNC bus; 3) Master 102 releasing the SYNC bus to a weak pull-up (OE_M); 4) Slave 104 checking the pulse width; 5) Slave 104 enabling OE (OE_S); 6) Slave 104 answering with a pulse if the received pulse is correct; 7) Slave 104 releasing the SYNC bus (by disabling OE_S); 8) Master 102 checking the pulse width and delay from its pulse of the received pulse from slave 104; 9) Master 102 enabling OE (OE_M); and 10) Master 102 initiating measurement to proceed with normal operation OR triggering interrupts to indicate failure.

[0026] Although system 100, and PLL 106, can operate at any clock speed. As an example, FIG. 3 illustrates a 200 MHz clock. Consequently, clock signal 302 and clock signal 304 has a 5 ns period. In that case, pulse 306 sent by master 102 may send a 20 ns pulse (four clock periods) and slave 104 respond with a similar 20 ns pulse. Other pulse widths may be used in accordance with the clock signals. Further, in some embodiments, slave 104 may respond with a pulse 308 with a width different from that pulse 306 produced from master 102.

[0027] Several failures in the synchronization can be detected. These failures can include whether there is too low drive strength of master 102, which can be detected by direct feedback in master 102 at step 208, for example. Another failure can be if there is too low a drive strength in slave 104, which is detected by direct feedback in slave 104. Further, in step 228 master 102 can detect if there is too late detection of SYNC pulse by slave, which can be detected by checking response time in master 102. In some cases, master 102 can also detect if there is too early detection of SYNC pulse, which cannot happen by protocol but may happen by external disturbances. The pulse width received at slave 104 and at master 102 can provide information regarding external disturbances.

[0028] The above detailed description is provided to illustrate specific embodiments of the present invention and is not intended to be limiting. Numerous variations and modifications within the scope of the present invention are possible. The present invention is set forth in the following claims.