Bonded body and power module substrate

Abstract

The bonded body of the present invention includes: a ceramic member made of ceramics; and a Cu member which is made of Cu or a Cu alloy and bonded to the ceramic member through a CuPSn-based brazing filler material and a Ti material, wherein a CuSn layer, which is positioned close to the ceramic member and in which Sn forms a solid solution with Cu, and a Ti layer which is positioned between the Cu member and the CuSn layer, are formed at a bonded interface between the ceramic member and the Cu member, a first intermetallic compound layer made of Cu and Ti is formed between the Cu member and the Ti layer, and a second intermetallic compound layer containing P is formed between the CuSn layer and the Ti layer.

Claims

1. A bonded body comprising: a ceramic member made of ceramics; and a Cu member which is made of Cu or a Cu alloy and bonded to the ceramic member through a CuPSn-based brazing filler material and a Ti material, wherein a CuSn layer, which is positioned close to the ceramic member and in which Sn forms a solid solution with Cu, and a Ti layer which is positioned between the Cu member and the CuSn layer, are formed at a bonded interface between the ceramic member and the Cu member, a first intermetallic compound layer made of Cu and Ti is formed between the Cu member and the Ti layer, and a second intermetallic compound layer containing P is formed between the CuSn layer and the Ti layer.

2. The bonded body according to claim 1, wherein a thickness of the first intermetallic compound layer is set to be in a range of 0.5 m to 10 m.

3. The bonded body according to claim 1, wherein a thickness of the Ti layer is set to be in a range of 1 m to 15 m.

4. A power module substrate comprising the bonded body according to claim 1, wherein the substrate further comprises: a ceramic substrate formed of the ceramic member; and a circuit layer formed by bonding a Cu foil formed of the Cu member to a first surface of the ceramic substrate through the CuPSn-based brazing filler material and the Ti material, wherein the CuSn layer, which is positioned close to the ceramic substrate and in which Sn forms a solid solution with Cu, and the Ti layer which is positioned between the circuit layer and the CuSn layer, are formed at a bonded interface between the ceramic substrate and the circuit layer, the first intermetallic compound layer made of Cu and Ti is formed between the circuit layer and the Ti layer, and the second intermetallic compound layer containing P is formed between the CuSn layer and the Ti layer.

5. The power module substrate according to claim 4, wherein a metal layer is formed on a second surface of the ceramic substrate.

6. The power module substrate according to claim 5, wherein the metal layer is formed by bonding a Cu foil made of Cu or a Cu alloy to the second surface of the ceramic substrate through a CuPSn-based brazing filler material and a Ti material, a CuSn layer, which is positioned close to the ceramic substrate and in which Sn forms a solid solution with Cu, and a Ti layer which is positioned between the metal layer and the CuSn layer, are formed at a bonded interface between the ceramic substrate and the metal layer, a first intermetallic compound layer made of Cu and Ti is formed between the metal layer and the Ti layer, and a second intermetallic compound layer containing P is formed between the CuSn layer and the Ti layer.

7. The power module substrate according to claim 5, wherein the metal layer is made of Al or an Al alloy.

8. The power module substrate according to claim 4, wherein a thickness of the Ti layer is set to be in a range of 1 m to 15 m.

9. The bonded body according to claim 2, wherein a thickness of the Ti layer is set to be in a range of 1 m to 15 m.

10. A power module substrate comprising the bonded body according to claim 2, wherein the substrate further comprises: a ceramic substrate formed of the ceramic member; and a circuit layer formed by bonding a Cu foil formed of the Cu member to a first surface of the ceramic substrate through the CuPSn-based brazing filler material and the Ti material, wherein the CuSn layer, which is positioned close to the ceramic substrate and in which Sn forms a solid solution with Cu, and the Ti layer which is positioned between the circuit layer and the CuSn layer, are formed at a bonded interface between the ceramic substrate and the circuit layer, the first intermetallic compound layer made of Cu and Ti is formed between the circuit layer and the Ti layer, and the second intermetallic compound layer containing P is formed between the CuSn layer and the Ti layer.

11. A power module substrate comprising the bonded body according to claim 3, wherein the substrate further comprises: a ceramic substrate formed of the ceramic member; and a circuit layer formed by bonding a Cu foil formed of the Cu member to a first surface of the ceramic substrate through the CuPSn-based brazing filler material and the Ti material, wherein the CuSn layer, which is positioned close to the ceramic substrate and in which Sn forms a solid solution with Cu, and the Ti layer which is positioned between the circuit layer and the CuSn layer, are formed at a bonded interface between the ceramic substrate and the circuit layer, the first intermetallic compound layer made of Cu and Ti is formed between the circuit layer and the Ti layer, and the second intermetallic compound layer containing P is formed between the CuSn layer and the Ti layer.

12. A power module substrate comprising the bonded body according to claim 9, wherein the substrate further comprises: a ceramic substrate formed of the ceramic member; and a circuit layer formed by bonding a Cu foil formed of the Cu member to a first surface of the ceramic substrate through the CuPSn-based brazing filler material and the Ti material, wherein the CuSn layer, which is positioned close to the ceramic substrate and in which Sn forms a solid solution with Cu, and the Ti layer which is positioned between the circuit layer and the CuSn layer, are formed at a bonded interface between the ceramic substrate and the circuit layer, the first intermetallic compound layer made of Cu and Ti is formed between the circuit layer and the Ti layer, and the second intermetallic compound layer containing P is formed between the CuSn layer and the Ti layer.

13. The power module substrate according to claim 10, wherein a metal layer is formed on a second surface of the ceramic substrate.

14. The power module substrate according to claim 11, wherein a metal layer is formed on a second surface of the ceramic substrate.

15. The power module substrate according to claim 12, wherein a metal layer is formed on a second surface of the ceramic substrate.

16. The power module substrate according to claim 13, wherein the metal layer is formed by bonding a Cu foil made of Cu or a Cu alloy to the second surface of the ceramic substrate through a CuPSn-based brazing filler material and a Ti material, a CuSn layer, which is positioned close to the ceramic substrate and in which Sn forms a solid solution with Cu, and a Ti layer which is positioned between the metal layer and the CuSn layer, are formed at a bonded interface between the ceramic substrate and the metal layer, a first intermetallic compound layer made of Cu and Ti is formed between the metal layer and the Ti layer, and a second intermetallic compound layer containing P is formed between the CuSn layer and the Ti layer.

17. The power module substrate according to claim 14, wherein the metal layer is formed by bonding a Cu foil made of Cu or a Cu alloy to the second surface of the ceramic substrate through a CuPSn-based brazing filler material and a Ti material, a CuSn layer, which is positioned close to the ceramic substrate and in which Sn forms a solid solution with Cu, and a Ti layer which is positioned between the metal layer and the CuSn layer, are formed at a bonded interface between the ceramic substrate and the metal layer, a first intermetallic compound layer made of Cu and Ti is formed between the metal layer and the Ti layer, and a second intermetallic compound layer containing P is formed between the CuSn layer and the Ti layer.

18. The power module substrate according to claim 15, wherein the metal layer is formed by bonding a Cu foil made of Cu or a Cu alloy to the second surface of the ceramic substrate through a CuPSn-based brazing filler material and a Ti material, a CuSn layer, which is positioned close to the ceramic substrate and in which Sn forms a solid solution with Cu, and a Ti layer which is positioned between the metal layer and the CuSn layer, are formed at a bonded interface between the ceramic substrate and the metal layer, a first intermetallic compound layer made of Cu and Ti is formed between the metal layer and the Ti layer, and a second intermetallic compound layer containing P is formed between the CuSn layer and the Ti layer.

19. The power module substrate according to claim 13, wherein the metal layer is made of Al or an Al alloy.

20. The power module substrate according to claim 14, wherein the metal layer is made of Al or an Al alloy.

Description

BRIEF DESCRIPTION OF DRAWINGS

(1) FIG. 1 is a schematic view of a power module in which a power module substrate is used in a first embodiment of the present invention.

(2) FIG. 2 is a schematic view of the power module substrate in the first embodiment of the present invention.

(3) FIG. 3 is an electron micrograph obtained by capturing an image of the section of the bonded interface between a circuit layer and a ceramic substrate shown in FIG. 2, and a schematic view thereof.

(4) FIG. 4 is a flowchart showing a method of producing the power module substrate and the power module in the first embodiment of the present invention.

(5) FIG. 5 shows schematic views showing the method of producing the power module substrate and the power module in the first embodiment of the present invention.

(6) FIG. 6 is a schematic view of a power module in which a power module substrate is used in a second embodiment of the present invention.

(7) FIG. 7 is a schematic view of the power module substrate in the second embodiment of the present invention.

(8) FIG. 8 is a schematic view of the section of the bonded interface between a metal layer and a ceramic substrate shown in FIG. 7.

(9) FIG. 9 is a flowchart showing a method of producing the power module substrate and the power module in the second embodiment of the present invention.

(10) FIG. 10 shows schematic views showing the method of producing the power module substrate and the power module in the second embodiment of the present invention.

(11) FIG. 11 is a schematic view of a power module in which a power module substrate in a third embodiment of the present invention is used.

(12) FIG. 12 is a schematic view of the power module substrate in the third embodiment of the present invention.

(13) FIG. 13 is a flowchart showing a method of producing the power module substrate and the power module in the third embodiment of the present invention.

(14) FIG. 14 shows schematic views showing the method of producing the power module substrate and the power module in the third embodiment of the present invention.

DESCRIPTION OF EMBODIMENTS

First Embodiment

(15) Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. First, a first embodiment of the present invention will be described.

(16) A bonded body in the embodiment is a power module substrate 10 in which a ceramic substrate 11 formed of a ceramic member, and a Cu foil 22 (a circuit layer 12) formed of a Cu member, are bonded to each other. FIG. 1 shows a power module 1 including the power module substrate 10 in the embodiment.

(17) The power module 1 includes the power module substrate 10 on which the circuit layer 12 is provided, and a semiconductor element 3 that is bonded to one surface (an upper surface in FIG. 1) of the circuit layer 12 through a bonding layer 2.

(18) As shown in FIG. 2, the power module substrate 10 includes the ceramic substrate 11 including a first surface and a second surface, and the circuit layer 12 that is provided on the first surface (an upper surface in FIG. 2) which is one surface of the ceramic substrate 11.

(19) The ceramic substrate 11 is made of high-insulation ceramics such as aluminum nitride (AlN), silicon nitride (Si.sub.3N.sub.4), and alumina (Al.sub.2O.sub.3). In the embodiment, the ceramic substrate 1 is made of aluminum nitride (AlN) having good heat radiation. The thickness of the ceramic substrate 11 is set to be in a range of 0.2 mm to 1.5 mm. In the embodiment, the thickness is set to 0.635 mm.

(20) The circuit layer 12 is formed by bonding an electrically-conductive metal plate (the Cu foil 22) made of Cu or a Cu alloy to the first surface of the ceramic substrate 11 through a CuPSn-based brazing filler material and Ti foil 25 as a Ti material. The Cu foil 22 may be made of oxygen-free copper, deoxidized copper, tough pitch copper, or the like. In the embodiment, the Cu foil 22 is made of oxygen-free copper. The thickness of the Cu foil 22 is preferably set to be in a range of 0.1 mm to 1.0 mm. In the embodiment, the thickness is set to 0.6 mm.

(21) Specific examples of the CuPSn-based brazing filler material include a CuPSn brazing filler material, a CuPSnNi-based brazing filler material, a CuPSnZn-based brazing filler material, a CuPSnMn-based brazing filler material, and a CuPSnCr-based brazing filler material. The CuPSn-based brazing filler material preferably contains 3 mass % to 10 mass % of P, and 0.5 mass % to 25 mass % of Sn. In the embodiment, a CuPSnNi brazing filler material 24 is used as the CuPSn-based brazing filler material. Preferably, the CuPSn-based brazing filler material is a foil shape and the thickness thereof is in a range of 5 m to 150 m.

(22) The CuPSn-based brazing filler material has a melting point of 710 C. or less. The CuPSnNi brazing filler material 24 used in the embodiment has a melting point of 580 C. In the embodiment, the solidus temperature of the CuPSn-based brazing filler material is used as the melting point.

(23) In the embodiment, the circuit layer 12 is formed by bonding the Cu foil 22 to the ceramic substrate 11 through the heating of the CuPSnNi brazing filler material 24, the Ti foil 25 as a Ti material, and the Cu foil 22 made of oxygen-free copper, which are laminated on the first surface of the ceramic substrate 11 (refer to FIG. 5).

(24) The thickness of the circuit layer 12 is set to be in a range of 0.1 mm to 1.0 mm. In the embodiment, the thickness is set to 0.6 mm.

(25) FIG. 3 shows an electron micrograph of the bonded interface between the ceramic substrate 11 and the circuit layer 12, and a schematic view thereof. As shown in FIG. 3, a CuSn layer 14 and a Ti layer 15 are formed at the bonded interface between the ceramic substrate 11 and the circuit layer 12. The CuSn layer 14 is positioned close to the ceramic substrate 11, and the Ti layer 15 is positioned between the circuit layer 12 and the CuSn layer 14.

(26) A first intermetallic compound layer 16 made of Cu and Ti is formed between the circuit layer 12 and the Ti layer 15. A second intermetallic compound layer 17 containing P and Ni is formed between the CuSn layer 14 and the Ti layer 15.

(27) The CuSn layer 14 is a layer in which Sn forms a solid solution with Cu. P and Ni contained in the CuPSnNi brazing filler material 24 is drawn into the second intermetallic compound layer 17 formed close to the Ti layer 15, and thereby the CuSn layer 14 is formed. The thickness of the CuSn layer 14 may be set to be in a range of 1 m to 140 m.

(28) As described above, the Ti layer 15 is formed by bonding the ceramic substrate 11 and Cu foil 22 are bonded to each other through the CuPSnNi brazing filler material 24 and the Ti foil 25. In the embodiment, the thickness of the Ti layer 15 is preferably set to be 1 m to 15 m.

(29) When the thickness of the Ti layer 15 is set to be 1 m to 15 m, the Ti layer acts reliably as a barrier layer which prevents Sn from diffusing to the circuit layer 12. Thereby, it is possible to reliably limit the diffusion of Sn. The Ti layer has a thermal resistance larger than that of the circuit layer 12 made of Cu foil 22. Since such Ti layer 15 does not have a large thickness, it is possible to limit an increase of the thermal resistance of the power module substrate 10. Further, the Ti layer has a relatively higher strength. Since such Ti layer 15 does not have a large thickness, when the power module substrate 10 undergoes a thermal cycle, it is possible to reduce thermal stress being generated in the ceramic substrate 11 and to limit the occurrence of cracking in the ceramic substrate 11. For this reason, the thickness of the Ti layer 15 is preferably set to be in the aforementioned range. The thickness of the Ti layer 15 may be set to be 1 m 20 to 5 m.

(30) Cu in the circuit layer 12 diffuses through the Ti layer 15 and Ti in the Ti layer 15 diffuses through the circuit layer 12. Thereby, the first intermetallic compound layer 16 is formed. Here, Cu and Ti diffuse in solids. The first intermetallic compound layer 16 includes at least one or more of a Cu.sub.4Ti phase, a Cu.sub.3Ti.sub.2 phase, a Cu.sub.4Ti.sub.3 phase, a CuTi phase, and a CuTi.sub.2 phase. In the embodiment, the first intermetallic compound layer 16 has the Cu.sub.4Ti phase, the Cu.sub.3Ti.sub.2 phase, the Cu.sub.4Ti.sub.3 phase, the CuTi phase, and the CuTi.sub.2 phase.

(31) In the embodiment, the thickness of the first intermetallic compound layer 16 is set to be 0.5 m to 10 m.

(32) When the thickness of the first intermetallic compound layer 16 is 0.5 m or more, Cu in the circuit layer 12 sufficiently diffuses through the Ti layer 15 and Ti in the Ti layer 15 sufficiently diffuses through the circuit layer 12. Thus, it is possible to sufficiently ensure the bonding strength between the circuit layer 12 and the Ti layer 15. When the thickness of the first intermetallic compound layer 16 is 10 m or less, the rigid first intermetallic compound layer 16 is thin. Thus, when the power module substrate 10 undergoes a thermal cycle, it is possible to reduce the thermal stress being generated in the ceramic substrate 11 and to limit the occurrence of cracking.

(33) For this reason, the thickness of the first intermetallic compound layer 16 is set to be in the aforementioned range. The thickness of the first intermetallic compound layer 16 may be set to be 0.5 m to 7 m.

(34) P and Ni contained in the CuPSnNi brazing filler material 24 are combined with Ti contained in the Ti foil 25, and thereby the second intermetallic compound layer 17 is formed. In the embodiment, as shown in FIG. 3, the second intermetallic compound layer 17 has a PNiTi layer 17a, a PTi layer 17b, and a CuNiTi layer 17c which are formed in this order from the CuSn layer 14. The thickness of the second intermetallic compound layer 17, that is, the total thickness of the PNiTi layer 17a, the PTi layer 17b, and the CuNiTi layer 17c may be 0.5 m to 6 m.

(35) The semiconductor element 3 is made of a semiconductor material such as Si. The semiconductor element 3 and the circuit layer 12 are bonded to each other through the bonding layer 2.

(36) The bonding layer 2 is made of a SnAg-based solder material, a SnIn-based solder material, a SnAgCu-based solder material, or the like.

(37) Hereinafter, a method of producing the power module substrate 10 and the power module 1 in the embodiment will be described with reference to the flowchart in FIG. 4, and FIG. 5.

(38) First, as shown in FIG. 5, the CuPSnNi brazing filler material 24, the Ti foil 25, and the Cu foil 22 which forms into the circuit layer 12 are sequentially laminated on the first surface (an upper surface in FIG. 5) which is one surface of the ceramic substrate 11 (laminating step S01). That is, between the ceramic substrate 11 and the Cu foil 22, the CuPSnNi brazing filler material 24 is disposed close to the ceramic substrate 11, and the Ti foil 25 is disposed close to the Cu foil 22.

(39) In the embodiment, the compositions of the CuPSnNi brazing filler material 24 are Cu, 7 mass % of P, 15 mass % of Sn, and 10 mass % of Ni.

(40) The thickness of the CuPSnNi brazing filler material 24 is in a range of 5 m to 150 m. In the embodiment, the CuPSnNi brazing filler material with the thickness of 20 m is used.

(41) The Ti foil 25 has a thickness of 6 m to 25 m and a purity of 99.4% or more. In the embodiment, Ti foil with a thickness of 10 m and a purity of 99.8%.

(42) Subsequently, the ceramic substrate 11, the CuPSnNi brazing filler material 24, the Ti foil 25, and the Cu foil 22 are placed into and heated in a vacuum heating furnace while being pressurized (at a pressure of 1 kgf/cm.sup.2 to 35 kgf/cm.sup.2 (0.10 MPa to 3.43 MPa)) in a laminating direction (heating step S02). In the embodiment, the internal pressure of the vacuum heating furnace is set to be in a range of 10.sup.6 Pa to 10.sup.3 Pa, the heating temperature is set to be in a range of 600 C. to 650 C., and the heating time is set to be in a range of 30 minutes to 360 minutes.

(43) In the heating step S02, the Ti foil 25 and the Cu foil 22 are bonded through the diffusion in solids. CuPSnNi brazing filler material 24 is melted to form a liquid phase, the liquid phase is solidified, and thereby the ceramic substrate 11 and the Ti foil 25 are bonded to each other. At this time, the first intermetallic compound layer 16 made of Ti and Cu is formed at the bonded interface between the Cu foil 22 (the circuit layer 12) and the Ti foil 25 (the Ti layer 15). P and Ni contained in the CuPSnNi brazing filler material 24 are combined with Ti contained in the Ti foil 25, and thereby the second intermetallic compound layer 17 is formed. The CuSn layer 14 not containing P and Ni or containing a very small amounts of P and Ni is formed close to the ceramic substrate 11.

(44) As a result, the circuit layer 12 is formed on the first surface of the ceramic substrate 11 such that the power module substrate 10 in the embodiment is produced.

(45) Subsequently, the semiconductor element 3 is bonded to the upper surface of the circuit layer 12 of the power module substrate 10 through the solder material (semiconductor element-bonding step S03).

(46) As such, the power module 1 in the embodiment is produced.

(47) In the power module substrate 10 with such a configuration according to the embodiment, at the bonded interface between the ceramic substrate 11 and the circuit layer 12, P and Ni contained in the CuPSnNi brazing filler material 24 are drawn into the second intermetallic compound layer 17 formed close to the Ti layer 15. Thereby, the CuSn layer 14 without an intermetallic compound containing P and Ni or with a very small amount of an intermetallic compound containing P and Ni is formed close to the ceramic substrate 11. That is, since a rigid intermetallic compound is not formed in the vicinity of the ceramic substrate 11, it is possible to reduce thermal stress generating in the ceramic substrate 11 when the power module substrate 10 undergoes a thermal cycle. As a result, it is possible to limit the occurrence of cracking in the ceramic substrate 11. Further, since a brittle intermetallic compound is not formed in the vicinity of the ceramic substrate 11, it is possible to limit a decrease in the bonding rate between the ceramic substrate 11 and the circuit layer 12 when the power module substrate 10 undergoes a thermal cycle, and it is possible to improve the reliability of bonding.

(48) The Ti layer 15 is formed between the CuSn layer 14 and the circuit layer 12, and thus it is possible to prevent Sn from diffusing to the circuit layer 12. Therefore, when the circuit layer 12 is formed on the first surface of the ceramic substrate 11 using the CuPSnNi brazing filler material 24, it is possible to prevent a decrease in the Sn concentration in the CuPSnNi brazing filler material 24, and thus to limit an increase in the melting point of the CuPSnNi brazing filler material 24. That is, by limiting the increase in the melting point of the CuPSnNi brazing filler material 24, the bonding can be performed at comparatively low temperature, and thus it is possible to limit the thermal degradation of the ceramic substrate 11.

(49) The thickness of the Ti layer 15 is preferably set to be 1 m to 15 m, and thus it is possible to reliably prevent Sn from diffusing to the circuit layer 12. In addition, in this case, the Ti layer with relatively high strength is thin. Therefore, thermal stress generating in the ceramic substrate 11 is reduced when the power module substrate 10 undergoes a thermal cycle, and it is possible to limit the occurrence of cracking in the ceramic substrate 11.

(50) Since the first intermetallic compound layer 16 made of Cu and Ti is formed between the circuit layer 12 and the Ti layer 15, Cu in the circuit layer 12 sufficiently diffuses through the Ti layer 15 and Ti in the Ti layer 15 sufficiently diffuses through the circuit layer 12. Thus, the circuit layer 12 and the Ti layer 15 are bonded sufficiently.

(51) The thickness of the first intermetallic compound layer 16 is set to be 0.5 m to 10 m. Thus, since Cu in the circuit layer 12 sufficiently diffuses through the Ti layer 15 and Ti in the Ti layer 15 sufficiently diffuses through the circuit layer 12, the sufficient bonding strength can be ensured. In addition to this, since the rigid first intermetallic compound layer 16 is thin, it is possible to reduce thermal stress generating in the ceramic substrate 11 when the power module substrate 10 undergoes a thermal cycle, and to limit the occurrence of cracking.

(52) In the power module substrate 10 and the power module 1 according to the embodiment, the circuit layer 12 made of the Cu foil 22 is formed on the first surface which is one surface of the ceramic substrate 11, and thus it is possible to spread out heat from the semiconductor element 3, and to dissipate heat to the ceramic substrate 11. Since the Cu foil 22 has a relatively high resistance to deformation, when the power module substrate 10 undergoes a thermal cycle, it is possible to limit deformation of the circuit layer 12. As a result, it is possible to limit deformation of the bonding layer 2 bonding the semiconductor element 3 to the circuit layer 12, and it is possible to improve the reliability of bonding between the semiconductor element 3 and the circuit layer 12.

(53) According to the method of producing the power module substrate 10 in the embodiment, since the ceramic substrate 11 and the Cu foil 22 is subjected to a heating process with the CuPSnNi brazing filler material 24 and the Ti foil 25 being interposed therebetween, during heating, Ti is melted into the liquid phase of the melted CuPSnNi brazing filler material 24, and wettability between the ceramic substrate 11 and the liquid phase of the CuPSnNi brazing filler material 24 is improved.

(54) When the heating temperature is 600 C. or higher in the heating step S02, the CuPSnNi brazing filler material 24 can be reliably melted at the bonded interface between the ceramic substrate 11 and the Cu foil 22. In addition to this, the Ti foil 25 and the Cu foil 22 are bonded to each other through a sufficient diffusion in solids. Therefore, the ceramic substrate 11 and the Cu foil 22 can be reliably bonded to each other. When the heating temperature is 650 C. or less, it is possible to limit the thermal degradation of the ceramic substrate 11, and to reduce thermal stress generating in the ceramic substrate 11. For this reason, in the embodiment, the heating temperature is set to be in a range of 600 C. to 650 C.

(55) When pressure applied to the ceramic substrate 11 and the like is 1 kgf/cm.sup.2 (0.10 MPa) or greater in the heating step S02, since the ceramic substrate 11 is capable of coming into close contact with the liquid phase of the CuPSnNi brazing filler material 24, the ceramic substrate 11 and the CuSn layer 14 can be sufficiently bonded to each other. When the pressure applied is 1 kgf/cm.sup.2 or greater, the occurrence of a gap being generated between the Ti foil 25 and the Cu foil 22 can be limited, and the Ti foil 25 and the Cu foil 22 can be bonded to each other by diffusion in solids. For this reason, in the embodiment, the applied pressure is set to be in a range of 1 kgf/cm.sup.2 to 35 kgf/cm.sup.2 (0.10 MPa to 3.43 MPa).

(56) When the heating time is 30 minutes or more in the heating step S02, since it is possible to ensure a sufficient amount of time required when P contained in the melted CuPSnNi brazing filler material 24 is combined with Ti contained in the Ti foil at the bonded interface between the ceramic substrate 11 and the Cu foil 22, the CuSn layer can be reliably formed close to the ceramic substrate 11. Further, when the heating time is 30 minutes or more, the Ti foil 25 and the Cu foil 22 are bonded to each other by sufficient diffusion in solids. Therefore, the ceramic substrate 11 and the Cu foil 22 can be reliably bonded to each other. Even when the heating time exceeds 360 minutes, bondability between the ceramic substrate 11 and the circuit layer 12 is not improved compared to the case in which the heating time is 360 minutes. When the heating time exceeds 360 minutes, productivity is decreased. For this reason, in the embodiment, the heating time is set to be in a range of 30 minutes to 360 minutes.

(57) In the embodiment, since the CuPSnNi brazing filler material 24 with a melting point of 580 C. is used, it is possible to form a liquid phase of the brazing filler material at a low temperature. In the embodiment, the solidus temperature of the CuPSnNi brazing filler material is used as a melting point.

(58) As described above, CuPSnNi brazing filler material 24 is sufficiently bonded to ceramics substrate 11, and the Ti foil 25 and the Cu foil are bonded to each other by diffusion in solids. As a result, the ceramics substrate 11 and the Cu foil 22 are sufficiently bonded to each other, and it is possible to improve the reliability of bonding between the ceramic substrate 11 and the circuit layer 12.

Second Embodiment

(59) Hereinafter, a second embodiment of the present invention will be described. The same reference signs will be assigned to the same configuration elements as in the first embodiment, and detailed descriptions thereof will be omitted.

(60) FIG. 6 shows a power module 101 including a power module substrate 110 in the second embodiment.

(61) The power module 101 includes: the power module substrate 110 in which a circuit layer 112 is provided on the first surface of the ceramic substrate 11; the semiconductor element 3 that is bonded to a surface at one side (an upper surface in FIG. 6) of the circuit layer 112 through the bonding layer 2; and a heat sink 130 disposed on the other side (a lower side in FIG. 6) of the power module substrate 110.

(62) As shown in FIG. 7, the power module substrate 110 includes: the ceramic substrate 11; the circuit layer 112 provided on the first surface (an upper surface in FIG. 7) which is one surface of the ceramic substrate 11; and a metal layer 113 provided on the second surface (a lower surface in FIG. 7) which is the other surface of the ceramic substrate 11.

(63) The ceramic substrate 11 is made of aluminum nitride (AlN) having good heat radiation.

(64) Similar to the first embodiment, the circuit layer 112 is formed by bonding a Cu foil 122 to the ceramic substrate 11 through the heating of the CuPSnNi brazing filler material 24, Ti foil 25 as the Ti material, and the Cu foil 122 made of oxygen-free copper, which are sequentially laminated on the first surface of the ceramic substrate 11 (refer to FIG. 10).

(65) The thickness of the circuit layer 112 is set to be in a range of 0.1 mm to 1.0 mm. In the second embodiment, the thickness is set to 0.6 mm.

(66) Similar to the first embodiment, the CuSn layer (a first CuSn layer) 14 and the Ti layer (a first Ti layer) 15 are formed at the bonded interface between the ceramic substrate 11 and the circuit layer 112. The CuSn layer 14 is positioned close to the ceramic substrate 11. The Ti layer 15 is positioned between the circuit layer 112 and the CuSn layer 14. Further, a first intermetallic compound layer 16 made of Cu and Ti is formed between the circuit layer 112 and the Ti layer 15. A second intermetallic compound layer 17 containing P and Ni is formed between the CuSn layer 14 and the Ti layer 15.

(67) The metal layer 113 is formed by bonding a metal plate made of Cu or a Cu alloy to the second surface which is the other surface of the ceramic substrate 11 through a CuPSn-based brazing filler material. In the second embodiment, the metal layer 113 is formed by bonding the Cu foil 123 to the ceramic substrate 11 through the heating of the CuPSnNi brazing filler material 24, Ti foil 25 as the Ti material, and the Cu foil 123 made of oxygen-free copper, which are sequentially laminated on the second surface of the ceramic substrate 11 (refer to FIG. 10).

(68) The thickness of the metal layer 113 is set to be in a range of 0.1 mm to 1.0 mm. In the embodiment, the thickness is set to 0.6 mm.

(69) FIG. 8 shows a schematic view of the bonded interface between the ceramic substrate 11 and the metal layer 113. As shown in FIG. 8, a CuSn layer (a second CuSn layer) 114 and a Ti layer (a second Ti layer) 115 are formed at the bonded interface between the ceramic substrate 11 and the metal layer 113. The CuSn layer 114 is positioned close to the ceramic substrate 11. The Ti layer 115 is positioned between the metal layer 113 and the CuSn layer 114. A first intermetallic compound layer (a third intermetallic compound layer) 116 made of Cu and Ti is formed between the metal layer 113 and the Ti layer 115. A second intermetallic compound layer (a fourth intermetallic compound layer) 117 containing P and Ni is formed between the CuSn layer 114 and the Ti layer 115. The second intermetallic compound layer 117 has a PNiTi layer 117a, a PTi layer 117b, and a CuNiTi layer 117c which are formed in this order from the CuSn layer 114.

(70) That is, the CuSn layer (the second CuSn layer) 114 has substantially the same structure as that of the CuSn layer (the first CuSn layer) 14, the Ti layer (the second Ti layer) 115 has a substantially the same structure as that of the Ti layer (the first Ti layer) 15, the first intermetallic compound layer (the third intermetallic compound layer) 116 has substantially the same structure as that of the first intermetallic compound layer 16, and the second intermetallic compound layer (the fourth intermetallic compound layer) 117 has substantially the same structure as that of the second intermetallic compound layer 17. The bonded interface between the ceramic substrate 11 and the metal layer 113 has the same structure as that of the bonded interface between the ceramic substrate 11 and the circuit layer 112.

(71) The heat sink 130 dissipates heat from the power module substrate 110. The heat sink 130 is made of Cu or a Cu alloy. In the embodiment, the heat sink 130 is made of oxygen-free copper. The heat sink 130 is provided with flow passages 131 through which a coolant flows. In the embodiment, the heat sink 130 and the metal layer 113 are bonded to each other through a solder layer 132 made of a solder material.

(72) Hereinafter, a method of producing the power module 101 in the embodiment will be described with reference to the flowchart in FIG. 9, and FIG. 10.

(73) First, as shown in FIG. 10, the CuPSnNi brazing filler material 24, the Ti foil 25, and the Cu foil 122 which forms into the circuit layer 112 are sequentially laminated on the first surface (an upper surface in FIG. 10) of the ceramic substrate 11 (a first laminating step S11). The CuPSnNi brazing filler material 24, the Ti foil 25, and the Cu foil 123 which forms into the metal layer 113 are sequentially laminated on the second surface (a lower surface in FIG. 10) of the ceramic substrate 11 (a second laminating step S12). That is, the CuPSnNi brazing filler material 24 is disposed close to the ceramic substrate 11, and the Ti foil 25 is disposed close to each of the Cu foils 122, 123 between the ceramic substrate 11 and each of the Cu foils 122, 123. The thickness of the Ti foil 25 is set to be in a range of 6 m to 25 m, and in the embodiment, the Ti foil 25 with a thickness of 8 m is used.

(74) Subsequently, the ceramic substrate 11, the CuPSnNi brazing filler material 24, the Ti foil 25, and the Cu foils 122 and 123 are placed into and heated in a vacuum heating furnace while being pressurized (at a pressure of 1 kgf/cm.sup.2 to 35 kgf/cm.sup.2 (0.10 MPa to 3.43 MPa)) in a laminating direction (heating step S13). In the second embodiment, the internal pressure of the vacuum heating furnace is set to be in a range of 10.sup.6 Pa to 10.sup.3 Pa, the heating temperature is set to be in a range of 600 C. to 650 C., and the heating time is set to be in a range of 30 minutes to 360 minutes.

(75) In the heating step S13, the Ti foil 25 and the Cu foil 122, 123 are bonded to each other through diffusion in solids. Further, the CuPSnNi brazing filler material 24 is melted to form a liquid phase, and the liquid phase is solidified. Thereby, the ceramic substrate 11 and the Ti foil 25 are bonded to each other through the CuPSnNi brazing filler material 24.

(76) Accordingly, the circuit layer 112 and the metal layer 113 are respectively formed on the first surface and the second surface of the ceramic substrate 11, and thereby the power module substrate 110 in the embodiment is produced.

(77) Subsequently, the heat sink 130 is bonded to a lower surface of the metal layer 113 of the power module substrate 110 through a solder material (heat sink bonding step S14).

(78) Subsequently, the semiconductor element 3 is bonded to the upper surface of the circuit layer 112 of the power module substrate 110 through a solder material (semiconductor element-bonding step S15).

(79) As such, the power module 101 in the embodiment is produced.

(80) The power module substrate 110 with such a configuration according to the second embodiment provides the same effects as the power module substrate 10 in the first embodiment.

(81) The metal layer 113 made of the Cu foil 123 is formed on the second surface of the ceramic substrate 11, and thus the power module substrate 110 is capable of efficiently dissipating heat from the semiconductor element 3 through the metal layer 113.

(82) Similar to the bonded interface between the ceramic substrate 11 and the circuit layer 112, at the bonded interface between the ceramic substrate 11 and the metal layer 113, the CuSn layer 114, in which Sn forms a solid solution with Cu, is formed closed to the ceramic substrate 11, and a rigid intermetallic compound is not formed in the vicinity of the ceramic substrate 11. For this reason, when the power module substrate 110 undergoes a thermal cycle, it is possible to reduce thermal stress generating in the ceramic substrate 11 and to limit the occurrence of cracking in the ceramic substrate 11. Further, since a brittle intermetallic compound layer is not formed in the vicinity of the ceramic substrate 11, it is possible to limit a decrease in the bonding rate between the ceramic substrate 11 and the metal layer 113 when the power module substrate 110 undergoes a thermal cycle, and it is possible to improve the reliability of bonding.

(83) Since the heat sink 130 is bonded to the metal layer 113, the power module substrate 110 in the second embodiment is capable of efficiently dissipating heat through the heat sink 130.

(84) According to the method of producing the power module substrate 110 in the second embodiment, the circuit layer 112 and the metal layer 113 are respectively bonded to the first surface which is one surface of the ceramic substrate 11 and the second surface which is the other surface of the ceramic substrate 11, simultaneously. As a result, it is possible to simplify a producing process, and to reduce production costs.

Third Embodiment

(85) Hereinafter, a third embodiment of the present invention will be described. The same reference signs will be assigned to the same configuration elements as in the first embodiment, and detailed descriptions thereof will be omitted.

(86) FIG. 11 shows a power module 201 including a power module substrate 210 in the third embodiment.

(87) The power module 201 includes: the power module substrate 210 in which a circuit layer 212 is provided on the first surface of the ceramic substrate 11; the semiconductor element 3 that is bonded to a surface at one side (an upper surface in FIG. 11) of the circuit layer 212 through the bonding layer 2; and a heat sink 230 bonded to the other side (a lower side in FIG. 11) of the power module substrate 210 through a bonding layer 232.

(88) As shown in FIG. 12, the power module substrate 210 includes: the ceramic substrate 11; the circuit layer 212 provided on the first surface (an upper surface in FIG. 12) which is one surface of the ceramic substrate 11; and a metal layer 213 provided on the second surface (a lower surface in FIG. 12) which is the other surface of the ceramic substrate 11.

(89) The ceramic substrate 11 is made of aluminum nitride (AlN) having good heat radiation.

(90) Similar to the first embodiment, the circuit layer 212 is formed by bonding a Cu foil 222 to the ceramic substrate 11 through the heating of the CuPSnNi brazing filler material 24, Ti foil 25 as the Ti material, and the Cu foil 222 made of oxygen-free copper, which are sequentially laminated on the first surface of the ceramic substrate 11 (refer to FIG. 14).

(91) The thickness of the circuit layer 212 is set to be in a range of 0.1 mm to 1.0 mm. In the third embodiment, the thickness is set to 0.6 mm.

(92) Similar to the first embodiment, the CuSn layer 14 and the Ti layer 15 are formed at the bonded interface between the ceramic substrate 11 and the circuit layer 212. The CuSn layer 14 is positioned close to the ceramic substrate 11. The Ti layer 15 is positioned between the circuit layer 212 and the CuSn layer 14. Further, the first intermetallic compound layer 16 made of Cu and Ti is formed between the circuit layer 212 and the Ti layer 15. A second intermetallic compound layer 17 containing P and Ni is formed between the CuSn layer 14 and the Ti layer 15.

(93) The metal layer 213 is formed by bonding a metal plate made of Al or an Al alloy to the second surface which is the other surface of the ceramic substrate 11 through a bonding material 227. In the third embodiment, the metal layer 213 is formed by bonding an Al plate 223 with a purity of 99.99 mass % or more to the second surface of the ceramic substrate 11 (refer to FIG. 14).

(94) The thickness of the metal layer 213 is set to be in a range of 0.1 mm to 3.0 mm. In the embodiment, the thickness is set to 1.6 mm.

(95) The heat sink 230 is made of Al or an Al alloy. In the embodiment, the heat sink 230 is made of A6063 (Al alloy). The heat sink 230 is provided with flow passages 231 through which a coolant flows. The heat sink 230 and the metal layer 213 are bonded to each other through an AlSi-based brazing filler material.

(96) Hereinafter, a method of producing the power module 201 in the embodiment will be described with reference to the flowchart in FIG. 13, and FIG. 14.

(97) First, as shown in FIG. 14, the CuPSnNi brazing filler material 24, the Ti foil 25, and the Cu foil 222 which forms into the circuit layer 212 are sequentially laminated on the first surface (an upper surface in FIG. 14) of the ceramic substrate 11 (a first laminating step S21). The Al plate 223 which forms into the metal layer 213 is laminated on the second surface (a lower surface in FIG. 14) of the ceramic substrate 11 with the bonding material 227 interposed between the Al plate 223 and the ceramic substrate 11 (a second laminating step S22). The heat sink 230 is laminated on a lower side of the Al plate 223 with a bonding material 242 interposed between the heat sink 230 and the Al plate 223 (a third laminating step S23).

(98) In the embodiment, the bonding materials 227 and 242 are AlSi-based brazing filler materials containing Si which lowers a melting point. In the third embodiment, an AlSi (7.5 mass %) brazing filler material is used.

(99) The thickness of the Ti foil 25 is set to be in a range of 6 m to 25 m, and in the embodiment, the Ti foil 25 with a thickness of 12 m is used.

(100) Subsequently, the ceramic substrate 11, the CuPSnNi brazing filler material 24, the Ti foil 25, the Cu foil 222, the bonding material 227, the Al plate 223, the bonding material 242, and the heat sink 230 are placed into and heated in a vacuum heating furnace while being pressurized (at a pressure of 1 kgf/cm.sup.2 to 35 kgf/cm.sup.2 (0.10 MPa to 3.43 MPa)) in a laminating direction (heating step S24). In the third embodiment, the internal pressure of the vacuum heating furnace is set to be in a range of 10.sup.6 Pa to 10.sup.3 Pa, the heating temperature is set to be in a range of 600 C. to 650 C., and the heating time is set to be in a range of 30 minutes to 360 minutes.

(101) In the heating step S24, the Ti foil 25 and the Cu foil 222 are bonded to each other by diffusion in solids. Further, the CuPSnNi brazing filler material 24 is melted to form a liquid phase, and the liquid phase is solidified. Thereby, the ceramic substrate 11 and the Ti foil 25 are bonded to each other. In the heating step S24, the bonding material 227 is melted to form a liquid phase, and the liquid phase is solidified. Thereby, the ceramic substrate 11 and the Al plate 223 are bonded to each other through the bonding material 227. In the heating step S24, the bonding material 242 is melted to form a liquid phase, and the liquid phase is solidified. Thereby, the Al plate 223 and the heat sink 230 are bonded to each other through the bonding material 242.

(102) Accordingly, the power module substrate 210 in the third embodiment is produced.

(103) Subsequently, the semiconductor element 3 is bonded to the upper surface of the circuit layer 212 of the power module substrate 210 through a solder material (semiconductor element-bonding step S25).

(104) As such, the power module 201 in the third embodiment is produced.

(105) The power module substrate 210 with such a configuration according to the third embodiment provides the same effects as the power module substrate 10 in the first embodiment.

(106) The Al plate 223 is bonded to the second surface of the ceramic substrate 11 such that the metal layer 213 is formed, and thus the power module substrate 210 in the third embodiment is capable of efficiently dissipating heat from the semiconductor element 3 through the metal layer 213. Since Al has a relatively low resistance to deformation, when the power module substrate 210 undergoes a thermal cycle, the metal layer 213 is capable of absorbing thermal stress occurring between the power module substrate 210 and the heat sink 230. As a result, it is possible to limit the occurrence of cracking in the ceramic substrate 11.

(107) According to the method of producing the power module substrate 210 in the third embodiment, the circuit layer 212 and the metal layer 213 are respectively bonded to the first surface and the second surface of the ceramic substrate 11 simultaneously. At this time, the heat sink 230 is also bonded to the metal layer 213 simultaneously. As a result, it is possible to simplify a producing process, and to reduce producing costs.

(108) The embodiments of the present invention have been described; however, the present invention is not limited to the embodiments, and modifications can be appropriately made to the embodiments insofar as the modifications do not depart from the technical spirit of the invention.

(109) In the second and third embodiments, the circuit layer and the metal layer are respectively bonded to the first surface and the second surface of the ceramic substrate simultaneously; however, the circuit layer and the metal layer may be independently bonded to the respective surfaces of the ceramic substrate.

(110) In the third embodiment, the bonding of the circuit layer, the metal layer, and the heat sink is performed simultaneously; however, after the circuit layer and the metal layer are bonded to the ceramic substrate, the metal layer and the heat sink may be bonded to each other.

(111) In the third embodiment, the metal layer is bonded to the second surface of the ceramic substrate through an AlSi-based brazing filler material; however, the metal layer may be bonded to the second surface of the ceramic substrate by a transient liquid phase (TLP) bonding method, an Ag paste, or the like.

(112) In the second and third embodiments, the heat sink with the flow passages are used; however, a plate-like heat sink called a heat radiation plate, or a heat sink with pin-like tins may be used. The power module substrate and the heat sink are bonded to each other through a solder material or a brazing filler material; however, grease may be applied between the power module substrate and the heat sink, and the power module substrate and the heat sink may be fixed together with screws. In the power module substrates according to the second and third embodiments, the heat sink may not be bonded to the other surface of the power module substrate (the second surface of the ceramic substrate).

(113) In the above-described embodiments, Ti foil is used as a Ti material; however, it is possible to use a Cu member/Ti clad material in which Ti is provided on one surface of a Cu member. Alternately, the Cu member on which Ti is disposed by vapor deposition or the like, may be used.

(114) In addition, it is possible to use a Ti material/brazing clad material in which a CuPSn-based brazing filler material is provided on one surface of a Ti material, or a Cu member/Ti material/brazing clad material in which a Cu member, a Ti material, and a CuPSn-based brazing filler material are sequentially laminated.

(115) In the above-described embodiments, Ti foil is used as a Ti material; however, the present invention is not limited to this configuration, and hydrogenated titanium may be used as the Ti material.

EXAMPLES

Example 1

(116) Hereinafter, results of confirmation tests (Example 1) performed to confirm the effects of the embodiments of the present invention will be described.

(117) Sheets of CuPSn-based brazing filler foil (37 mm37 mm) with thicknesses shown in Table 1; Ti foils (37 mm37 mm) with thicknesses shown in Table 1; and Cu foils (37 mm37 mm0.3 mm thickness) made of oxygen-free copper were sequentially laminated on first surfaces of ceramic substrates (40 mm40 mm) shown in Table 1. When the material of the ceramic substrate was AlN, the thickness of the ceramic substrate was set to 0.635 mm, and when the material was Si.sub.3N.sub.4, the thickness was set to 0.32 mm.

(118) While being pressurized at a pressure of 15 kgf/cm.sup.2 (1.47 MPa) in a laminating direction, the ceramic substrate, the CuPSn-based brazing filler material, the Ti foil, and the Cu foil, which were laminated, were placed into and heated in a vacuum heating furnace. Thereby, the Cu foil was bonded to the first surface of the ceramic substrate, and a circuit layer was formed. The internal pressure of the vacuum heating furnace was set to be in a range of 10.sup.6 Pa to 10.sup.3 Pa, and the heating temperature and the heating time were set to the conditions shown in Table 1. As such, the power module substrates in Examples 1-1 to 1-13 of the present invention were obtained.

(119) A power module substrate in Comparative Example 1 was obtained in the following manner. CuPSn-based brazing filler foils (37 mm37 mm) with thicknesses shown in Table 1 and Cu foils (37 mm37 mm0.3 mm thickness) made of oxygen-free copper were sequentially laminated on first surfaces of ceramic substrates (40 mm40 mm0.635 mm thickness) made of AlN. While being pressurized at a pressure of 15 kgf/cm.sup.2 (1.47 MPa) in a laminating direction, the ceramic substrate, the CuPSn-based brazing filler material, and the Cu foil, which were laminated, were placed into and heated in a vacuum heating furnace. Thereby, the Cu foil was bonded to the first surface of the ceramic substrate, and a circuit layer was formed.

(120) That is, in the power module substrate of Comparative Example 1, the ceramic substrate and the Cu foil were bonded to each other without a Ti foil being interposed therebetween.

(121) In each of the power module substrates obtained in the aforementioned manner, the initial bonding rate between the circuit layer and the ceramic substrate was evaluated. A method of evaluating the bonding rate will be described below.

(122) In each of the obtained power module substrates, the thicknesses of the Ti layer and the first intermetallic compound layer were measured at the bonded interface between the ceramic substrate and the circuit layer. A method of measuring the thickness of the Ti layer and the first intermetallic compound layer will be described below.

(123) (Evaluation of Bonding Rate)

(124) In the power module substrate, the bonding rate of the interface between the ceramic substrate and the circuit layer was evaluated by an ultrasonic flaw detector (FineSAT200 manufactured by Hitachi Power Solutions), and was calculated by the following expression.

(125) An initial bonding area was an area before bonding, which has to be bonded. In the examples, the initial bonding area was the area (37 mm37 mm) of the circuit layer. Exfoliation in an image obtained by binarizing an ultrasonic-detected image was shown by a white portion in a bonding portion, and thus the area of the white portion was deemed to be an exfoliation area.
(Bonding Rate (%))=((Initial Bonding Area)(Exfoliation Area))/(Initial Bonding Area)100

(126) (Method of Measuring Thicknesses of Ti Layer and First Intermetallic Compound Layer)

(127) The thicknesses of the Ti layer and the first intermetallic compound layer were measured by the following method. A backscattered electron image of interface between the Cu foil and the Ti layer (in section in parallel with the laminating direction) was obtained using Electron Micro Analyzer (EPMA) (JXA-8530F manufactured by JEOL). In a visual field with magnification of 3,000-fold (30 m vertical (in the laminating direction)40 m horizontal), area of the Ti layer and total area of the first intermetallic compound layer (Cu.sub.4Ti, Cu.sub.3Ti.sub.2, Cu.sub.4Ti.sub.3, CuTi, CuTi.sub.2) formed at the bonded interface were measured. Each of the area of the Ti layer and the total area of the first intermetallic compound layer was divided by the horizontal length (40 m) of the visual field. Thereby, the thicknesses of the Ti layer and the first intermetallic compound layer in the visual field were obtained. The averages of the thicknesses of the Ti layer and the first intermetallic compound layer obtained in five visual fields is determined as the thicknesses of the Ti layer and the first intermetallic compound layer, respectively.

(128) Results of the aforementioned evaluations were shown in Table 1.

(129) TABLE-US-00001 TABLE 1 Thickness Melting of Point CuPSn- of Thickness based CuPSn- Thick- Thick- of First Brazing based ness Material Heating ness Intermetallic Initial Components of Filler Brazing of Ti of Conditions of Ti Compound Bonding CuPSn-based Material Filler Foil Ceramic Temper- Layer Layer Rate Brazing Filler Material m Material m Substrate ature Time m m % Example Cu-6.3 mass % of P-9.3 20 600 C. 9 AlN 650 C. 90 3 5 99.1 1-1 mass % of Sn-7 mass % of Ni min. Example Cu-7 mass % of P-15 mass % 20 580 C. 8 AlN 650 C. 90 1 5 99.6 1-2 of Sn-10 mass % of Ni min. Example Cu-7 mass % of P-15 mass % 20 580 C. 20 AlN 650 C. 90 15 5 98.6 1-3 of Sn-10 mass % of Ni min. Example Cu-7 mass % of P-15 mass % 20 580 C. 15 AlN 630 C. 30 8 0.5 97.2 1-4 of Sn-10 mass % of Ni min. Example Cu-7 mass % of P-15 mass % 20 580 C. 10 AlN 650 C. 300 4 10 100.0 1-5 of Sn-10 mass % of Ni min. Example Cu-7 mass % of P-15 mass % 20 580 C. 6 AlN 630 C. 120 0.5 4 96.3 1-6 of Sn-10 mass % of Ni min. Example Cu-7 mass % of P-15 mass % 20 580 C. 20 AlN 600 C. 120 18 2 94.1 1-7 of Sn-10 mass % of Ni min. Example Cu-7 mass % of P-15 mass % 20 580 C. 12 AlN 600 C. 30 7 0.3 92.4 1-8 of Sn-10 mass % of Ni min. Example Cu-7 mass % of P-15 mass % 20 580 C. 10 AlN 650 C. 360 2 12 97.8 1-9 of Sn-10 mass % of Ni min. Example Cu-6.3 mass % of P-9.3 20 600 C. 9 Si.sub.3N.sub.4 650 C. 90 3 5 96.8 1-10 mass % of Sn-7 mass % of Ni min. Example Cu-7 mass % of P-15 mass % 20 580 C. 8 Si.sub.3N.sub.4 650 C. 90 1 5 97.0 1-11 of Sn-10 mass % of Ni min. Example Cu-7 mass % of P-15 mass % 20 580 C. 8 AlN 650 C. 90 1 5 98.2 1-12 of Sn-5 mass % of Mn min. Example Cu-7 mass % of P-15 mass % 20 580 C. 8 AlN 650 C. 90 1 5 98.8 1-13 of Sn-7 mass % of Cr min. Compar- Cu-7 mass % of P-15 mass % 20 580 C. AlN 650 C. 90 0.0 ative of Sn-10 mass % of Ni min. Example 1

(130) As shown in Table 1, in Examples 1-1 to 1-13 of the present invention, the ceramic substrate and the Cu foil were bonded together with the CuPSn-based brazing filler material and the Ti foil being interposed therebetween, and thus it was confirmed that the initial bonding rate between the ceramic substrate and the circuit layer was high, and the ceramic substrate and the circuit layer were sufficiently bonded to each other.

(131) In contrast, in Comparative Example 1, the ceramic substrate and the Cu foil were bonded to each other without the Ti foil being interposed therebetween, and thus the ceramic substrate and the Cu foil (circuit layer) could not be bonded together.

Example 2

(132) Hereinafter, results of confirmation tests (Example 2) performed to confirm the effects of the embodiments of the present invention will be described.

(133) Sheets of CuPSn-based brazing filler foil (37 mm37 mm) with thicknesses shown in Table 2; Ti foils (37 mm37 mm) with thicknesses shown in Table 2; and Cu foils (37 mm37 mm0.3 mm thickness) made of oxygen-free copper were sequentially laminated on first surfaces and second surfaces of ceramic substrates (40 mm40 mm) shown in Table 2. When the material of the ceramic substrate was AlN, the thickness of the ceramic substrate was set to 0.635 mm, and when the material was Si.sub.3N.sub.4, the thickness was set to 0.32 mm.

(134) While being pressurized at a pressure of 15 kgf/cm.sup.2 (1.47 MPa) in a laminating direction, the ceramic substrate, the CuPSn-based brazing filler material, the Ti foil, and the Cu foil, which were laminated, were placed into and heated in a vacuum heating furnace. Thereby, the Cu foils were respectively bonded to the first surface and the second surface of the ceramic substrate, and a circuit layer and a metal layer were formed. The internal pressure of the vacuum heating furnace was set to be in a range of 10.sup.6 Pa to 10.sup.3 Pa, and the heating temperature and the heating time were set to the conditions shown in Table 2. As such, the power module substrates in Examples 2-1 to 2-13 of the present invention were obtained.

(135) A power module substrate in Comparative Example 2 was obtained using a method which was the same as that used to obtain the power module substrates in Examples 2-1 to 2-13 except the fact that the ceramic substrate and the circuit layer were bonded to each other without the Ti foil being interposed therebetween.

(136) In each of the power module substrates obtained in the aforementioned manner, the initial bonding rate between the circuit layer and the ceramic substrate, and the bonding rate after the thermal cycle test were measured. The number of cycles of thermal cycle tests performed until the occurrence of cracking in the ceramic substrate of the power module substrate was measured, and the bonding rate after the thermal cycle test were evaluated. In each of the obtained power module substrates, the thicknesses of the Ti layer and the first intermetallic compound layer were measured at the bonded interface between the ceramic substrate and the circuit layer.

(137) Similar to Example 1, the bonding rate was evaluated, and the thicknesses of Ti layer and the first intermetallic compound layer were measured. The thermal cycle test was performed as described below.

(138) (Thermal Cycle Test)

(139) One cycle of the thermal cycle test was complete by placing the power module substrate in a liquid phase (Fluorinert) at 40 C. for 5 minutes and 150 C. for 5 minutes using a thermal shock tester TSB-51 manufactured by ESPEC. The thermal cycle tests were performed in 2000 cycles. The power module substrate, in which cracking did not occur in the ceramic substrate even after the thermal cycle tests were performed in 2000 cycles, was denoted by >2000 in Table 2.

(140) Results of the aforementioned evaluations were shown in Table 2.

(141) TABLE-US-00002 TABLE 2 Thickness of Melting Point CuPSn-based of Thickness Material Components of Brazing Filler CuPSn-based of of CuPSn-based Material Brazing Filler Ti Foil Ceramic Heating Conditions Brazing Filler Material m Material m Substrate Temperature Time Example Cu-6.3 mass % of P-9.3 mass % 20 600 C. 8 AlN 630 C. 90 min. 2-1 of Sn-7 mass % of Ni Example Cu-7 mass % of P-15 mass % 20 580 C. 8 AlN 650 C. 180 min. 2-2 of Sn-10 mass % of Ni Example Cu-7 mass % of P-15 mass % 20 580 C. 22 AlN 650 C. 180 min. 2-3 of Sn-10 mass % of Ni Example Cu-7 mass % of P-15 mass % 20 580 C. 12 AlN 630 C. 30 min. 2-4 of Sn-10 mass % of Ni Example Cu-7 mass % of P-15 mass % 20 580 C. 9 AlN 650 C. 300 min. 2-5 of Sn-10 mass % of Ni Example Cu-7 mass % of P-15 mass % 20 580 C. 7 AlN 650 C. 120 min. 2-6 of Sn-10 mass % of Ni Example Cu-7 mass % of P-15 mass % 20 580 C. 22 AlN 630 C. 120 min. 2-7 of Sn-10 mass % of Ni Example Cu-7 mass % of P-15 mass % 20 580 C. 13 AlN 600 C. 30 min. 2-8 of Sn-10 mass % of Ni Example Cu-7 mass % of P-15 mass % 20 580 C. 12 AlN 650 C. 360 min. 2-9 of Sn-10 mass % of Ni Example Cu-7 mass % of P-15 mass % 20 580 C. 22 Si.sub.3N.sub.4 650 C. 180 min. 2-10 of Sn-10 mass % of Ni Example Cu-7 mass % of P-15 mass % 20 580 C. 12 Si.sub.3N.sub.4 630 C. 30 min. 2-11 of Sn-10 mass % of Ni Example Cu-7 mass % of P-15 mass % 20 580 C. 8 AlN 650 C. 180 min. 2-12 of Sn-5 mass % of Mn Example Cu-7 mass % of P-15 mass % 20 580 C. 8 AlN 650 C. 180 min. 2-13 of Sn-7 mass % of Cr Comparative Cu-7 mass % of P-15 mass % 20 580 C. AlN 650 C. 90 min. Example 2 of Sn-10 mass % of Ni Thickness of First Bonding Cracking in Intermetallic Initial Rate After Ceramic Thickness of Compound Bonding Thermal Substrate Ti Layer Layer Rate Cycle Number of m m % % Thermal Cycles Example 2-1 4 3 97.2 96.8 >2000 Example 2-2 1 7 100.0 99.4 >2000 Example 2-3 15 7 100.0 97.2 >2000 Example 2-4 7 0.5 97.4 96.7 >2000 Example 2-5 2 10 98.5 97.8 >2000 Example 2-6 0.3 6 96.4 94.4 >2000 Example 2-7 20 4 97.3 97.1 1500-2000 Example 2-8 8 0.3 94.1 89.7 >2000 Example 2-9 4 12 97.9 94.6 1500-2000 Example 2-10 15 7 97.7 96.9 >2000 Example 2-11 7 0.5 95.7 94.8 >2000 Example 2-12 1 7 97.8 97.4 >2000 Example 2-13 1 7 98.9 98.1 >2000 Comparative Example 2 0.0

(142) As shown in Table 2, in Examples 2-1 to 2-13 of the present invention, the ceramic substrate and the Cu foil were bonded to each other with the CuPSn-based brazing filler material and the Ti foil being interposed therebetween, and thus it was confirmed that the initial bonding rate between the ceramic substrate and the circuit layer was high, and the ceramic substrate and the circuit layer were sufficiently bonded together. In Examples 2-1 to 2-13 of the present invention, it was confirmed that the bonding rate after the thermal cycle test was high, and the reliability of bonding was high. In Examples 2-1 to 2-13 of the present invention, it was confirmed that the number of cycles of thermal cycle tests, which were performed until the occurrence of cracking in the ceramic substrate, was large, and cracking was unlikely to occur in the ceramic substrate.

(143) In contrast, in Comparative Example 2, the ceramic substrate and the Cu foil were bonded to each other without the Ti foil being interposed therebetween, and thus the ceramic substrate and the Cu foil (circuit layer) could not be bonded to each other.

Example 3

(144) Hereinafter, results of confirmation tests (Example 3) performed to confirm the effects of the embodiments of the present invention will be described.

(145) Sheets of CuPSn-based brazing filler foil (37 mm37 mm) with thicknesses shown in Table 3; Ti foils (37 mm37 mm) with thicknesses shown in Table 3; and Cu foils (37 mm37 mm0.3 mm thickness) made of oxygen-free copper were sequentially laminated on first surfaces of ceramic substrates (40 mm40 mm) shown in Table 3. When the material of the ceramic substrate was AlN, the thickness of the ceramic substrate was set to 0.635 mm, and when the material was Si.sub.3N.sub.4, the thickness was set to 0.32 mm. An Al plate (37 mm37 mm1.6 mm thickness) made of Al with a purity of 99.99% was laminated on a second surface of the ceramic substrate with an AlSi-based brazing filler material (37 mm37 mm0.02 mm thickness) being interposed therebetween.

(146) The ceramic substrate, the CuPSn-based brazing filler material, the Ti foil, the Cu foil, the AlSi-based brazing filler material, and the Al plate, which were laminated, were placed into and heated in a vacuum heating furnace while being pressurized at a pressure of 15 kgf/cm.sup.2 (1.47 MPa) in a laminating direction. As a result, the Cu foil was bonded to the first surface of the ceramic substrate. Thereby, a circuit layer was formed. The Al plate was bonded to the second surface of the ceramic substrate, and thereby a metal layer was formed. The internal pressure of the vacuum heating furnace was set to be in a range of 10.sup.6 Pa to 10.sup.3 Pa, and the heating temperature and the heating time were set to the conditions shown in Table 3. As such, the power module substrates in Examples 3-1 to 3-13 of the present invention were obtained.

(147) A power module substrate in Comparative Example 3 was obtained using a method which was the same as that used to obtain the power module substrates in Examples 3-1 to 3-13 except the fact that the ceramic substrate and the circuit layer were bonded together without the Ti foil being interposed therebetween.

(148) The following was evaluated for each of the power module substrates obtained in the aforementioned manner: the initial bonding rate between the circuit layer and the ceramic substrate; the bonding rate after the thermal cycle test. In each of the obtained power module substrates, the thicknesses of the Ti layer and the first intermetallic compound layer were measured at the bonded interface between the ceramic substrate and the circuit layer.

(149) Similar to Example 2, the bonding rate was evaluated, the thermal cycle test was performed, and the thicknesses of Ti layer and the first intermetallic compound layer were measured.

(150) Results of the aforementioned evaluations are shown in Table 3.

(151) TABLE-US-00003 TABLE 3 Thickness of Melting Point CuPSn-based of Thickness Material Components of Brazing Filler CuPSn-based of of CuPSn-based Material Brazing Filler Ti Foil Ceramic Heating Conditions Brazing Filler Material m Material m Substrate Temperature Time Example Cu-6.3 mass % of P-9.3 mass % 20 600 C. 9 AlN 630 C. 60 min. 3-1 of Sn-7 mass % of Ni Example Cu-7 mass % of P-15 mass % 20 580 C. 6 AlN 650 C. 30 min. 3-2 of Sn-10 mass % of Ni Example Cu-7 mass % of P-15 mass % 20 580 C. 20 AlN 650 C. 30 min. 3-3 of Sn-10 mass % of Ni Example Cu-7 mass % of P-15 mass % 20 580 C. 8 AlN 630 C. 30 min. 3-4 of Sn-10 mass % of Ni Example Cu-7 mass % of P-15 mass % 20 580 C. 9 AlN 650 C. 300 min. 3-5 of Sn-10 mass % of Ni Example Cu-7 mass % of P-15 mass % 20 580 C. 6 AlN 650 C. 150 min. 3-6 of Sn-10 mass % of Ni Example Cu-7 mass % of P-15 mass % 70 580 C. 22 AlN 630 C. 90 min. 3-7 of Sn-10 mass % of Ni Example Cu-7 mass % of P-15 mass % 20 580 C. 10 AlN 600 C. 30 min. 3-8 of Sn-10 mass % of Ni Example Cu-7 mass % of P-15 mass % 20 580 C. 10 AlN 650 C. 360 min. 3-9 of Sn-10 mass % of Ni Example Cu-7 mass % of P-15 mass % 20 580 C. 8 Si.sub.3N.sub.4 630 C. 30 min. 3-10 of Sn-10 mass % of Ni Example Cu-7 mass % of P-15 mass % 20 580 C. 9 Si.sub.3N.sub.4 650 C. 300 min. 3-11 of Sn-10 mass % of Ni Example Cu-7 mass % of 13-15 mass % 20 580 C. 6 AlN 650 C. 30 min. 3-12 of Sn-5 mass % of Mn Example Cu-7 mass % of P-15 mass % 20 580 C. 6 AlN 650 C. 30 min. 3-13 of Sn-7 mass % of Cr Comparative Cu-7 mass % of P-15 mass % 20 580 C. AlN 650 C. 60 min. Example 3 of Sn-10 mass % of Ni Thickness of First Bonding Cracking in Intermetallic Initial Rate After Ceramic Thickness of Compound Bonding Thermal Substrate Ti Layer Layer Rate Cycle Number of m m % % Thermal Cycles Example 3-1 4 2 97.8 96.5 >2000 Example 3-2 1 3 99.4 97.5 >2000 Example 3-3 15 3 99.1 98.2 >2000 Example 3-4 3 0.5 97.2 96.8 >2000 Example 3-5 2 10 100.0 97.2 >2000 Example 3-6 0.2 7 96.2 90.7 >2000 Example 3-7 20 3 97.9 92.5 1000-1500 Example 3-8 4 0.3 93.3 90.0 >2000 Example 3-9 2 12 100.0 97.1 1500-2000 Example 3-10 3 0.5 95.7 93.1 >2000 Example 3-11 2 10 98.0 97.5 >2000 Example 3-12 1 3 98.2 96.7 >2000 Example 3-13 1 3 99.4 98.5 >2000 Comparative Example 3 0.0

(152) As shown in Table 3, in Examples 3-1 to 3-13 of the present invention, the ceramic substrate and the Cu foil were bonded to each other with the CuPSn-based brazing filler material and the Ti foil being interposed therebetween, and thus it was confirmed that the initial bonding rate between the ceramic substrate and the circuit layer was high, and the ceramic substrate and the circuit layer were sufficiently bonded to each other. In Examples 3-1 to 3-13 of the present invention, it was confirmed that the bonding rate after the thermal cycle test was high, and the reliability of bonding was high. In Examples 3-1 to 3-13 of the present invention, it was confirmed that the number of cycles of thermal cycle tests, which were performed until the occurrence of cracking in the ceramic substrate, was large, and cracking was unlikely to occur in the ceramic substrate.

(153) In contrast, in Comparative Example 3, the ceramic substrate and the Cu foil were bonded to each other without the Ti foil being interposed therebetween, and thus the ceramic substrate and the Cu foil (circuit layer) could not be bonded to each other.

INDUSTRIAL APPLICABILITY

(154) In the bonded body and the power module substrate of the present invention, when the bonded body and the power module substrate undergo a thermal cycle, the occurrence of cracking in the ceramic member can be limited and the reliability of bonding between the ceramic member and a Cu member can be improved. For this reason, the bonded body and the power module substrate of the present invention are suitably used in a power module under severe operating environments, for example, a high-power control power semiconductor element used to control wind power generation systems and electric vehicles such as electric automobiles.

REFERENCE SIGNS LIST

(155) 10, 110, 210: POWER MODULE SUBSTRATE (BONDED BODY) 11: CERAMIC SUBSTRATE (CERAMIC MEMBER) 12, 112, 212: CIRCUIT LAYER 13.113, 213: METAL, LAYER 14: CuSn LAYER (FIRST CuSn LAYER) 114: CuSn LAYER (SECOND CuSn LAYER) 15: Ti LAYER (FIRST Ti LAYER) 115: Ti LAYER (SECOND Ti LAYER) 16: FIRST INTERMETALLIC COMPOUND LAYER 17: SECOND INTERMETALLIC COMPOUND LAYER 116: FIRST INTERMETALLIC COMPOUND LAYER (THIRD INTERMETALLIC COMPOUND LAYER) 117: SECOND INTERMETALLIC COMPOUND LAYER (FOURTH INTERMETALLIC COMPOUND LAYER) 22, 122, 123, 222: Cu FOIL (Cu MEMBER)