FZ SILICON AND METHOD TO PREPARE FZ SILICON

Abstract

FZ silicon which shows no degradation of its minority carrier lifetime after any processing steps at a processing temperature of less than 900 C. is prepared by annealing FZ silicon at an annealing temperature of greater than or equal to 900 C. and processing the annealed FZ silicon at a processing temperature of less than 900 C.

Claims

1.-14. (canceled)

15. A method for preparing FZ silicon with improved minority carrier lifetime, comprising: annealing FZ silicon at an annealing temperature of 900 C., and further processing the annealed FZ silicon at processing temperatures of less than 900 C.

16. The method of claim 15, further comprising mechanically forming a plurality of FZ silicon wafers from an FZ pulled ingot, prior to annealing at 900 C.

17. The method of claim 15, comprising annealing an FZ pulled ingot at an annealing temperature of 900 C., and then mechanically forming a plurality of FZ wafers.

18. The method of claim 15, wherein the FZ silicon is annealed in an oxygen-containing ambient.

19. The method of claim 16, wherein at least one FZ wafer formed from the FZ silicon is further processed at a processing temperature of less than 900 C.

20. The method of claim 17, wherein at least one FZ wafer formed from the FZ silicon is further processed at a processing temperature of less than 900 C.

21. The method of claim 15, wherein the annealing step is performed in a rapid thermal processing chamber.

22. The method of claim 15, wherein processing the annealed FZ silicon at a processing temperature of less than 900 C. comprises a step of deposition of polycrystalline silicon on a surface of an FZ wafer.

23. The method of claim 15, wherein the FZ silicon is doped with nitrogen.

24. FZ silicon which shows no degradation of minority carrier lifetime after any processing steps at processing temperatures of less than 900 C.

25. The FZ silicon of claim 24, doped with nitrogen.

26. The FZ silicon of claim 24, comprising a wafer with a nominal diameter of 75 mm, 125 mm, 150 mm or 200 mm.

27. The FZ silicon of claim 26, wherein the wafer contains a polycrystalline silicon surface layer.

28. In the manufacture of semiconductor devices from a silicon wafer, the improvement comprising employing an FZ silicon wafer of FZ silicon of claim 26 as the silicon wafer.

29. In the manufacture of high-efficiency solar cells, from a silicon wafer, the improvement comprising employing an FZ wafer of FZ silicon of claim 26 as the silicon wafer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0043] FIG. 1 shows the lifetime of n-doped FZ 200 mm wafers as pulled, with poly backside and after different annealing steps.

[0044] FIG. 2 shown the measured DLTS defect concentrations.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0045] FZ crystals were pulled. The nitrogen level in the puller was chosen to yield a nitrogen concentration of about 10.sup.14 cm.sup.3 in the final crystal. To check the role of nitrogen, some crystals were pulled without the addition of nitrogen in the puller.

[0046] Various wafers with thicknesses 1 mm+/500 m were used. The wafer diameter does not appear to play a significant role, as the described effects could be observed with wafers from 75 mm to 200 mm diameter.

[0047] The lifetime was measured using the PCD-tool of Semilab.

[0048] Iodine-Ethanol-passivation was used to suppress surface recombination, hence to reveal true bulk lifetime properties. Moderately doped FZ wafers typically reach >3 ms lifetime with this measurement setup.

[0049] The annealing was done under an oxidative atmosphere in horizontal or vertical furnaces. The hold time was kept at 1 h, using standard ramp rates.

[0050] FIG. 1 shows the lifetime of n-doped FZ 200 mm wafers as pulled, with poly backside and after different annealing steps. As mentioned before poly deposition is done at temperatures of about 650 C. Thus, there is a degradation of minority carrier lifetime.

[0051] For wafers as pulled without any thermal treatment, the lifetime is about 3500 s. For wafers with a poly backside the lifetime drops to about 100-200 s. After annealing steps at 900 C. or above, the as pulled lifetime is more or less re-installed. If the wafers have seen a pre-anneal at 900 C. or above the poly deposition at 650 C. has no impact on the lifetime.

[0052] Thus, results can be summarized as follows: [0053] Annealing at temperatures below 900 C. degrades the as grown lifetime. It does not matter whether this takes place in oxidative or non-oxidative furnace atmosphere [0054] Annealing at a temperature of 900 C. or higher does not degrade the lifetime [0055] Annealing at a temperature of 900 C. or higher can re-install the originally high lifetime of samples that had been degraded by prior annealing at temperatures of below 900 C. [0056] Samples that have seen this high temperature annealing step (temperature of 900 C. or higher) remain widely immune against subsequent annealing at lower temperatures of less than 900 C. Their lifetime does not notably degrade any more

[0057] Subsequent DLTS (Deep-level transient spectroscopy) measurements on these samples revealed characteristic defect levels.

[0058] FIG. 2 shows the measured DLTS defect concentrations.

[0059] The results can be summarized as follows: [0060] annealing below 900 C. generates levels at 205 K and 127K [0061] annealing at 900 C. or above erases these defect levels

[0062] Since the appearance and removal of these defect levels during annealing correlates well with the lifetime behavior, the defect levels are thought to be the root cause for the lifetime impact. While not wishing to be bound by theory, vacancies and nitrogen might play a role in these defect levels.

[0063] The above description of the preferred embodiments has been given by way of example. From the disclosure given, those skilled in the art will not only understand the present invention and its attendant advantages, but will also find apparent various changes and modifications to the structures and methods disclosed. The applicant seeks, therefore, to cover all such changes and modifications as fall within the spirit and scope of the invention, as defined by the appended claims, and equivalents thereof.