Abstract
An improved structure for reducing compound semiconductor wafer distortion comprises a contact metal layer formed on a bottom surface of a compound semiconductor wafer, at least one stress balance layer formed on a bottom surface of the contact metal layer and made of nonconductive material, stress balance layer via holes and a die attachment layer. Each stress balance layer via hole penetrates the stress balance layer. The die attachment layer is made of conductive material, formed on a bottom surface of the stress balance layer and an inner surface of each stress balance layer via hole, and electrically connected with the contact metal layer through the stress balance layer via holes. By locating the stress balance layer between the contact metal layer and the die attachment layer, the stress suffered by the compound semiconductor wafer is balanced so that the distortion of the compound semiconductor wafer is reduced.
Claims
1. An improved structure for reducing compound semiconductor wafer distortion, comprising: a contact metal layer formed on a bottom surface of a compound semiconductor wafer; at least one stress balance layer formed on a bottom surface of said contact metal layer, wherein said at least one stress balance layer is made of nonconductive material; a plurality of stress balance layer via holes, wherein each of said plurality of stress balance layer via holes penetrates said at least one stress balance layer; and a die attachment layer formed on a bottom surface of said at least one stress balance layer and an inner surface of each of said plurality of stress balance layer via holes, wherein said die attachment layer is made of conductive material, said die attachment layer and said contact metal layer are electrically connected through said plurality of stress balance layer via holes; wherein the stress suffered by said compound semiconductor wafer is balanced by locating said at least one stress balance layer between said contact metal layer and said die attachment layer, so that the distortion of said compound semiconductor wafer is reduced.
2. The improved structure for reducing compound semiconductor wafer distortion according to claim 1, wherein an ohmic contact is formed between said contact metal layer and said bottom surface of said compound semiconductor wafer so that said contact metal layer forms an ohmic electrode.
3. The improved structure for reducing compound semiconductor wafer distortion according to claim 2, wherein said ohmic electrode is used for at least one diode, wherein said at least one diode is at least one selected from the group consisting of a PN diode, a Schottky diode, a light-emitting diode, a laser diode, a vertical-cavity surface-emitting laser diode, a photodiode, a varicap diode, a current regulative diode, and a Zener diode.
4. The improved structure for reducing compound semiconductor wafer distortion according to claim 3, wherein each of said at least one diode comprises at least one of said plurality of stress balance layer via holes.
5. The improved structure for reducing compound semiconductor wafer distortion according to claim 4, wherein each of said plurality of stress balance layer via holes is filled up with said die attachment layer.
6. The improved structure for reducing compound semiconductor wafer distortion according to claim 3, wherein each of said plurality of stress balance layer via holes is filled up by said die attachment layer.
7. The improved structure for reducing compound semiconductor wafer distortion according to claim 2, wherein each of said plurality of stress balance layer via holes is filled up by said die attachment layer.
8. The improved structure for reducing compound semiconductor wafer distortion according to claim 1, wherein each of said plurality of stress balance layer via holes is filled up by said die attachment layer.
9. The improved structure for reducing compound semiconductor wafer distortion according to claim 1, wherein said compound semiconductor wafer has a thickness greater than or equal to 25 m and less than or equal to 350 m.
10. The improved structure for reducing compound semiconductor wafer distortion according to claim 1, wherein said compound semiconductor wafer has a diameter greater than or equal to 3 inches.
11. The improved structure for reducing compound semiconductor wafer distortion according to claim 1, wherein said compound semiconductor wafer is made by one material selected from the group consisting of: GaAs, sapphire, InP, GaP, SiC, GaN, AlN, ZnSe, InAs, and GaSb.
12. The improved structure for reducing compound semiconductor wafer distortion according to claim 1, wherein said contact metal layer is made by at least one material selected from the group consisting of Pd, Ge, Ni, Ti, Pt, Au, and Ag.
13. The improved structure for reducing compound semiconductor wafer distortion according to claim 1, wherein each of said at least one stress balance layer is made by at least one material selected from the group consisting of: dielectric material, glass, and polymer.
14. The improved structure for reducing compound semiconductor wafer distortion according to claim 13, wherein each of said at least one stress balance layer is made by at least one material selected from the group consisting of: SiN, SiC, and SiO.sub.2.
15. The improved structure for reducing compound semiconductor water distortion according to claim 13, wherein said at least one stress balance layer is formed on said bottom surface of said contact metal layer by chemical vapor deposition or coating.
16. The improved structure for reducing compound semiconductor wafer distortion according to claim 1, wherein said die attachment layer is made by at least one material selected from the group consisting of: Au or Au alloy, Ag or Ag alloy, Sn or Sn alloy, and silver conductive epoxy adhesive.
17. The improved structure for reducing compound semiconductor wafer distortion according to claim 1, wherein said at least one stress balance layer has a thickness greater than or equal to 50 nm and less than or equal to 5 m.
Description
BRIEF DESCRIPTION OF DRAWINGS
[0023] FIG. 1A is a sectional schematic view of an embodiment of an improved structure for reducing compound semiconductor wafer distortion of the present invention.
[0024] FIG. 1B is a sectional schematic view of another embodiment of an improved structure for reducing compound semiconductor wafer distortion of the present invention.
[0025] FIG. 2A is a sectional schematic view of an application of an improved structure for reducing compound semiconductor wafer distortion of the present invention to vertical-cavity surface-emitting laser diodes.
[0026] FIG. 2B is a sectional schematic view of an application of an improved structure for reducing compound semiconductor wafer distortion of the present invention to a vertical-cavity surface-emitting laser diode.
[0027] FIG. 3 is a sectional schematic view of an improved structure for silicon semiconductor wafer of conventional technology.
DETAILED DESCRIPTIONS OF PREFERRED EMBODIMENTS
[0028] Please refer to FIG. 1A, which is a sectional schematic view of an embodiment of an improved structure for reducing compound semiconductor wafer distortion of the present invention. The improved structure 1 for reducing compound semiconductor wafer distortion of the present invention comprises a contact metal layer 30, at least one stress balance layer 40, a plurality of stress balance layer via holes 72 and a die attachment layer 50. The contact metal layer 30 is formed on a bottom surface 202 of a compound semiconductor wafer 20, wherein the compound semiconductor wafer 20 has a top surface 201 and the bottom surface 202. The material of the compound semiconductor wafer 20 may be one selected from the group consisting of: GaAs, sapphire, InP, GaP, SiC, GaN, AlN, ZnSe, InAs, and GaSb. The compound semiconductor wafer 20 has a thickness greater than or equal to 25 m and less than or equal to 350 m. In some preferable embodiments, the compound semiconductor wafer 20 has a diameter greater than or equal to 3 inches. Since the larger diameter of the compound semiconductor wafer 20 will cause the distortion of the compound semiconductor wafer 20 more seriously. Therefore, the effect of reducing the distortion of the compound semiconductor wafer 20 is more significant when applying the improved structure 1 for reducing compound semiconductor wafer distortion of the present invention to the compound semiconductor wafer 20 which has a diameter greater than or equal to 3 inches. The material of the contact metal layer 30 is at least one selected from the group consisting of: Pd, Ge, Ni, Ti, Pt, Au, and Ag. The stress balance layer 40 is formed on a bottom surface 302 of the contact metal layer 30. The stress balance layer 40 is made of nonconductive material. The stress balance layer 40 is formed on the bottom surface 302 of the contact metal layer 30 by chemical vapor deposition, coating, vacuum evaporation, ion plating or sputtering. In some preferable embodiments, the stress balance layer 40 is formed on the bottom surface 302 of the contact metal layer 30 by chemical vapor deposition or coating. The stress balance layer 40 has a thickness greater than or equal to 50 nm and less than or equal to 5 m. In some embodiments, the material of each of the at least one stress balance layer 40 is at least one selected from the group consisting of: dielectric material, glass, and polymer. In some preferable embodiments, the material of each of the at least one stress balance layer 40 is at least one selected from the group consisting of: SiN, SiC, and SiO.sub.2. Each of the plurality of stress balance layer via holes 72 penetrates the stress balance layer 40. The die attachment layer 50 is formed on a bottom surface 402 of the stress balance layer 40 and an inner surface 74 of each of the plurality of stress balance layer via holes 72. The die attachment layer 50 is made of conductive material. The die attachment layer 50 and the contact metal layer 30 are electrically connected through the plurality of stress balance layer via holes 72. The material of the die attachment layer 50 is at least one selected from the group consisting of: Au or Au alloy, Ag or Ag alloy, Sn or Sn alloy, and silver conductive epoxy adhesive. By locating the at least one stress balance layer 40 between the contact metal layer 30 and the die attachment layer 50, the stress suffered by the compound semiconductor wafer 20 is balanced so that the distortion of the compound semiconductor wafer 20 is reduced. Since the contact metal layer 30 and the die attachment layer 50 are all made of conductive materials; and the contact metal layer 30 and the die attachment layer 50 are electrically connected through the plurality of stress balance layer via holes 72; therefore the improved structure 1 for reducing compound semiconductor wafer distortion of the present invention not only can balance the stress suffered by the compound semiconductor wafer 20 to reduce the distortion of the compound semiconductor wafer 20, but the improved structure 1 also have the function of conducting to meet the requirements of some specific applications. According to the stress suffered by the compound semiconductor wafer 20, the improved structure 1 for reducing compound semiconductor wafer distortion of the present invention may choose appropriate materials and thicknesses (including the contact metal layer 30, the stress balance layer 40 and the die attachment layer 50) to balance the stress of the structure formed on the top surface 201 of the compound semiconductor wafer 20.
[0029] In some preferable embodiments, the material of the compound semiconductor wafer 20 is one selected from the group consisting of: GaAs, sapphire, InP, GaP, SiC, GaN and AlN. In some preferable embodiments, the material of the contact metal layer 30 is at least one selected from the group consisting of: Pd, Ge, Ni, Ti, Pt, Au, and Ag. In some preferable embodiments, the material of the die attachment layer 50 is Au or Au alloy.
[0030] In some preferable embodiments, the thickness of the compound semiconductor wafer 20 is greater than or equal to 25 m and less than or equal to 350 m, greater than or equal to 35 m and less than or equal to 350 m, greater than or equal to 50 m and less than or equal to 350 m, greater than or equal to 75 m and less than or equal to 350 m, greater than or equal to 100 m and less than or equal to 350 m, greater than or equal to 25 m and less than or equal to 300 m, greater than or equal to 25 m and less than or equal to 250 m, greater than or equal to 25 m and less than or equal to 200 m, greater than or equal to 25 m and less than or equal to 150 m, or greater than or equal to 25 m and less than or equal to 100 m. In some preferable embodiments, the thickness of the stress balance layer 40 is greater than or equal to 50 nm and less than or equal to 5 m, greater than or equal to 75 nm and less than or equal to 5 m, greater than or equal to 100 nm and less than or equal to 5 m, greater than or equal to 150 nm and less than or equal to 5 m, greater than or equal to 200 nm and less than or equal to 5 m, greater than or equal to 250 nm and less than or equal to 5 m, greater than or equal to 50 nm and less than or equal to 4.5 m, greater than or equal to 50 nm and less than or equal to 4 m, greater than or equal to 50 nm and less than or equal to 3.5 m, or greater than or equal to 50 nm and less than or equal to 3 m.
[0031] Please refer to FIG. 1B, which is a sectional schematic view of another embodiment of an improved structure for reducing compound semiconductor wafer distortion of the present invention. The embodiment of FIG. 1B is basically the same as the embodiment of FIG. 1A, except that the die attachment layer 50 has a plurality of die attachment layer recesses 76. When forming the die attachment layer 50, a width and a depth of the plurality of die attachment layer recesses 76 are correlated to a width and a depth of the plurality of stress balance layer via holes 72, a thickness of the balance layer 40, and a thickness of the die attachment layer 50. In some embodiments, the depth of the die attachment layer recess 76 is less than or equal to the thickness of the die attachment layer 50 so that each of the plurality of stress balance layer via holes 72 is filled up with the die attachment layer 50. In some other embodiments, the depth of the die attachment layer recess 76 is greater than the thickness of the die attachment layer 50 so that the stress balance layer via hole 72 is not filled up with the die attachment layer 50.
[0032] Please refer to FIG. 2A, which is a sectional schematic view of an application of an improved structure for reducing compound semiconductor wafer distortion of the present invention to vertical-cavity surface-emitting laser diodes, wherein the improved structure 1 for reducing compound semiconductor wafer distortion of the present invention is applied to form a plurality of vertical-cavity surface-emitting laser diodes 2. In the embodiment of FIG. 2A, the improved structure 1 for reducing compound semiconductor wafer distortion of the present invention comprises a contact metal layer 30, at least one stress balance layer 40, a plurality of stress balance layer via holes 72 and a die attachment layer 50. The contact metal layer 30 is formed on a bottom surface 202 of a compound semiconductor wafer 20. The stress balance layer 40 is formed on a bottom surface 302 of the contact metal layer 30. Each of the plurality of stress balance layer via holes 72 penetrates the stress balance layer 40. The die attachment layer 50 is formed on a bottom surface 402 of the stress balance layer 40 and an inner surface 74 of each of the plurality of stress balance layer via holes 72. The die attachment layer 50 and the contact metal layer 30 are electrically connected through the plurality of stress balance layer via holes 72. The improved structure 1 for reducing compound semiconductor water distortion of embodiment of FIG. 2A is basically the same as the improved structure 1 of the embodiment of FIG. 1A, except that an ohmic contact is formed between the contact metal layer 30 and the bottom surface 202 of the compound semiconductor wafer 20 so that the contact metal layer 30 forms an ohmic electrode. In current embodiment, the ohmic electrode is an n-type ohmic electrode. In the embodiment of FIG. 2A, it further comprises: an n-type distributed Bragg reflector 60, a quantum well structure 62, an oxidation confinement layer 64, a p-type distributed Bragg reflector 66, a p-type ohmic electrode 68, a plurality of mesa structures 67 and a plurality recesses 69. The n-type distributed Bragg reflector 60 is formed on a top surface 201 of the compound semiconductor wafer 20. The quantum well structure 62 is formed on the n-type distributed Bragg reflector 60. The oxidation confinement layer 64 is formed on the quantum well structure 62. The p-type distributed Bragg reflector 66 is formed on the oxidation confinement layer 64. The p-type ohmic electrode 68 is formed on the p-type distributed Bragg reflector 66. The plurality of recesses 69 is formed by etching the p-type ohmic electrode 68, the p-type distributed Bragg reflector 66 and the oxidation confinement layer 64 within the area of the plurality of recesses 69. Thereby the plurality of mesa structures 67 is formed. Each mesa structure 67 includes the p-type ohmic electrode 68, the p-type distributed Bragg reflector 66 and the oxidation confinement layer 64. Please also refer to FIG. 2B, which is a sectional schematic view of an application of an improved structure for reducing compound semiconductor wafer distortion of the present invention to a vertical-cavity surface-emitting laser diode. By cutting the structure of FIG. 2A along the dashed lines 70, a plurality of vertical-cavity surface-emitting laser diodes 2 as shown in FIG. 2B is produced. Each vertical-cavity surface-emitting laser diode 2 comprises the die attachment layer 50, the stress balance layer 40, at least one stress balance layer via hole 72, the contact metal layer 30 (n-type ohmic electrode), the compound semiconductor wafer 20, the n-type distributed Bragg reflector 60, the quantum well structure 62, the oxidation confinement layer 64, the p-type distributed Bragg reflector 66, the p-type ohmic electrode 68 and one mesa structure 67.
[0033] In some embodiments, the improved structure 1 for reducing compound semiconductor wafer distortion of the present invention (an ohmic contact is formed between the contact metal layer 30 and the bottom surface 202 of the compound semiconductor wafer 20 so that the contact metal layer 30 forms an ohmic electrode), the ohmic electrode formed by the contact metal layer 30 may be applied to the vertical-cavity surface-emitting laser diode 2 as shown in FIG. 2A and besides may also be applied to at least one selected from the group consisting of: a PN diode, a Schottky diode, a light-emitting diode, a laser diode, a photodiode, a varicap diode, a current regulative diode, and a Zener diode.
[0034] As disclosed in the above description and attached drawings, the present invention can provide an improved structure for reducing compound semiconductor wafer distortion. It is new and can be put into industrial use.
[0035] Although the embodiments of the present invention have been described in detail, many modifications and variations may be made by those skilled in the art from the teachings disclosed hereinabove. Therefore, it should be understood that any modification and variation equivalent to the spirit of the present invention be regarded to fall into the scope defined by the appended claims.
