Abstract
An erasing method of a single-gate non-volatile memory is provided. The single-gate non-volatile memory has a single floating gate. The erasing method includes applying a voltage to the drain without applying to the gate to create and control an inversion layer. Therefore the required erasing voltage is reduced and the erasing speed is improved to avoid the over-erase problem.
Claims
1. An erasing method of a single-gate non-volatile memory, wherein said single-gate non-volatile memory comprises a P-type semiconductor substrate, a transistor and a capacitor structure, wherein said transistor and said capacitor structure disposed in said semiconductor substrate, and wherein said transistor includes a first electrically-conductive gate and multiple first ion-doped regions that are separately disposed at both sides of said first electrically-conductive gate and respectively function as the source and the drain, and wherein said capacitor structure includes a second electrically-conductive gate and a second ion-doped region, wherein said first electrically-conductive gate and said second electrically-conductive gate electrically interconnected to form a single floating gate, and wherein said erasing method is characterized in: respectively applying a substrate voltage V.sub.sub, a source voltage V.sub.s and a drain voltage V.sub.d to said P-type semiconductor substrate, said source and said drain, and not applying a voltage to said first ion-doped regions, wherein said voltages meet the following conditions: V.sub.d>V.sub.sV.sub.sub, and V.sub.sub is grounded.
2. The erasing method of a single-gate non-volatile memory according to claim 1, wherein said first ion-doped regions and said second ion-doped region are N-type ion-doped regions, and said capacitor structure is N-type capacitor or N-well capacitor.
3. The erasing method of a single-gate non-volatile memory according to claim 1, wherein said transistor structure is a metal-oxide-semiconductor field-effect transistor (MOSFET).
Description
BRIEF DESCRIPTION OF THE DRAWINGS
(1) FIG. 1A is a sectional view schematically showing the structure of the single-gate non-volatile memory according to a first embodiment of the present invention.
(2) FIG. 1B is a sectional view schematically showing the structure of the single-gate non-volatile memory according to a second embodiment of the present invention
(3) FIG. 2A is a diagram schematically showing the four-terminal structure of the first embodiment.
(4) FIG. 2B is a diagram schematically showing the four-terminal structure of the second embodiment.
(5) FIG. 2C is a diagram schematically showing an equivalent circuit of the structure shown in FIG. 2A and FIG. 2B.
DETAILED DESCRIPTION OF THE INVENTION
(6) Refer to FIG. 1A a sectional view schematically showing the structure of the single-gate non-volatile memory according to a first embodiment of the present invention. The single-gate non-volatile memory structure 30 comprises an NMOS transistor (NMOSFET) 32 and an N-well capacitor structure 34 with both of them embedded in a P-type semiconductor substrate 36, such as a silicon substrate. The NMOS transistor 32 includes a first dielectric layer 320 disposed on the surface of the P-type semiconductor substrate 36; a first electrically-conductive gate 322 stacked on the first dielectric layer 320; and two high-conductivity first ion-doped regions disposed inside the P-type semiconductor substrate 36, and respectively functioning as the source 324 and the drain 324 with a channel 326 formed between the source 324 and the drain 324. The N-well capacitor structure 34 includes a second ion-doped region disposed in the P-type semiconductor substrate 36 and functioning as an N-type well 340; a second dielectric layer 342 disposed on the surface of the N-type well 340; and a second electrically-conductive gate 344 stacked on the second dielectric layer 342; those abovementioned elements form a top layer-dielectric layer-bottom layer capacitor structure. The first electrically-conductive gate 322 of the NMOS transistor 32 and the second electrically-conductive gate 344 on the top of the N-well capacitor structure 34 are separated with an isolation material 38 and electrically interconnected to form a single floating gate 40.
(7) Refer to FIG. 2A. The single-gate non-volatile memory structure 30 has four terminals, including the connecting structures of the substrate, the source, the drain, and the control gate; a substrate voltage V.sub.sub, a source voltage V.sub.s, a drain voltage V.sub.d, a control gate voltage V.sub.c are respectively applied to the substrate, the source, the drain, and the first ion-doped region. Refer to FIG. 2C for the equivalent circuit thereof. The conditions of the erasing operation process of the single-gate non-volatile memory structure 30 are:
(8) a. V.sub.sub is grounded (=0), and
(9) b. V.sub.sz V.sub.sub=0, and V.sub.s<V.sub.d.
(10) Therefore, V.sub.d>V.sub.sV.sub.sub=0, and V.sub.c is not applied.
(11) Refer to FIG. 1B a sectional view schematically showing the structure of the single-gate non-volatile memory according to a second embodiment of the present invention. The single-gate non-volatile memory structure 50 comprises a NMOS transistor 52 and an N-type capacitor structure 54 with both of them embedded in a P-type semiconductor substrate 56, such as a silicon substrate. The NMOS transistor 52 includes a first dielectric layer 520 disposed on the surface of the P-type semiconductor substrate 56; a first electrically-conductive gate 522 stacked on the first dielectric layer 520; and two high-conductivity first ion-doped regions disposed inside the P-type semiconductor substrate 56, and respectively functioning as the source 524 and the drain 524 with a channel 526 formed between the source 524 and the drain 524. The N-type capacitor structure 54 includes a second ion-doped region disposed in the P-type semiconductor substrate 56; a second dielectric layer 542 disposed on the surface of the P-type semiconductor substrate 56; and a second electrically-conductive gate 544 stacked on the second dielectric layer 542; those abovementioned elements form a top layer-dielectric layer-bottom layer capacitor structure. The first electrically-conductive gate 522 of the NMOS transistor 52 and the second electrically-conductive gate 544 on the top of the N-type capacitor structure 54 are separated with an isolation material 58 and electrically interconnected to form a single floating gate 60.
(12) Refer to FIG. 2B. The single-gate non-volatile memory structure 50 has four terminals, including the connecting structures of the substrate, the source, the drain, and the control gate; a substrate voltage V.sub.sub, a source voltage V.sub.s, a drain voltage V.sub.d, a control gate voltage V.sub.c are respectively applied to the substrate, the source, the drain, and the first ion-doped region. Refer to FIG. 2C for the equivalent circuit thereof. The conditions of the erasing operation process of the single-gate non-volatile memory structure 50 are:
(13) a. V.sub.sub is grounded (=0), and
(14) b. V.sub.sV.sub.sub=0, and V.sub.s<V.sub.d.
(15) Therefore, V.sub.d>V.sub.sV.sub.sub=0, and V.sub.c is not applied.
(16) The single-gate non-volatile memory structure 30 shown in FIG. 1A is formed on a P-type silicon wafer. The isolation structure 38 is fabricated with a standard isolation module process. After the formation of the isolation structure 38, the channel 326 of the NMOS transistor 32 and the N-type well 340 are fabricated with ion-implant processes. After the dielectric layers of the first electrically-conductive gate 322 and the second electrically-conductive gate 344 have been grown, a polysilicon layer is formed via a deposition process. The polysilicon layer is patterned with a lithographic process and an etching process to form the single floating gate 40. Next, ion-implant processes are undertaken to form the source 324, the drain 324 of the NMOS transistor 32 and the control gate. Lastly, a metallization process is undertaken, and then, the fabrication of the single-gate non-volatile memory structure 30 is completed.
(17) The fabrication process of single-gate non-volatile memory structure 50 shown in FIG. 1B is essentially similar to that described above. The single-gate non-volatile memory structure 50 is formed on a P-type silicon wafer. The isolation structure 58 is fabricated with a standard isolation module process. After the formation of the isolation structure 58, the channel 526 of the NMOS transistor 52 and the N-type capacitor structure 54 are fabricated with ion-implant processes. After the dielectric layers of the first electrically-conductive gate 522 and the second electrically-conductive gate 544 have been grown, a polysilicon layer is formed via a deposition process. The polysilicon layer is patterned with a lithographic process and an etching process to form the single floating gate 60. Next, ion-implant processes are undertaken to form the source 524, the drain 524 of the NMOS transistor 52 and the control gate. Lastly, a metallization process is undertaken, and then, the fabrication of the single-gate non-volatile memory structure 50 is completed.
(18) In the present invention, the abovementioned processes usually refer to general CMOS processes.
(19) In conclusion, the present invention provides an erasing method of the single-gate non-volatile memory. During erasing the memory, the voltage is applied to the drain of the single-gate non-volatile memory structure without applying to the gate for generating and controlling an anti-layer by the drain voltage, so that the required erasing voltage is reduced and the erasing speed is improved. When the erasing is completed, the drain voltage drops due to the channel opening or the source voltage rises to cause the erasing operation to stop, thereby reducing the erasing voltage and solving the over-erase problem.
(20) Those embodiments described above are to clarify the present invention to enable the persons skilled in the art to understand, make and use the present invention; however, it is not intended to limit the scope of the present invention, and any equivalent modification and variation according to the spirit of the present is to be also included within the scope of the claims stated below.
