SEMICONDUCTOR STRUCTURE HAVING BUMP ON TILTING UPPER CORNER SURFACE

Abstract

A semiconductor structure is provided. The semiconductor structure includes a semiconductor substrate and a first conductive bump. The semiconductor substrate has an integrated circuit and an interconnection metal layer, and a tilt surface is formed on an edge of the semiconductor substrate. The first conductive bump is electrically connected to the integrated circuit via the interconnection metal layer, and is disposed on the tilt surface, wherein a profile of the first conductive bump extends beyond a side surface of the edge of the semiconductor layer.

Claims

1. A semiconductor structure, comprising: a semiconductor substrate having an integrated circuit and an interconnection metal layer, wherein a tilt surface is formed on an edge of the semiconductor substrate; a first conductive bump electrically connected to the integrated circuit via the interconnection metal layer, and in direct contact with the tilt surface, wherein a profile of the first conductive bump extends beyond a side surface of the edge of the semiconductor substrate; a plurality of second conductive bumps in direct contact with an upper surface of the semiconductor substrate, each of the second conductive bumps has a cross-sectional area greater than a cross-sectional area of the first conductive bump; and a printed circuit board having a plurality of solder pads which are in contact with and electrically connected to the second conductive bumps, without contacting the first conductive bump, wherein both the tilt surface and the upper surface of the semiconductor substrate face toward the printed circuit board.

2. The semiconductor structure of claim 1, wherein the semiconductor substrate further comprising: a substrate; a passivation layer disposed on the substrate; a first conductor layer disposed on the passivation layer; and a second conductor layer disposed on the passivation layer and the first conductor layer, wherein the second conductor layer is electrically connected to the first conductor layer.

3. The semiconductor structure of claim 2, wherein the substrate has an inclined plane, a portion of the first conductor layer has a first portion and a second portion, the first portion is disposed on the inclined plane of the substrate and the second portion is disposed on a horizontal upper surface of the substrate, and an upper surface of the first portion of the first conductor layer is the tilt surface.

4. The semiconductor structure of claim 2, wherein the passivation layer includes a redistribution layer.

5-7. (canceled)

8. A semiconductor device, comprising: two semiconductor structures laterally connected with each other, each of the two semiconductor structures comprising: a semiconductor substrate having an integrated circuit and an interconnection metal layer, wherein a tilt surface is formed on an edge of the semiconductor substrate; a first conductive bump electrically connected to the integrated circuit via the interconnection metal layer, and in direct contact with the tilt surface, wherein a profile of the first conductive bump extends beyond a side surface of the edge; a plurality of second conductive bumps in direct contact with an upper surface of the semiconductor substrate, each of the second conductive bumps has a cross-sectional area greater than a cross-sectional area of the first conductive bump; and a printed circuit board having a plurality of solder pads which are in contact with and electrically connected to the second conductive bumps, without contacting the first conductive bump, both the tilt surface and the upper surface of the semiconductor substrate face toward the printed circuit board, wherein the two semiconductor structures are laterally connected by their respective first conductive bumps that are jointed.

9. The semiconductor device of claim 8, wherein the semiconductor substrate further comprising: a substrate; a passivation layer disposed on the substrate; a first conductor layer disposed on the passivation layer; a second conductor layer disposed on the passivation layer and the first conductor layer, wherein the second conductor layer is electrically connected to the first conductor layer.

10. The semiconductor device of claim 9, wherein the substrate has an inclined plane, a portion of the first conductor layer has a first portion and a second portion, the first portion is disposed on the inclined plane of the substrate and the second portion is disposed on a horizontal upper surface of the substrate, and an upper surface of the first portion of the first conductor layer is the tilt surface.

11. The semiconductor device of claim 9, wherein the passivation layer includes a redistribution layer.

12-20. (canceled)

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The disclosure can be more fully understood by reading the following detailed description of the embodiment, with reference made to the accompanying drawings as follows:

[0023] FIG. 1 is a schematic cross-sectional view of a semiconductor structure according to one embodiment of this disclosure;

[0024] FIGS. 2A-2F are cross-sectional views of various fabrication steps of a method of forming a semiconductor structure according to one embodiment of this disclosure;

[0025] FIG. 3 is a schematic cross-sectional view of a semiconductor device according to one embodiment of this disclosure;

[0026] FIG. 4 is a schematic cross-sectional view of a semiconductor device according to another embodiment of this disclosure;

[0027] FIGS. 5A-5B are flow charts illustrating various fabrication steps of a method of forming a semiconductor device according to one embodiment of this disclosure.

DETAILED DESCRIPTION

[0028] In the following detailed description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the disclosed embodiments. It will be apparent, however, that one or more embodiments may be practiced without these specific details. In other instances, well-known structures and devices are schematically depicted in order to simplify the drawings.

[0029] Referring to FIG. 1, FIG. 1 is a schematic cross-sectional view of a semiconductor structure 100 according to one embodiment of this disclosure. A semiconductor structure 100 includes a semiconductor substrate 110, a first conductive bump 120, and second conductive bumps 130. In the present embodiment, the first conductive bump 120 and the second conductive bumps 130 are formed from solder, tin-lead or other suitable materials, but the present disclosure is not be limited thereto. For example, in various embodiments, the first conductive bump 120 and the second conductive bumps 130 may include a solder bump or paste that may be mounted or printed onto a top surface SU of the semiconductor substrate 110.

[0030] As shown in FIG. 1, the semiconductor substrate 110 has an integrated circuit 111 and an interconnection metal layer 113, and further includes a substrate 112, a passivation layer 114, a first conductor layer 116 and a second conductor layer 118. The passivation layer 114 is disposed on the substrate 112. The first conductor layer 116 is disposed on the passivation layer 114. The second conductor layer 118 is disposed on the passivation layer 114 and the first conductor layer 116, in which the second conductor layer 118 is electrically connected to the first conductor layer 116.

[0031] Moreover, as shown in FIG. 1, a tilt surface 115 is formed on an edge 117 of the semiconductor substrate 110. The first conductive bump 120 is electrically connected to the integrated circuit 111 via the interconnection metal layer 113, and is disposed on the tilt surface 115, in which a profile of the first conductive bump 120 extends beyond a side surface SE of the edge 117. The second conductive bumps 130 are disposed on an upper surface SU of the semiconductor substrate 110, and are electrically connected to the second conductor layer 118.

[0032] The process of forming the semiconductor structure 100 will be further explained below with reference to FIG. 2A to FIG. 2F.

[0033] FIGS. 2A-2F are cross-sectional views of various fabrication steps of a method forming a semiconductor structure 100 according to one embodiment of this disclosure. Referring to FIG. 2A, a substrate 112 is provided, and a passivation layer 114 is formed on the substrate 112. In the present embodiment, the semiconductor substrate 110 has an integrated circuit 111 and an interconnection metal layer 113. For example, as shown in FIG. 2A, the passivation layer 114 further includes a redistribution layer RDL which may be connected to the integrated circuit 111 inside the semiconductor substrate 110.

[0034] Referring to FIG. 2B, a metal layer 116 is formed on the passivation layer 114, and an inclined plane IP is formed on an edge 117 of the substrate 112. For example, the method of forming the inclined plane IP includes drilling the substrate 112 by using a laser at an inclined angle in the present embodiment. Then, the substrate 112 is cut to keep the part of the inclined plane IP on the edge 117. In this way, the inclined plane IP on the edge 117 of the substrate 112 is formed.

[0035] Referring to FIG. 2C, the metal layer 116 is patterned to form a first conductor layer 116 on the passivation layer 114. As shown in FIG. 2C, in the present embodiment, an upper surface of a portion of the first conductor layer 116 on the edge 117 of the substrate 112 is the tilt surface 115. In more detail, in the present embodiment, a portion of the first conductor layer 116 has a first portion 116a and a second portion 116b. The first portion 116a is disposed on the inclined plane IP of the substrate 112, and the second portion 116b is disposed on a horizontal upper surface SU of the substrate 112. The upper surface of the first portion 116a of the first conductor layer 116 is the tilt surface 115.

[0036] Referring to FIG. 2D, a second conductor layer 118 is formed on the passivation layer 114 and the first conductor layer 116. As shown in FIG. 2D, in the present embodiment, the second conductor layer 118 is electrically connected to the first conductor layer 116. More specifically, in the present embodiment, portions of the first conductor layer 116 may be connected through the second conductor layer 118. However, the present disclosure is not limited thereto. Alternatively, portions of the first conductor layer 116 may be not connected, and are separated spatially in another embodiment.

[0037] Referring to FIG. 2E, conductive materials 120 and 130 may be formed on the first conductor layer 116 and the second conductor layer 118. In the present embodiment, the conductive materials 120 and 130 may be printed or deposited on the first conductor layer 116 and the second conductor layer 118 using a print mask (not shown) to align the conductive materials 120 and 130 to the first conductor layer 116 and the second conductor layer 118.

[0038] Referring to FIGS. 2E and 2F, a reflow process may be performed to reflow the conductive materials 120 and 130 of FIG. 2E to form the first conductive bump 120 and the second conductive bumps 130 for the semiconductor structure 100. As a result, the first conductive bump 120 is formed on the tilt surface 115, and a profile of the first conductive bump 120 extends beyond a side surface SE of the edge 117, as shown in FIG. 2F. Besides, the first conductive bump 120 is electrically connected to the integrated circuit 111 via the interconnection metal layer 113. Moreover, as shown in FIG. 2F, the second conductive bumps 130 is also formed on a horizontal upper surface SU of the semiconductor substrate 110 at the same time, in which the second conductive bumps 130 are electrically connected to the second conductor layer 118.

[0039] In more detail, as shown in FIG. 2F, a maximum vertical height H of each of the second conductive bumps 130 is greater than a maximum vertical height h of the first conductive bump 120. For example, in the present embodiment, a diameter D of each of the second conductive bumps 130 is greater than a diameter d of the first conductive bump 120, such that the maximum vertical height H of each of the second conductive bumps 130 is greater than a maximum vertical height h of the first conductive bump 120. However, the present disclosure is not limited thereto. For example, in various embodiments, the diameter D of each of the second conductive bumps 130 may be equal to or greater than the diameter d of the first conductive bump 120, thus also resulting in the maximum vertical height H of each of the second conductive bumps 130 being greater than a maximum vertical height h of the first conductive bump 120 since the first conductive bump 120 is on the tilt surface 115.

[0040] As a result, the semiconductor structure 100 is formed. Furthermore, in the present embodiment, by using the configuration of the first conductive bump 120 on the tilt surface 115, the semiconductor structure 100 is capable of connecting the semiconductor element to another object side by side. Hereinafter, further explanations are provided in the below with reference to FIG. 3.

[0041] Referring to FIG. 3, FIG. 3 is a schematic cross-sectional view of a semiconductor device 300 according to one embodiment of this disclosure. The semiconductor device 300 includes two aforementioned semiconductor structures 100, and the tilt surfaces 115 of the two semiconductor substrates 100 face toward each other. By using this configuration, the first conductive bumps 120 on the tilt surfaces 115 of the two semiconductor substrates 110 may be jointed so as to connect the two semiconductor structures 100 laterally. In this way, the two semiconductor structures 100 are laterally connected by their respective first conductive bumps 120 that are jointed, and therefore, no redistribution layer build-up is needed to connect the semiconductor element to another object laterally. That is, in the present embodiment, the semiconductor device 300 is capable of laterally communicating with conductive bumps, thus achieving cost-saving.

[0042] Referring to FIG. 4, FIG. 4 is a schematic cross-sectional view of a semiconductor device 400 according to another embodiment of this disclosure. The semiconductor device 400 is similar to the semiconductor device 300, but the semiconductor device 400 further includes a printed circuit board 440. In more detail, the printed circuit board 440 has solder pads 441. The solder pads 441 are electrically connected to the second conductive bumps 130, and the solder pads 441 are in contact with the second conductive bumps 130. Since the maximum vertical height H of each of the second conductive bumps 130 is greater than a maximum vertical height h of the first conductive bump 120, the solder pads 441 do not contact the first conductive bump 120.

[0043] In this way, the two semiconductor structures 100 are laterally connected by their respective first conductive bumps 120 that are jointed, and therefore, no redistribution layer is needed to be built-up in the printed circuit board 440 to connect the semiconductor element to another object laterally. That is, in the present embodiment, the semiconductor device 400 is capable of laterally communicating with conductive bumps for cost-saving.

[0044] FIGS. 5A-5B are flow charts illustrating various fabrication steps of a method of forming a semiconductor device, according to one embodiment of this disclosure. Referring to FIG. 5A, in the method of forming a semiconductor device, step 510 is performed for forming a tilt surface on an edge of at least one semiconductor substrate having an integrated circuit and an interconnection metal layer. More specifically, referring to FIG. 5B, step 510 of forming the tilt surface on the edge includes steps 511, 512, 513, 514, 515 and 516 as follows.

[0045] As shown in FIG. 5B, in the present embodiment, in step 510, step 511 is performed for providing a substrate. Then, step 512 is performed for forming a passivation layer on the substrate. Thereafter, step 513 is performed forming an inclined plane on an edge of the substrate. Then, step 514 is performed for forming a metal layer on the passivation layer. Thereafter, step 510 515 is performed for forming a second conductor layer on the passivation layer and the first conductor layer. Then, step 516 is performed for patterning the metal layer to form a first conductor layer on the passivation layer

[0046] Referring to FIG. 5A again, the method of forming a semiconductor device further includes step 520 of forming a first conductive bump on the tilt surface and forming second conductive bumps on a horizontal upper surface of the semiconductor substrate. Then, step 530 is performed for jointing the first conductive bumps on the tilt surfaces of the two semiconductor substrates so as to connect the two semiconductor structures laterally. Alternatively, the method of forming a semiconductor device may further includes step 540 of providing a printed circuit board with solder pads, and electrically connecting the solder pads to the second conductive bumps.

[0047] As mentioned above, by using the configuration of the first conductive bump on the tilt surface, the semiconductor structure is capable of connecting the semiconductor element to another object side by side. For example, when a semiconductor device includes two aforementioned semiconductor structures, and the tilt surfaces of the two semiconductor substrates face toward each other, and the first conductive bumps on the tilt surfaces of the two semiconductor substrates may be jointed so as to connect the two semiconductor structures laterally. In this way, the two semiconductor structures are laterally connected by their respective first conductive bumps being jointed, and therefore, there is no need of redistribution layer build-up to connect the semiconductor element to another object laterally. Therefore, the semiconductor device is capable of laterally communicating with conductive bumps, thus achieving cost-saving.

[0048] All the features disclosed in this specification (including any accompanying claims, abstract, and drawings) may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise. Thus, unless expressly stated otherwise, each feature disclosed is one example only of a generic series of equivalent or similar features.

[0049] Any element in a claim that does not explicitly state means for performing a specified function, or step for performing a specific function, is not to be interpreted as a means or step clause as specified in 35 U.S.C. 112, 6th paragraph. In particular, the use of step of in the claims herein is not intended to invoke the provisions of 35 U.S.C. 112, 6th paragraph.