Radio modulation technique using DMPSK for immproved BER

Abstract

A millimeter wave radio link in which the transceivers have most of its components fabricated on a single chip or chipset of a small number of semiconductor chips. The chip or chipsets when mass produced is expected to make the price of millimeter wave radios comparable to many of the lower-priced microwave radios available today from low-cost foreign suppliers. Preferred embodiments of the present invention operate in the range of about 3.5 Gbps to more than 10 Gbps. The transceivers of a preferred embodiment are designed to receive binary input data at an input data rate in 10.3125 Gbps and to transmit at a transmit data rate in of 10.3125 Gbps utilizing encoded three-bit data symbols on a millimeter carrier wave at E-Band frequencies. Preferred embodiments include an averaging technique that greatly improves bit error rates. A constellation averaging technique is utilized to improve bit error rates.

Claims

1. A two-transceiver E-Band radio link, defining a first transceiver and a second transceiver, with 8PSK modulation and demodulation, capable of 10.3125 Gbps operation, said link comprising: A. a first transceiver adapted to transmit at a first E-Band frequency band and to receive at a second E-Band frequency band, each of the two bandwidths, defining a first and second E-Band bandwidth, each being at least as wide as 3.5 GHz, said transceiver comprising: 1) transmitter front-end circuitry adapted to receive a binary input data stream with a capability of producing output signals at data rates at least as fast as 10.3125 Gbps utilizing 8PSK modulation of an E-Band carrier signal, said transmitter front-end circuitry comprising: a. encoding circuitry adapted to encode input binary signals to produce encoded signals, with each encoded signal comprising three bits; and b. 8PSK modulation circuitry adapted to phase shift the millimeter wave carrier signal based on the encoded signals to produce a phase-shifted carrier signal at the first E-Band frequency band with each phase of the signal defining one of eight phases, having spacing between the phases of about 45 degrees or a multiple of about 45 degrees; 2) receiver circuitry adapted to receive incoming E-Band signals transmitted from the second transceiver at the second E-Band frequency millimeter wave transmitter, said receiver circuitry comprising: a. millimeter wave amplifier circuitry adapted to amplify incoming E-Band signals; b. demodulation circuitry adapted to demodulate the amplified incoming millimeter wave signals to produce a binary output data stream; 3) radio transmit and receive components adapted transmit and receive phase shifted E-band radio signals to and from the second transceiver, said radio components comprising: a. a millimeter wave amplifier circuit adapted to amplify phase shifted carrier signal to produce an amplified phase shifted transmit E-Band radio beam, b. a millimeter wave amplifier circuit adapted to amplify phase shifted carrier signals received from the second transceiver; 4) an antenna system adapted to convert the phase shifted E-band radio transmit beams to produce a narrow band E-Band pencil beam confined within a single narrow channel less than 1.2 degrees wide and to collect phase shifted E-band radio beams transmitted from the second transceiver; B. a second transceiver adapted to transmit at a first E-Band frequency band and to receive at a second E-Band frequency band, each of the two bandwidths, defining a first and second E-Band bandwidth, each being at least as wide as 3.5 GHz, said transceiver comprising: 1) transmitter front-end circuitry adapted to receive a binary input data stream with a capability of producing output signals at data rates at least as fast as 10.3125 Gbps utilizing D8PSK modulation of an E-Band carrier signal, said transmitter front-end circuitry comprising: a. encoding circuitry adapted to encode input binary signals to produce encoded signals, with each encoded signal comprising three bits; and b. 8PSK modulation circuitry adapted to phase shift the millimeter wave carrier signal based on the encoded signals to produce a phase-shifted carrier signal at the first E-Band frequency band with each phase of the signal defining one of eight phases, having spacing between the phases of about 45 degrees or a multiple of about 45 degrees; 2) receiver circuitry adapted to receive incoming E-Band signals transmitted from the second transceiver at the second E-Band frequency millimeter wave transmitter, said receiver circuitry comprising: a. millimeter wave amplifier circuitry adapted to amplify incoming E-Band signals; b. demodulation circuitry adapted to demodulate the amplified incoming millimeter wave signals to produce a binary output data stream; 3) radio transmit and receive components adapted transmit and receive phase shifted E-band radio signals to and from the first transceiver, said radio components comprising: a. a millimeter wave amplifier circuitry adapted to amplify phase shifted carrier signal to produce an amplified, phase-shifted transmit E-Band radio beam, b. a millimeter wave amplifier circuitry adapted to amplify phase-shifted carrier signals received from the first transceiver; 4) an antenna system adapted to convert the phase-shifted E-band radio transmit beams to produce a narrow band E-Band pencil beam confined within a single narrow channel less than 1.2 degrees wide and to collect phase-shifted E-band radio beams transmitted from the first transceiver; wherein a constellation averaging technique is utilized to improve bit error rates.

2. The radio link as in claim 1 wherein all or mostly all of the transmitter front-end circuitry and the receiver circuitry of both transceivers are fabricated on a single chip or chipset,

3. The radio link as in claim 1 wherein the 8PSK modulation circuitry is D8PSK modulation circuitry.

4. The radio link as in claim 1 wherein the transmitter front end circuitry of both transceivers are adapted to derive their internal clock references directly from 10 GbE fiber or coaxial cable data input.

5. The radio link as in claim 4 wherein the transmitter front end circuitry of both transceivers are adapted to generate symbol clock, intermediate frequencies and transmit frequencies from their internal clock references.

6. The radio link as in claim 5 wherein the receiver circuitry in both transceivers derive their receiver symbol clock from their 10 GBE antenna data input with a result that receiver internal symbol clock of each of the transceivers is slaved to the transmitter clock of the other transceiver and fully independent of internal transmit clock of the transceiver.

7. The radio link as in claim 6 wherein the receiver circuitry of each of the two transceivers utilizes an edge detector comprised of a delay and sum interference circuit, using a half wave delay of the intermediate frequency receive signal to detect and synchronize to phase jumps in order to generate an internal receiver clock.

8. The radio link as in claim 7 wherein the receiver circuitry of each of the two transceivers is adapted to generate its symbol clock, intermediate frequencies and local oscillator frequencies from its internal edge-detector derived clock eliminating a need for a Costas loop or other carrier recovery circuit.

9. The radio link as in claim 8 wherein the receiver circuitry of each of the two transceivers is adapted to decode data based on differential phase between successive symbols, eliminating a need for a common phase reference with the transmitter of the other transceiver.

10. The radio link as in claim 1 wherein the chips or chipsets are comprised of silicon germanium or gallium arsenide.

11. The radio link as in claim 7 wherein the receiver circuitry of each of the two transceivers is fabricated utilizing silicon complementary metal-oxide semiconductor (Si CMOS) technology.

12. The radio link as in claim 11 wherein a plurality of peripheral radio components are external to the chips or chipsets.

13. The radio link as in claim 12 wherein the plurality of peripheral radio components include some or all of the following components: fiber-optic transceivers, frequency generators, filters, power supplies and regulators, high-power amplifiers, diplexers and antenna systems.

14. The radio link as in claim 1 wherein front-end analog electronics, including amplifies, clock recovery, mixers, frequency multiplies and dividers, edge detectors, and phase comparators, and digital processing electronics, including digitizers, FPGA's, digital to analog converters, are fabricated on a single all-silicon CMOS semiconductor chips or chipsets.

15. The radio link as in claim 1 wherein the transceivers are adapted to operate in accordance with a protocol or standard chosen from the following group of protocols or standards: SONET OC-96 (4.976 Gbps) 4Gig-E (5.00 Gbps) 5Gig-E (6.25 Gbps) OBSAI RP3-01 (6.144 Gbps) 6Gig-E (7.50 Gbps) Fibre Channel 8GFC (8.5 Gbps) SONET OC-192 (9.952 Gbps) Fibre Channel 10GFC Serial (10.52 Gbps)

16. The radio link as in claim 1 wherein the transmitters and the receivers transmit and receive through separate antennas.

17. The radio link as in claim 1 wherein the transmitters are adapted to provide a dynamic range in power output exceeding 15 dB.

18. The radio links as in claim 1 wherein the transmitter and the receiver portions of the transceivers are contained in a single enclosure.

19. The radio links as in claim 1 wherein the transmitter and the receiver portions of the transceiver are contained in separate enclosures.

20. The radio link as in claim 1 wherein the transmitters and the receivers transmit and receive through a single antenna.

21. The radio as in claim 1 wherein the link includes a processor programmed to include a constellation averaging algorithm for reduction bit error rates.

22. The link as in claim 21 wherein the reduction in bit error rate is a five order magnitude reduction.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0041] FIG. 1 describes the transmitter of a preferred embodiment.

[0042] FIG. 2 shows how data is handled by a fast FPGA and clocked into an array processor at a slower rate.

[0043] FIG. 3 shows a symbol constellation of the preferred embodiment.

[0044] FIG. 4 demonstrates the use of a high quality temperature controlled crystal oscillator (TCXO) to suppress phase noise.

[0045] FIG. 5 shows the use of digital to analog device to drive X and Y magnitudes for the symbol constellation.

[0046] FIG. 6 shows a clock and data recovery circuit.

[0047] FIG. 7 shows features of a receiver for detecting and demodulating the transmit signal.

[0048] FIG. 8 shows how the transmitter provides the clock for both the transmitter and the receiver.

[0049] FIG. 9 shows how the clock signal is used to control the ultra-stable TCXO.

[0050] FIG. 10 shows how the signal from the transmitter is filtered and how phase is compared to the previous phase to determine the size of the phase jump.

[0051] FIG. 11 is a symbol constellation of a radio using 8PSK modulation

[0052] FIG. 12 shows constellation for an 8PSK radio with an imperfect carrier in the receiver.

[0053] FIG. 13 demonstrates a phase change (including noise) from one symbol to the next.

[0054] FIG. 14 is a plot of complementary error function.

[0055] FIG. 15 demonstrates error reduction with averaging.

[0056] FIG. 16 demonstrates effects of averaging on angular blurring.

[0057] FIG. 17 demoushates a truncation of a binary representation.

[0058] FIG. 18 shows a 16 QAM constellation.

[0059] FIG. 19 shows a 64 QAM constellation.

[0060] FIG. 20 shows a 32-APSK constellation.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

Circuit Methodologies

[0061] As radio technology has evolved from low frequencies to higher and higher frequencies, the circuit methodologies optimized for the physical and practical constraints of lower-frequency communications were continually applied to higher frequency applications. This was done without consideration for differences in the physical and practical constraints characteristic of high frequency communications. As a result, previous attempts at delivering single-chip and minimal chipset solutions for frequencies above 64 GHz have not been successful at producing commercially viable radios at data rates exceeding 4 Gbps.

[0062] Two key conditions dictated early (lower frequency) chip designs for fixed point-to-point communications: 1) very limited available bandwidth in which to transmit as much data as possible, and 2) minimal dynamic range variation associated with rain fade and other weather or atmospheric variations. The first of these conditions dictated the adoption of very high-order modulation techniques such as 64-QAM, 128-QAM, or 256-QAM, in which several (6 to 8) digital bits could be sent simultaneously using a single pseudo-digital symbol, thereby increasing spectral throughput (bits per second per Hertz). The high-order modulation results in a penalty of 17 to 22 dB in transmitter power relative to single-bit symbol modulation (on-off keying or binary phase shift keying) to maintain a manageable bit error rate. The second key condition, the comparativcly lower atmospheric attenuation and weather fade characteristic of lower frequencies, made such modulation efficiency trades desirable for microwave radios, by requiring little additional signal to noise link margin to cope with high humidity and heavy rainfall.

Silicon-Germanium Semiconductors

[0063] Silicon-germanium bipolar transistors on complementary metal-oxide-semiconductor (referred to as SiGe BiCMOS) technology, which marries the superior low-noise and high-speed properties of the SiGe heterojunction bipolar transistors with the low cost and manufacturability advantages of conventional CMOS technology, represent an ideal solution for mixed-signal applications such as millimeter-wave wireless communications systems, in which frequency sources and multipliers, mixers and low-noise amplifiers are used alongside digital modulator control and processing circuitry. Amplifiers using SiGe bipolar transistors are more efficient and achieve lower noise figures than comparable conventional CMOS amplifiers, and the higher breakdown voltage of SiGe allows for higher device output power as well.

High Frequency Radio Components on Si and SiGe

[0064] Gallium Arsenide (GaAs) is superior to SiGe semiconductors for ultra-low phase noise high-frequency oscillators (so an external microwave phase-locked voltage-controlled oscillator (PLVCO) is a preferred frequency source), but the frequency multiplier chain, up-conversion and down-conversion mixers and millimeter-wave, microwave and baseband amplifiers can all be implemented satisfactorily using conventional microstrip circuitry on Si and SiGe semiconductor substrates. For lowest cost, a silicon wafer can be used as a substrate, with germanium placed locally on the chip at the locations of the millimeter-wave transistors and diodes, so that the SiGe material is localized only in the regions of the high-frequency MMW and microwave semiconductor junctions. Lower frequency circuitry, including the data encoder, high-speed driving logic and all other baseband and digital data and control electronics are implemented using standard CMOS processes on the same silicon substrate. The data decoder can be implemented on the receiver chip. A SiGe foundry, such as the Global Foundries foundry located near Essex Junction, Vt., with a 0.13-micron or 0.09-micron SiGe process can produce SiGe chips of the preferred design for 10 Gbps E-Band radio transceivers. A silicon foundry, such as TSMC in Taiwan, with a 0.028 micron Si CMOS process, can produce Si chips of the preferred design for 10 Gbps E-Band radio transceivers at even lower cost.

Chip Design

[0065] Prior radio-on-a-chip designs have universally featured heterodyne and super-heterodyne circuits with relatively narrow (<1 GHz) baseband frequency channels for modulation and demodulation, because the symbol rate was constrained far below 1 billion symbols per second by the channel bandwidth available for microwave radios. Optimal designs for E-Band radio chips will utilize baseband modulation bandwidths of 1 to 5 GHz to make use of the preferential E-Band rules allowing occupation of up to 5 GHz of contiguous spectrum per half-duplex radio path.

Transmitter Output Power

[0066] Ultimate output power is less important in E-Band radio than at lower frequencies, because rain fade quickly nullifies the benefits of a few dB of extra power even over a relatively short (approximately 1 km) link. Antenna gain is much higher at millimeter-waverelative to microwavefor a given antenna size, so effective radiated power (ERP) is greatly enhanced by antennas of modest size, further reducing the importance of an expensive and reliability-limiting power amplifier in the transmitter. An optimal E-Band radio design will have a typical output power not exceeding 200 milliwatts, but with flat gain and phase characteristics across the full operating band of the radio (1 to 5 GHz) and allowing for a large dynamic range in output power. At frequencies above 70 GHz high humidity and heavy rainfall results in substantial increases in atmospheric attenuation, so any excess link margin at these frequencies is needed to cope with weather-related signal fade, rather than for increased modulation efficiency.

Need for Low Order Modulation

[0067] The strong atmospheric attenuation associated with rain events is accompanied by large temporal variations in the signal amplitude and phase received from a remote transmitter. This effect makes it difficult to distinguish small differences in amplitude and phase imposed by a modulator from those imposed by the atmosphere, leading to high bit error rates from radios using high-order modulation schemes. The most robust modulation schemes are on-off keying and binary phase shift keying (OOK and BPSK), which require at least 1 Hz of bandwidth for each bit-per-second of data throughput. This modulation efficiency is acceptable for E-Band radios supporting up to at least 3.072 Gbps of data throughput (OBSAI protocols). For radios supporting 10-Gigabit Ethernet (10 Gig-E), the modulation efficiency must exceed 2 bits per second per Hz (e.g. 8PSK at 3 bits per second per Hz), but any higher order modulation schemes, typical of microwave radios, will be detrimental to radio performance.

Need for Amplitude-Insensitive Demodulator

[0068] The need for large power margin to accommodate rain events will often require the E-Band transmitter to transmit into the compression region of the output power amplifier. The symbol demodulator must be designed to be insensitive to amplitude, relying only on a power threshold and the polarity of the demodulated signals, so that the transmitter power amplifier may be pushed into compression during heavy rain events without significant degradation of symbol discrimination (bit error rate).

Output Power and Spectrum Gain Control

[0069] For this preferred embodiment shown in FIG. 1 operating at data rates of the 10.3125 Gbps the occupied transmit bandwidth is between 3.5 GHz and 5 GHz. The transceiver is designed to provide a power spectral density, over more than 70 percent of occupied bandwidth of the transmitter which is constant to within +/1.5 dB and the transceiver provides a dynamic range in power output exceeding 15 dB.

Comparison with Prior Art Chipset Radios

[0070] As explained in the background section recent advances in semiconductor technology have enabled the fabrication of increasingly complex mixed-signal (analog/digital) circuitry on a single integrated circuit chip or a chipset containing a minimal number of chips. Such circuitry has included analog microwave and millimeter-wave front-end amplifiers, filters, oscillators, and mixer/down-converters, as well as intermediate-frequency electronics, phase-lock loops, power control and back-end analog baseband circuitry, along with digital modulators and de-modulators, clock recovery circuits, forward error correction and other digital data management functions. Mixed-signal integrated chip solutions for wireless communications have universally evolved from RF frequencies below 1 GHz (e.g. 900 MHz handsets for wireless telephone in the home) to low microwave frequencies (analog/digital cell phone technology with carrier frequencies up to 2 GHz), to high microwave and low millimeter-wave frequencies (6 to 38 GHz) for wireless point-to-point broadband communications. Most recently, radio receivers and transmitters have been demonstrated using single-chip circuits at frequencies in the license-free band spanning 57 to 64 GHz. At these transmit frequencies the radios operate at very short distances due to the absorption of the radio beam by oxygen in air. These circuits have been based on techniques that have been successful to lower frequency radios. For example, these prior art radio-on-a-chip designs have featured heterodyne and super-heterodyne circuits with relatively narrow (<1 GHz) baseband frequency channels for modulation and demodulation, because the symbol rate was constrained far below 1 billion symbols per second by the channel bandwidth available for microwave radios. Embodiments of the present invention are designed to utilize the entire available bandwidth, greater than 1 GHz, for modulation and demodulation. Optimal designs for Applicants' radio chips will utilize baseband modulation bandwidths of 1 to 5 GHz to make use of the preferential rules including E-Band rules allowing occupation of up to 5 GHz of contiguous spectrum per half-duplex radio path.

Benefits of 8PSK Modulation

[0071] At a given data rate, an 8PSK-modulated radio operates at a two-times higher symbol rate than a more common 64-QAM-modulated radio, necessitating higher-performance and more expensive digitizers, digital-to-analog converters, and digital logic components. However, the sparser 8PSK constellation allows error-free operation at 5 dB lower signal-to-noise ratio than 64-QAM. Because the signal is transmitted at full power for every constellation point, power efficiency is 8 dB higher than 64-QAM. Since amplitude is fixed for all constellation points, the transmitter need not be backed off from full power but can be operated well into compression, offering another 7 dB advantage over 64-QAM. Combined, these advantages contribute an additional 20 dB to the link margin for an 8PSK radio relative to an equivalent 64-QAM radio, which translates to about a 75% longer path reach in a four nines (99.99% weather available) path.

A 10.3125 Gbps Transceiver

Transmitter

[0072] In a preferred embodiment, transmitters (shown in FIG. 1) for each radio transceiver supports a digital data rate of 10.3125 Gbps (10 Gigabits raw data per second plus IEEE 802.3 Clause 49 64b/66b encoding which accounts for the 0.3125 Gbps excess). Using 3-bit symbol encoding (differential 8PSK), the carrier phase is modulated at a symbol rate of 3.4375 billion-symbols-per-second, so as to fit easily into the 5 GHz channel modulation bandwidth allowed by the prevailing FCC band plan for E-Band communication. Serial data awaiting transmission is loaded at 10.3125 Gbps into a fast 40-bit serial buffer input of a Field-Programmable Gate Array (FIG. 2) and then clocked into the array processor at the slower rate of 257.8125 MHz (the ratio of the 10 GigE bit rate [i.e. 10.3125 Gbps] and the buffer length [40 bits]). In the FPGA, the bits are segmented sequentially into groups of three, one group representing each one data symbol to be transmitted by the D8PSK modulator.

Gray Coding

[0073] Gray coding was invented in 1947 by Frank Gray of Bell Laboratories as a means of reducing the number of erroneous bits transmitted in a noisy signal channel or noisy switching environment. The basic tenet of the invention is that data errors most often arise from mistaking symbol phase near the boundary between phase states; for instance when the phase of a noisy signal measured at 157 degrees actually represents the 180 symbol state, but is interpreted to belong to the slightly closer 135 symbol state. For a simple encoding scheme it is possible for such adjacent symbol phases to represent strongly different bit sequences: for instance the 135 state might represent the bits 011 while the 180 state represents the bits 100. In this case an error between the two adjacent states results in all three data bits being in error. The Gray code imposes a special sequence to the bit strings such that all adjacent phase states represent bit sequences that differ by only a single bit state, for instance:

TABLE-US-00003 0 000 45 001 90 011 135 010 180 110 225 111 270 101 315 100

Differential Gray Coding

[0074] With differential Gray coding, the phase state represented by each three bit Gray code is imposed as a modulator phase shift, rather than an absolute phase, at the subsequent cycle of the symbol clock. This technique eliminates the need for the local transmitter and remote receiver to share knowledge of a common absolute phase reference.

I/Q Modulator

[0075] Differential Gray coding of the data stream yields a progression of phase jumps that modulate the MMW carrier to encode the data. Graphically, these phase jumps push the MMW carrier phase around a circle on the phase (or I/Q) plot, as shown in FIG. 3. For instance, when the remote receiver recognizes a phase jump near 135, it recognizes the transmitted data string as a 010, per the previous table. Signal vector phase is stepped in the transmitter modulator by use of a pair of mixers modulating an intermediate-frequency (IF) carrier in quadraturethat is to say on two separate channels that are separated by 90 of the IF carrier frequency (see FIG. 3). One channel, the cosine, or in-phase (I) channel, modulates the signal amplitude along the real (x) axis of the phase plot (figure N); the other channel, the sine, or quadrature (Q) channel, modulates the signal along the imaginary (y) axis. The vector plot of symbol amplitude and phase, accumulated over many symbol periods, becomes the symbol constellation, which is shown for D8PSK modulation in FIG. 3.

Intermediate Frequency Phase Noise

[0076] Bit-error performance of a digital data link is a statistical concept, based on the likelihood of phase and amplitude noise on the signal exceeding the phase and amplitude spacing between points on the constellation. The 8PSK constellation has only one amplitude state, so phase noise is much more important than amplitude noise in determining bit-error rate. The convenience of using Differential 8PSK encoding comes at a price in radio noise sensitivity, since both the preceding and the current bit contribute noise to the measurement of phase change at the clock cycle. In order to achieve error-free transmission (10.sup.12 bit-error rate), the threshold for phase noise on the IF signal should be very low (for example, about 0.6 degrees, or about 10010.sup.15 seconds of jitter). However, the use of differential encoding reduces constraints on phase noise considerably, since the phase jitter is only important as integrated over the short interval between the two successive symbols. Phase noise suppression to the required level is accomplished through the use a phase-locked voltage controlled oscillator, driven by high-quality temperature-controlled crystal oscillator at around 78.125 MHz, and a phase-lock loop with a loop bandwidth in the range of 100 Hz (FIG. 4).

Digital-to-Analog Converters (DACs)

[0077] In order to jump to a specific position in the symbol constellation, the voltages at the vector modulator (I/Q mixer) inputs as shown in FIG. 5 must be driven to positive and negative levels proportional to the x- and y-magnitudes of the constellation point as shown in FIG. 3. Two independent DAC channels controlled by the FPGA (FIG. 2) are used to drive the x- and y-magnitudes. For D8PSK modulation, these DACs are driven to place the D8PSK constellation points at fixed 45 intervals around a fixed radius circle.

[0078] After each interval of the symbol clock (approximately 29110.sup.12 seconds), three sequential bits of new data are evaluated by a D8PSK Gray Encoder in the transmitter FPGA to determine how far the phase should progress on the next cycle, and by comparison with the I/Q phase of the previous symbol, what precise carrier phase should be imposed by the I/Q mixer. At the next clock cycle, appropriate digital controls are sent to the two independent DAC channels to drive the carrier to that phase state.

MMW Up-Converter

[0079] After vector (I/Q) modulation, the IF carrier is up-converted to the MMW transmit frequency and sent to the transmitter power amplifier and antenna.

Up-Converter Phase Noise

[0080] Similarly to the IF carrier, the phase noise of the upconverter oscillator affects the bit-error performance of the 10 GigE radio. A low-noise VCO is phase-locked at a multiple (9) of the temperature-controlled crystal, with a loop bandwidth of about 300 kHz, to achieve a phase noise of about 2.2 degrees at near 60 GHz (100 fs of jitter), where it acts as the local oscillator to drive the MMW up-converter mixer (FIG. 14).

System Clock

[0081] The master clock for the transmitter is derived from the 10 GigE input data line. A clock-and-data recovery circuit at the input (FIG. 6) strips the clock and divides it by 132 to tune the temperature-controlled crystal oscillator to a frequency near 78.125 MHz. Data clock jitter is smoothed by the 100 Hz loop bandwidth of a phase lock loop at the crystal frequency. The crystal oscillator then becomes the low-phase-noise reference frequency for both the IF carrier and the MMW upconverter. The recovered raw data clock is also divided by 40 to drive the FPGA clock each time the 40-bit serial data buffer is filled and ready for parallel transfer, and divided by 3 to drive the DAC at the 3.4375 GSps symbol rate.

[0082] A significant and critical feature of this timing architecture is that the MMW carrier frequency is in fact derived from the recovered GigE data clock, and is thereby allowed to float (within limits) with the input data rate. For a transmitter in the 71-76 GHz band, for instance, the data clock is divided by a factor of 132 to tune the 78.125 MHz crystal, and then split to two separate multipliersa 220 multiplier that generates the first IF (17.1875 GHz), and a 720 multiplier that acts as the MMW upconverter local oscillator (56.25 GHz). The sum of these two frequencies, 73.4375 GHz, becomes the carrier frequency near the center of the 71-76 GHz band. The carrier frequency is thus a rational multiple of the data rate as follows: 10.3125*(220+720)/132=73.4735 GHz. For the 81-86 GHz Band, the IF multiplier changes from 220 to 204 and the MMW LO multiplier changes from 720 to 864, such that the carrier frequency becomes 10.3125*(204+864)/132=83.4375 GHz. This feature of a common frequency reference for data clock and carrier frequency generation allows the remote receiver to exactly recover the signal carrier frequency without a Costas loop, simply by repeating the rational multiplication sequence on the recovered data clock.

Receiver

[0083] In this preferred embodiment, the receiver (FIG. 7) detects and demodulates the MMW signal from the remote D8PSK transmitter using clock and frequency references derived from the received data signal. This is made possible by the transmitter design feature that the RF carrier, the IF carrier and the symbol clock are all derived from the data clock recovered at the transmitter input.

Down-Converter

[0084] In the receiver, the MMW signal is downconverted using the same frequency plan (RF, IF and baseband frequencies) used in the remote transmitter.

Clock, Carrier and Data Recovery

[0085] After down-conversion, the IF signal is fed to a data demodulator. Along this feed, a small portion of the signal power is split off and directed into an edge detector circuit to recover the clock from the remote transmitter (FIG. 8). In this sense the local receiver is the slave to the master clock generated at the remote transmitter. [This also highlights the fact that the local transmitter and local receiver do not share a common clockeach transmitter carries the master clock for the receiver at the other end of the link]. At the 10 GigE standard data rate of 10.3125 Gbps and for the D8PSK data modulation carrying 3 bits per symbol, the recovered clock is at or very near 3.4375 GHz.

[0086] As in the transmitter, the recovered data clock reference is divided by a factor of 132 to tune an ultra-stable temperature-controlled crystal oscillator at 78.125 MHz (FIG. 9). In the receiver, this crystal is phase-locked at a loop bandwidth of 1 kHz, somewhat higher than the loop bandwidth used in the transmitter to allow it to track transmitter drifts, but low enough to minimize added phase noise and associated increase in the error vector magnitude (EVM) of the received signal constellation. The IF and MMW local oscillator frequencies are generated by the same integer multiples of the crystal oscillator frequency as those used in the remote transmitter, to lock the receiver to the carrier frequency of the remote transmitter, without the use of a Costas loop.

[0087] The larger fraction of the IF signal goes into an I/Q mixer of the same type used in the transmitter; here it is separated into its vector in-phase (I) and quadrature-phase (Q) channels. Since there is no absolute phase reference connecting the local receiver and remote transmitter, the recovered constellation may be rotated by an arbitrary amount relative to the transmitted constellation, but the Differential 8PSK encoding scheme ensures that only the phase change between symbols, and not the symbol phases themselves, are needed to decode the data.

Edge Detector

[0088] Another significant and critical feature of the radio architecture is the edge detector that recovers the remote master clock. In this circuit, shown in FIG. 9, the IF signal is split into two equal parts and recombined (mixed) after imposing a differential time delay of a -period of the IF carrier frequency, equivalent to about 10% of a symbol period. In the absence of sudden jumps in phase, the two inputs to the mixer are then out of phase and the mixer output is nulled. However, when the phase changes abruptly at the start of a new symbol, there is a period of one-half IF cycle where the two mixer inputs are not perfectly out of phase, and the power level at the output of the mixer spikes temporarily before settling back to zero for the rest of the symbol period. The amplitude of transition spikes vary depending upon the degree of phase change at the individual symbol edges, but the output of the edge detector is amplified to strongly to clip the spikes and then filtered in a narrow band around 3.4375 GHz so that only the fundamental clock frequency and fiducial timing phase are preserved.

Signal Demodulation

[0089] The I and Q outputs of the quadrature mixer are digitized in separate analog-to-digital converter (ADC) channels, and 12-bit digital data is streamed from each ADC synchronously into an FPGA (FIG. 10). In the FPGA, the I and Q waveforms are cleaned with an Inter-Symbol Interference (ISI) Equalization Filter to compensate signal distortion arising from band limiting of the transmitted signal. Vector phase is then determined through the ratio of the cleaned Q and I amplitudes (tangent of phase is Q/I) and compared with the phase of the previous symbol to determine the size of the phase jump. This measured phase jump is sorted into one of eight discrete 45-degree sector intervals and then compared against the Differential Gray Code table to recover the three bits encoded in the symbol step.

ISI Equalization Filter

[0090] The transmitted spectrum is restricted, by FCC regulations, to a fixed bandwidth (5 GHz in each of the 71-76 and 81-86 GHz bands). At a transmit symbol rate of 3.4375 GSps, third- and higher harmonics of the modulation spectrum must be filtered out prior to transmission over the air. This filtering leads to distortion of the signal waveform that must be compensated in the receiver prior to signal decoding. The compensation is applied as a form of Finite Impulse Response (FIR) filter, created by comparing a received signal waveform with a known reference copy of that waveform as generated, prior to channel filtering, in the remote transmitter. An inverse transfer function is computed such as to digitally reciprocate the received waveform in the FPGA and recreate the original, undistorted modulation waveform prior to data decoding. The implemented filter samples and compensates the received waveform through impulse samples at a number of taps, separated by single periods of the symbol rate.

Improving Bit Error Rates

[0091] The following discussion focuses specifically on techniques and for improving bit error rates for differentially-encoded, eight-state phase-shift keyed (DE8PSK) modulator, although it can be generalized to any m-state phase modulator. For a DE8PSK radio, the transmitted symbol constellation is shown in FIG. 11 which is a symbol constellation of a radio using 8PSK modulation.

[0092] With DE8PSK modulation, data is encoded, three bits at a time, through the time sequence, or progression, of transmitted symbols. Any time the symbol rotates by one position in the counterclockwise direction, for instance, the encoded data stream could indicate the three-bit sequence 001. Any time the symbol rotates by two positions in the counter-clockwise direction, the encoded data stream could indicate 011, and so on; each of the eight possible three-bit binary sequences is uniquely identifiable by a number of steps (0 through 7) in the counterclockwise direction.

[0093] If the receiver's local frequency reference, used to demodulate the received signal waveform, is slightly offset from the frequency of the remote carrier, the constellation shown in FIG. 1 can rotate slowly, for instance to a position such as that shown in FIG. 12. This symbol constellation of an 8PSK radio shows an imperfect carrier recovery in the receiver that is rotating slowly in clockwise or counterclockwise direction relative to the constellation shown in FIG. 11.

[0094] This rotation will not change the formula for indicating data sequences; an inter-symbol counter-clockwise rotation of one or two positions would still represent 001 and 011 respectively, so absolute symbol phase becomes irrelevant, and small offset of reference and carrier frequencies is acceptable without consequence. This fact eases fidelity requirements on the receiver's carrier recovery technique, allowing for lower transceiver cost and complexity.

[0095] Measuring phase shift between symbols involves measurement of two phasesnamely the before and after phases across the symbol transition. FIG. 13 shows nominal measurements of these phase measurements, each residing within a symbol point cluster, but each with a small amount of uncorrelated signal noise from thermal sources.

[0096] The number of counter-clockwise steps between data symbols is determined by measuring the vector angles of the before and after receive signals, taking the difference between these measurements, dividing by the step interval (in this case 45 degrees), and then rounding to the nearest integer. If the root-mean-square (RMS) deviation of each vector angle measurement from the ideal (noise-free) positioni.e. the centroid of each point clusteris a given amount .sub., then the RMS error in the difference angle becomes:

.sub.(.sub.1.sub.-.sub.2.sub.)={square root over (.sub.1.sup.2+.sub.2.sup.2)}={square root over (2)}.sub.(1) (1)

[0097] Thus the differential measurement increases the angle error by a factor of the square root of two relative to the error in either of the two (before and after) angle measurements taken separately. The significant impact of this increased angle error for differentially-encoded radio performance is made evident by considering its impact on radio bit-error rate.

[0098] FIG. 14 shows a plot of the complementary error function erfc(x), which for Gaussian error distributions describes the likelihood of an individual measurement being separated from its mean value by more than a given number of standard deviations and indicating the likelihood that a certain measurement will fall outside of a given multiple of the RMS error away from its mean, assuming a Gaussian error distribution.

[0099] Referring to FIG. 14, an RMS error of 5 degrees in the phase shift measurement (for which 4.5=22.5) leads to an error probability of approximately 10.sup.5. By comparison, the corresponding error in the individual before and after phase measurements is 5/{square root over (2)}=3.54 degrees (for which 6.36=22.5) and the error probability in assignation of either symbol to a given symbol cluster is approximately 10.sup.10.

[0100] For DE8PSK modulation, the maximum error in measured phase shift which can be tolerated without generating a bit error is +/22.5 degrees, or half of the 45 degree step between constellation clusters. For error larger than this threshold, the rounding step in the demodulation algoritlun will under- or overestimate the number of counterclockwise rotation quanta represented by the phase transition, thus leading to an error in the reconstructed bit stream. The significance of five orders of magnitude in raw bit error rate is reflected in the amount of throughput overhead needed to correct the bit errors that do occur. Correcting bit errors in a data stream with a raw BER of 10.sup.5 requires an aggressive Forward Error Correction (FEC) algorithm with significant overhead (7%) to achieve a corrected BER of better than 10.sup.20. This overhead reduces achievable data rate within a given allocated radio frequency bandwidth. By comparison, a data stream with a raw BER of 10.sup.10 needs an FEC algorithm with less than 1% overhead to achieve the same corrected BER, allowing significantly more data throughput over the allocated frequency band. Likewise the substantial link latency imposed by more aggressive FEC algorithms is highly detrimental to aggregated high-bandwidth backhaul applications. It is thus desirable to construct a means of achieving the benefits to link cost and complexity offered by differentially-encoded PSK, without incurring the higher noise associated with the differentiating process.

Constellation Averaging Technique

[0101] The RMS noise shown in equation 1 for a differential phase shift measurement assumes that the noise level on the before and after phase states is the same. This is strictly true for measurements taken over equal symbol periods, as is the case for any constant-rate transmission. However, it is possible in principle to reduce the effective noise level of the before phase measurement, by including this measurement in an ensemble average of a large number of previous symbol vectors associated with the same constellation cluster.

[0102] The optimum number of prior symbols to be included in the ensemble average is a balance between reducing differential phase error (which improves for larger ensembles) and blurring of the cluster centroid due to constellation rotation and carrier phase noise (which are made worse for larger ensembles). FIG. 15 shows the reduction in differential phase error and FIG. 16 shows the increase in phase blur associated with averaging over ensembles of different sizes, assuming a 10 GigE 8PSK transceiver with a 300 kHz difference in frequency between transmitted carrier and receiver-replicated carrier. Specifically FIG. 15 shows the RMS error reduction due to symbol averaging, relative to an ideal non-differential modulator, and FIG. 16 shows the integrated constellation rotation versus ensemble size, for a specified symbol rate and carrier frequency offset (3.4375 Gsps and 300 kHz respectively).

[0103] It is evident that most of the benefit of symbol averaging is achieved with ensembles as small as 8 symbols, while ensembles larger than 32 symbols may suffer measurable rotation blurring. Ensembles of 8 symbols bring the error down to within one percent of the asymptotic minimum (which is the theoretical error level that could be achieved by an ideal non-differential demodulator), while incurring a phase blur of less than 0.3 degrees (approximately 1% of the threshold for producing bit errors). For slower constellation rotation, larger ensembles might be used, but with minimal further impact in improving radio link performance.

Constellation Averaging Algorithm

[0104] In order to make optimum use of fast mathematical processing in a Field-Programmable Gate Array or other custom digital ASIC, averaging is done on ensembles of size 2.sup.N, with N an integer. This reduces the divide after summation to a simple bit truncation. For instance, a symbol's vector angle might be represented as a signed 17-bit hex datum, including the sign bit, a most significant bit corresponding to 360 degrees of phase, and 16 more bits with the phase represented by each successive bit corresponding to a halving of the previous bit phase, as shown in FIG. 17. This figure provides a binary representation of a symbol's vector phase, truncated to its modulo45 residual for simplification of error averaging.

[0105] In this case, simple truncation of the hex datum to the thirteen least significant bits generates a signed, modulo45 remainder that can be averaged over successive symbols and used to track the rotation of the constellation. Regardless of which symbol cluster a specific symbol falls into, this remainder reflects the rotating modulo45 cluster centroid and the residual error of the individual symbol. In order to average 8 successive symbols, the 13-bit truncated values are summed to a 16-bit datum, and then the three least significant bits are dropped to generate the signed 12-bit data average. Once this average is updated for a new symbol, bits 17 to 13 of the original datum (as shown in FIG. 6) are concatenated back onto the average to regenerate the signed 17-bit symbol position, now corrected for its random error. This corrected value serves as the before symbol for comparison with the subsequent (uncorrected) symbol vector measurement in calculating the phase step between symbols. Using this averaging, the error in the differential phase coding modulator drops to within 1% of that of an ideal non-differential phase modulator, while providing a significant reduction m complexity and cost of the radio hardware. This technique and method were implemented on a Xilinx Virtex-7 FPGA and resulted in a five-order-of-magnitude improvement (from 10.sup.7 BER before to 10.sup.12 BER after) in bit-error rate performance of a 10 GigE MMW radio link without FEC.

Variations

[0106] Although a preferred embodiment of the present invention has been described in detail above, persons skilled in the radio art will recognize that many variations are possible within the scope of the present invention. Some variations are listed below

Other High Data Rate Millimeter Radios

[0107] Applicant has described a preferred embodiment of a radio supporting a data rate of 10 Gbps using a differential octal phase shift keyed (D8PSK) modulator; however the radio on a chip or minimal chipset should not be considered to be bound by this data rate or modulation approach. Indeed at lower data rates, more robust modulation approaches such as DBPSK or DQPSK may be employed and would allow for bit-error-free operation at lower link margins.

[0108] A popular data transfer standard supported by one radio sold by Applicant is the Gigabit-Ethernet (GigE) standard which exchanges data at a rate of 1.25 Gbps. At this rate, and for data rates up to about 3.5 Gbps, the preferred modulation scheme is Differential Binary Phase Shift Keying (DBPSK), where the difference between phase states (180 degrees) is four times larger than for D8PSK (45 degrees), and consequently a lower signal-to-noise ratio is required to distinguish between phase states. The DBPSK design is described in parent application Ser. No. 12/928,017 which has been incorporated herein by reference. In accordance with the present invention these circuits would be fabricated on a single chip or chipset utilizing well-known integrated circuitry fabrication techniques as explained above with respect to the first preferred embodiment. Beyond data rates of 3.5 Gpbs, the Federal Communication Commission allocated channel bandwidth becomes insufficient to support the modulation rates, and it becomes necessary to transmit data symbols representing more than one data bit at a time. For radios supporting data transfer rates between 3.5 Gbps and about 7 Gbps, the preferred modulation approach is Differential Quadrature Phase Shift Keying (DQPSK), in which two bits of data are sent simultaneously within each symbol, and the spacing between the four possible symbol phase states is 90 degrees. For radios supporting data rates between 7 Gbps and about 10.5 Gbps, the preferred modulation approach is Differential Octal Phase Shift Keying (D8PSK), in which three bits of data are sent simultaneously, as described in the first preferred embodiment for this patent. For radios supporting even higher data rates the modulation scheme is chosen to send four or more bits of data simultaneously, and the link margin (or signal-to-noise ratio) required for maintaining error-free transmission becomes successively higher.

Even Higher Data Rates

[0109] For data rates in excess of 10.5 Gbps, progressively higher order modulation schemes are necessary. Symbol constellations on 16 symbols, such as 16-QAM, encode 4 bits per symbol, supporting data rates up to 14 Gbps. (See FIG. 18.) Constellations of 32 symbols, such as 32-state Amplitude and Phase Shift Keying (32-APSK), encode 5 bits per symbol, supporting data rates of 17.5 Gbps. (See FIG. 20 Constellations of 64 symbols (see FIG. 19), such as 64-QAM, encode 6 bits per symbol and support data rates to 21 Gbps, and so on. Successively higher order modulation schemes impose higher and higher signal-to-noise requirement thresholds and greater restrictions on amplifier linearity, so extension to infinite data rates is not practical. The use of differential encoding, and in particular prior-symbol averaging to reduce demodulation noise and improve bit-error rate performance (as described above) applies to such higher modulation schemes as well as to DEMPSK. For a symbol constellation that is slowly rotating due to oscillator phase noise and/or imperfect carrier frequency recovery, integrating the centroid of each constellation point over a period short compared to that for which the rotation blurs two points into one, reduces the demodulation noise contribution from small displacements of the prior symbol and thereby drives the BER performance asymptotically toward that of non-differential encoding at the same modulation order.

[0110] Chip-based radio transceivers designed for a range of data transfer rates less than the threshold rates of 3.5 Gbps, will preferably include modulator/demodulators of the DBPSK types. For data rates above 3.5 Gbps and below 7.0 Gbps, DQPSK is preferred. And for rates above 7.0 Gbps and below 10.5 Gbps, D8PSK is preferred.

Silicon-Germanium Semiconductors

[0111] The components of the millimeter wave radios described above are in general state of the art millimeter wave and optical fiber components. However, many of the components could be fabricated together on one or more semiconductor substrates to produce very low cost millimeter wave radios. Silicon-germanium bipolar transistors on complementary metal-oxide-semiconductor (referred to as SiGe BiCMOS) technology, which marries the superior low-noise and high-speed properties of the SiGe heterojunction bipolar transistors with the low cost and manufacturability advantages of conventional CMOS technology, represent an ideal solution for mixed-signal applications such as millimeter-wave wireless communications systems, in which frequency sources and multipliers, mixers and low-noise amplifiers are used alongside digital modulator control and processing circuitry. Amplifiers using SiGe bipolar transistors are more efficient and achieve lower noise figures than comparable conventional CMOS amplifiers, and the higher breakdown voltage of SiGe allows for higher device output power as well.

High Frequency Radio Components on Si and SiGe

[0112] Gallium Arsenide (GaAs) is superior to SiGe semiconductors for ultra-low phase noise high-frequency oscillators (so an external microwave phase-locked voltage-controlled oscillator (PLVCO) is a preferred frequency source), but the frequency multiplier chain, up-conversion and down-conversion mixers and millimeter-wave, microwave and baseband amplifiers can all be implemented satisfactorily using conventional micro-strip circuitry on Si and SiGe semiconductor substrates. For lowest cost, a silicon wafer can be used as a substrate, with germanium placed locally on the chip at the locations of the millimeter-wave transistors and diodes, so that the more expensive SiGe material is localized only in the regions of the high-frequency MMW and microwave semiconductor junctions. Lower frequency circuitry, including the data encoder, high-speed driving logic and all other baseband and digital data and control electronics may be implemented using standard CMOS processes on the same silicon substrate. Recent advances in Si processing to 28-nm process feature sizes have enabled transistor cutoff frequencies above 100 GHz on pure silicon substrates as well. A SiGe foundry, such as the IBM foundry located near Essex Junction, Vt., with a 0.13-micron or 0.09-micron SiGe process can produce SiGe chips of the preferred design for 10 Gbps E-Band radio transceivers. And as indicated above, a Si-CMOS foundry with a 28-nm process in Taiwan can likewise produce chips of the preferred design at an even lower price.

Other Variations

[0113] The radio described in this patent is capable of delivering data rates in excess of 3.5 Gigabits per second. The preferred embodiments in this description operate under the Internet Protocol (IP) Ethernet Standard at 10 Gigabits per second with a small amount of overhead for ensuring bit toggling at some minimum speed. There are, however, many other communications standards which involve serial transfer of binary data at speeds in excess of 3.5 Gigabits per second and within the maximum bandwidth capability of this radio. Some of these include:

SONET OC-96 (4.976 Gbps)

4Gig-E (5.00 Gbps)

5Gig-E (6.25 Gbps)

OBSAI RP3-01 (6.144 Gbps)

6Gig-E (7.50 Gbps)

Fibre Channel 8GFC (8.5 Gbps)

SONET OC-192 (9.952 Gbps)

Fibre Channel 10GFC Serial (10.52 Gbps)

[0114] The High Data Rate Wireless Communications Radio described in this patent will support all of these protocols and a variety of others, up to a maximum data rate of about 13 Gbps. In preferred embodiments operating at data rates in the range of about 3.5 Gbps the occupied transmit bandwidth should be between 1.0 GHz and 5 GHz. For the higher data rates the transmit bandwidth will preferably be in a range closer to the 5 GHz limit.

[0115] Therefore readers should determine the scope of the present invention by reference to the appended claims.