METHOD OF MANUFACTURING A HYBRID SUBSTRATE

Abstract

A method of manufacturing a hybrid substrate is disclosed, which comprises: bonding a first semiconductor substrate to a first combined substrate via at least one layer of dielectric material to form a second combined substrate, the first combined substrate includes a layer of III-V compound semiconductor and a second semiconductor substrate, the layer of III-V compound semiconductor arranged intermediate the layer of dielectric material and second semiconductor substrate; removing the second semiconductor substrate from the second combined substrate to expose at least a portion of the layer of III-V compound semiconductor to obtain a third combined substrate; and annealing the third combined substrate at a temperature about 250 C. to 1000 C. to reduce threading dislocation density of the layer of III-V compound semiconductor to obtain the hybrid substrate.

Claims

1. A method of manufacturing a hybrid substrate, comprising: (i) bonding a first semiconductor substrate to a first combined substrate via at least one layer of dielectric material to form a second combined substrate, the first combined substrate includes a layer of III-V compound semiconductor and a second semiconductor substrate, the layer of III-V compound semiconductor arranged intermediate the at least one layer of dielectric material and the second semiconductor substrate; (ii) removing the second semiconductor substrate from the second combined substrate to expose at least a portion of the layer of III-V compound semiconductor to obtain a third combined substrate; and (iii) annealing the third combined substrate at a temperature about 250 C. to 1000 C. to reduce threading dislocation density of the layer of III-V compound semiconductor to obtain the hybrid substrate.

2. The method of claim 1, wherein subsequent to step (i) and prior to step (ii), further comprises at least one of: inverting the second combined substrate; and depositing a layer of protective material on the first semiconductor substrate.

3. The method of claim 1, wherein step (ii) includes at least one of: using a combination of mechanical grinding and wet-etching the second combined substrate in a solution of tetramethylammonium hydroxide to remove the second semiconductor substrate; and (iv) at least partially grinding the second semiconductor substrate, (v) arranging the second combined substrate to be in a solution of tetramethylammonium hydroxide to remove the second semiconductor substrate, and (vi) performing etch-stopping on the exposed portion of the layer of III-V compound semiconductor.

4. (canceled)

5. The method of claim 1, wherein the at least one layer of dielectric material is formed on the first combined substrate, and arranged adjacent to the layer of III-V compound semiconductor.

6. The method of claim 5, wherein the at least one layer of dielectric material is formed using plasma-enhanced chemical vapour deposition or atomic layer deposition.

7. (canceled)

8. The method of claim 1, wherein the first and second semiconductor substrates are respectively formed from a silicon-based material.

9. The method of claim 8, wherein the second semiconductor substrate is a silicon substrate with 6 off-cut toward [111] direction.

10. The method of claim 1, wherein prior to the bonding, further comprises: performing plasma cleaning on the first combined substrate and first semiconductor substrate; washing the cleaned first combined substrate and first semiconductor substrate with a deionized fluid; and drying the washed first combined substrate and first semiconductor substrate.

11. The method of claim 10, wherein the deionized fluid is deionized water.

12. The method of claim 10, wherein drying the washed first combined substrate and first semiconductor substrate includes using spin-drying.

13. The method of claim 1, wherein step (i) further includes annealing the second combined substrate to increase the bonding between the first semiconductor substrate and the at least one layer of dielectric material.

14. The method of claim 13, wherein the annealing is performed using nitrogen at a temperature of about 300 C. and at atmosphere pressure.

15. The method of claim 10, wherein the plasma cleaning is performed with oxygen plasma, hydrogen plasma, argon plasma, or nitrogen plasma.

16. (canceled)

17. The method of claim 2, wherein the protective material includes ProTEK B3-25, silicon dioxide or silicon nitride.

18. (canceled)

19. The method of claim 3, wherein the first solution is heated to a temperature of about 80 C.

20. The method of claim 3, further comprises depositing a layer of protective material on the first semiconductor substrate; and removing the protective material from the first semiconductor substrate using acetone or oxygen plasma configured with a power of about 800 W, subsequent to step (v).

21. The method of claim 1, wherein the at least one layer of dielectric material includes a plurality of layers of different dielectric materials.

22. A method of manufacturing a hybrid substrate, comprising: (i) bonding a first semiconductor substrate to a first combined substrate via at least one layer of dielectric material to form a second combined substrate, the first combined substrate includes a germanium layer, a layer of III-V compound semiconductor and a second semiconductor substrate, the germanium layer arranged intermediate the second semiconductor substrate and layer of III-V compound semiconductor, the layer of III-V compound semiconductor arranged intermediate the at least one layer of dielectric material and the germanium layer; (ii) removing the second semiconductor substrate and germanium layer from the second combined substrate to expose at least a portion of the layer of III-V compound semiconductor to obtain a third combined substrate; and (iii) annealing the third combined substrate at a temperature about 250 C. to 1000 C. to reduce threading dislocation density of the layer of III-V compound semiconductor to obtain the hybrid substrate.

23. The method of claim 22, wherein step (ii) includes: (iv) using a combination of mechanical grinding and wet-etching the second combined substrate in a first solution of tetramethylammonium hydroxide to remove the second semiconductor substrate.

24. The method of claim 23, wherein subsequent to step (iv), further comprises using a second solution which includes 10% of hydrogen peroxide to remove the germanium layer.

25-26. (canceled)

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Embodiments of the invention are disclosed hereinafter with reference to the accompanying drawings, in which:

[0036] FIGS. 1a to 1e collectively depict a method of manufacturing a hybrid substrate, according to a first embodiment;

[0037] FIG. 2 is an infrared (IR) image of the plan-view of a second combined substrate obtained at step 152 of FIG. 1b;

[0038] FIG. 3 is a cross-sectional scanning electron microscope (X-SEM) micrograph of a fabricated sample of the hybrid substrate manufactured using the method of the first embodiment;

[0039] FIG. 4 is a graph depicting high resolution X-ray diffraction (HRXRD) profiles measuring the full-width at half maximum (FWHM) of a GaAs/Si substrate, and a GaAs-OI substrate (before and after annealing);

[0040] FIG. 5 is a graph depicting photoluminescence (PL) intensity measurement of a GaAs/Si substrate and a GaAs-OI substrate (before and after annealing);

[0041] FIG. 6a is a photograph showing etch-pitch-density (EPD) of a GaAs/Si substrate;

[0042] FIG. 6b is a photograph showing EPD of a GaAs-OI substrate before annealing, and FIG. 6c is a photograph showing EPD of the GaAs-OI substrate after annealing, with reference to the method of the first embodiment;

[0043] FIG. 7a is a plan-view transmission electron microscopy (TEM) image of a GaAs layer (i.e. the layer of III-V compound semiconductor) of the hybrid substrate before annealing, and FIG. 7b is a plan-view TEM image of the GaAs layer after annealing;

[0044] FIGS. 8a to 8f collectively depict a method of manufacturing a hybrid substrate, according to a second embodiment;

[0045] FIG. 9 is an IR image of the plan-view of a second combined substrate obtained at step 852 of FIG. 8b;

[0046] FIG. 10 is a X-SEM micrograph of a fabricated sample of the hybrid substrate manufactured using the method of the second embodiment;

[0047] FIG. 11 is a graph depicting HRXRD profiles measuring the FWHM of a GaAs/Ge/Si substrate, and a GaAs-OI substrate (before and after annealing);

[0048] FIG. 12 is a graph depicting PL intensity measurement of a GaAs/Ge/Si substrate and a GaAs-OI substrate (before and after annealing); and

[0049] FIG. 13a is a photograph showing EPD of a GaAs-OI substrate before annealing, and FIG. 13b is a photograph showing EPD of the same GaAs-OI substrate after annealing, with reference to the method of the second embodiment.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

[0050] FIGS. 1a to 1e depict (steps of) a method 100 of manufacturing a hybrid substrate 180, according to a first embodiment. At step 150 (i.e. FIG. 1a), a first semiconductor substrate 102, and a first combined substrate 104 are provided, in which the first semiconductor substrate 102 is provided above the first combined substrate 104. The first combined substrate 104 includes (arranged from top to bottom sequentially): at least one layer of dielectric material 106, a layer of III-V compound semiconductor 108, and a second semiconductor substrate 110. The layer of III-V compound semiconductor 108 is arranged intermediate the layer of dielectric material 106 and second semiconductor substrate 110. More particularly, the layer of III-V compound semiconductor 108 includes a combination based at least one group III semiconductor material (e.g. gallium (Ga), indium (In) or aluminium (Al)) and one group V semiconductor material (e.g. phosphorus (P) arsenic (As) or antimony (Sb)). Possible examples of the layer of III-V compound semiconductor 108 include GaAs, InP, InGaAs, InGaP, InGaAsP, or other combination of III-As/P material systems. But for this embodiment, GaAs is used as an example of the layer of III-V compound semiconductor 108.

[0051] It is to be appreciated that both the first and second semiconductor substrates 102, 110 are respectively formed from a silicon-based material. In this case, both the first and second semiconductor substrates 102, 110 are formed from silicon (Si), and moreover, the second semiconductor substrate 110 is an epi-ready <100> orientated Si wafer substrate with 6 off-cut towards the nearest [111] direction. Also, the first and second semiconductor substrates 102, 110 may respectively be termed a Si handler substrate, and a Si donor substrate. Furthermore, a two-step GaAs growth was used to grow the GaAs epilayer (i.e. the layer of III-V compound semiconductor 108) directly on a Si donor wafer (i.e. the second semiconductor substrate 110) to obtain the first combined substrate 104.

[0052] Separately, it is to be appreciated that the layer of dielectric material 106 (e.g. 500 nm thick) serves as a capping layer for the layer of III-V compound semiconductor 108 (with regard to the first combined substrate 104), and also provides a bonding interface at step 152 (described below). The dielectric material is selected from the group consisting of aluminium oxide (Al.sub.2O.sub.3), aluminium nitride (AlN), silicon dioxide (SiO.sub.2), synthetic diamond, silicon nitride (Si.sub.3N.sub.4) and boron nitride (BN), but other suitable dielectric materials are usable too. The layer of dielectric material 106 is formed using, for example, plasma-enhanced chemical vapour deposition (PECVD) or atomic layer deposition to deposit the dielectric material onto the layer of III-V compound semiconductor 108. It is to be appreciated that in variant embodiments, the layer of dielectric material 106 can instead be formed on the first semiconductor substrate 102, rather than on the first combined substrate 104. Yet alternatively, respective layers of (same/different) dielectric material(s) may be formed on the first semiconductor substrate 102 and first combined substrate 104, and then the respective layers of dielectric material(s) are bonded together at step 152 (in the process of bonding the first semiconductor substrate 102 to the first combined substrate 104). Moreover, it is also possible that a plurality of layers of different dielectric materials (and combinations thereof) may be formed on the first combined substrate 104, if desired, instead of just a single layer 106.

[0053] At step 152 (i.e. FIG. 1b), the first semiconductor substrate 102 is then bonded to the first combined substrate 104 via the layer of dielectric material 106 to form a second combined substrate 112. FIG. 2 shows an infrared (IR) image 200 of the plan-view of the second combined substrate 112 obtained from step 152. So, from a top-down perspective, the second combined substrate 112 is configured with the following layers: the first semiconductor substrate 102, the layer of dielectric material 106, the layer of III-V compound semiconductor 108, and the second semiconductor substrate 110. After bonding, the second combined substrate 112 is optionally annealed to further increase/enhance the bonding strength between the first semiconductor substrate 102 and the layer of dielectric material 106. The annealing is performed (for about three hours) using nitrogen (N.sub.2) at a temperature of about 300 C. and at ambient atmosphere pressure. But not limiting, other alternative suitable gases such as oxygen (O.sub.2), hydrogen (H.sub.2), forming gas, helium (He), or argon (Ar) may also be used for the annealing, depending on specific requirements. It is to be appreciated that for variant embodiments where the layer of dielectric material 106 is formed on the first semiconductor substrate 102, the annealing is then carried out to increase the bonding strength between the layer of dielectric material 106 and the layer of III-V compound semiconductor 108.

[0054] It is also to be highlighted that optionally, subsequent to step 150 and prior to step 152, plasma cleaning (e.g. using oxygen plasma, hydrogen plasma, argon plasma, or nitrogen plasma) may be performed on the first semiconductor substrate 102, and first combined substrate 104 for about 15 seconds each, followed by washing the cleaned first semiconductor substrate 102, and first combined substrate 104 with a deionized fluid (e.g. deionized water), and finally drying (e.g. spin-drying) the washed first semiconductor substrate 102, and first combined substrate 104. These additional steps are taken to better prepare the first semiconductor substrate 102, and first combined substrate 104 for the bonding at step 152.

[0055] Next at step 154 (i.e. FIG. 1c), the second combined substrate 112 is vertically inverted, and the sequence of the layers of the second combined substrate 112 now becomes vertically reversed, from the top-down perspective.

[0056] At further step 156 (i.e. FIG. 1d), the second semiconductor substrate 110 is removed from the second combined substrate 112 to expose at least a portion of the layer of III-V compound semiconductor 108 to obtain a third combined substrate 114. In this case, the entire top surface of the layer of III-V compound semiconductor 108 is exposed, and the top surface is arranged in opposition to the bottom surface of the layer of III-V compound semiconductor 108 that is adjacent to and in contact with the layer of dielectric material 106. Specifically, the second semiconductor substrate 110 is removed from the second combined substrate 112 by submerging the second combined substrate 112 in a solution of tetramethylammonium hydroxide (TMAH) heated to about 80 C. Upon completion, etch stopping is performed on the layer of III-V compound semiconductor 108. Alternatively, the second semiconductor substrate 110 may also be removed using a combination of mechanical grinding and wet etching (using suitable solvents).

[0057] It is to be appreciated that subsequent to step 154 and prior to step 156, a layer of protective material (not shown) (e.g. ProTEK B3-25, silicon dioxide (SiO.sub.2), silicon nitride (SiN), or combinations thereof) may optionally be deposited on the first semiconductor substrate 102. Specifically, the protective material is spin coated on a first surface of the first semiconductor substrate 102, the first surface opposing a second surface (of the first semiconductor substrate 102) on which the dielectric material 106 is arranged adjacent, to act as a protection layer during the process of removing the second semiconductor substrate 110.

[0058] After the second semiconductor substrate 110 has been completely removed with no existence of bubbles observed, the coating of protective material is removed from the first semiconductor substrate 102 using oxygen plasma configured with an operating power of about 800 W. Alternatively, the coating of protective material may be removed using acetone.

[0059] At step 158 (i.e. FIG. 1e), the third combined substrate 114 is annealed at a temperature about 250 C. to 1000 C. (for one or several cycles) to reduce threading dislocation density (TDD) of the layer of III-V compound semiconductor 108 to obtain the hybrid substrate 180. It is to be appreciated that the effective temperature for the recrystallization process (to reduce TDD) is determined to be about of the melting point of the layer of III-V compound semiconductor 108. So, if GaAs is used as the layer of III-V compound semiconductor 108, the annealing temperature is then about 850 C. To be clear, the hybrid substrate 180 is the third combined substrate 114 that has been subjected to annealing. From a top-down perspective, the hybrid substrate 180 consists: the layer of III-V compound semiconductor 108, the layer of dielectric material 106, and the first semiconductor substrate 102. It is to be appreciated that annealing is carried out using a gas selected from the group consisting of O.sub.2, H.sub.2, N.sub.2, forming gas, He and Ar. For avoidance of doubt, it is highlighted that only steps 152, 156 and 158 of the disclosed method 100 are needed as a bare minimum; the other steps are either optional or may not be performed as part of the method 100.

[0060] FIG. 3 is a cross-sectional scanning electron microscope (X-SEM) micrograph 300 of a fabricated sample of the hybrid substrate 180 manufactured using the proposed method 100. In this case, the layer of III-V compound semiconductor 108 is GaAs (e.g. 436 nm thick), and the layer of dielectric material 106 is SiO.sub.2 (e.g. 315 nm thick).

[0061] FIG. 4 is a graph 400 depicting high resolution X-ray diffraction (HRXRD) profiles measuring the full-width at half maximum (FWHM) of a GaAs/Si substrate, and a GaAs-OI substrate (before and after annealing). The GaAs-OI substrate is the hybrid substrate 180 manufactured using the method 100, and OI is an abbreviation for on-insulator. In FIG. 4, #1, #2 and #3 in the legend column respectively represent GaAs/Si, GaAs-OI before annealing, and GaAs-OI after annealing. Specifically, it is observed that the FWHM measured has decreased from 416 arcsec to 250 arcsec after annealing. FIG. 5 then depicts a graph 500 of photoluminescence (PL) intensity measurement of the same GaAs/Si substrate and GaAs-OI substrate (before and after annealing). In FIG. 5, #1, #2 and #3 in the legend column respectively represent GaAs-OI before annealing, GaAs-OI after annealing, and GaAs/Si. Accordingly, it is observed that the PL intensity has increased by at least 2 times after annealing, which indicates a better GaAs crystal quality is obtained post-annealing.

[0062] FIG. 6a is a first photograph 600 showing etch-pitch-density (EPD) of a GaAs/Si substrate, which was measured to be greater than 210.sup.8/cm.sup.2. FIG. 6b is a second photograph 610 showing EPD of the GaAs-OI substrate (mentioned in relevant text of FIG. 4) before annealing, which was measured to be about 510.sup.7/cm.sup.2. FIG. 6c is a third photograph 620 showing EPD of the same GaAs-OI substrate after annealing, which was measured to be about 310.sup.6/cm.sup.2 showing that the EPD has been significantly reduced (i.e. improved crystal quality of the GaAs layer).

[0063] FIG. 7a is a plan-view transmission electron microscopy (TEM) image 700 of the layer of III-V compound semiconductor 108 (i.e. GaAs being used) of the hybrid substrate 180 before annealing, in which more than 30 threading dislocations are detected. FIG. 7b is a plan-view TEM image 710 of the same GaAs layer after annealing, in which only about 2-3 threading dislocations are now observed.

[0064] The remaining configurations/embodiments will be described hereinafter. For the sake of brevity, description of like elements, functionalities and operations that are common between the different configurations/embodiments are not repeated; reference will instead be made to similar parts of the relevant configuration(s)/embodiment(s).

[0065] According to a second embodiment, FIGS. 8a to 8f depict a variant method 800 of manufacturing the hybrid substrate 180. But in this embodiment, the reference numeral 880 is instead used for the hybrid substrate 880 to differentiate from that in the first embodiment to avoid confusion. At step 850 (i.e. FIG. 8a), a first semiconductor substrate 802, and a first combined substrate 804 are provided, in which the first semiconductor substrate 802 is provided above the first combined substrate 804. The first combined substrate 804 includes (arranged from top to bottom sequentially): at least one layer of dielectric material 806, a layer of III-V compound semiconductor 808, a germanium layer 810, and a second semiconductor substrate 812. It is to be appreciated that the physical and material properties/characteristics of the first semiconductor substrate 802, second semiconductor substrate 812, layer of dielectric material 806, layer of III-V compound semiconductor 808, and second semiconductor substrate 812 are entirely same to the similarly-named elements of the first embodiment and hence not repeated here. Also, the first and second semiconductor substrates 802, 812 may respectively be termed a Si handler substrate, and a Si donor substrate. Again, GaAs is used as an example of the layer of III-V compound semiconductor 808 here.

[0066] The layer of dielectric material 806 (e.g. 500 nm thick) serves as a capping layer for the layer of III-V compound semiconductor 808 (with regard to the first combined substrate 804), and then provide a bonding interface at step 852. The layer of dielectric material 806 can be formed using PECVD, or atomic layer deposition to deposit the dielectric material onto the layer of III-V compound semiconductor 808. It is to be appreciated that in variant embodiments, the layer of dielectric material 806 may instead be formed on the first semiconductor substrate 802, rather than on the first combined substrate 804. Yet alternatively, respective layers of (same/different) dielectric material(s) may be formed on the first semiconductor substrate 802 and first combined substrate 804, and then the respective layers of dielectric material(s) are bonded together at step 852 (in the process of bonding the first semiconductor substrate 802 to the first combined substrate 804). Also, it is possible that a plurality of layers of different dielectric materials (and combinations thereof) may be formed on the first combined substrate 804, if desired.

[0067] At step 852 (i.e. FIG. 8b), the first semiconductor substrate 802 is bonded to the first combined substrate 804 via the layer of dielectric material 806 to form a second combined substrate 814. FIG. 9 shows an infrared (IR) image 900 of the plan-view of the second combined substrate 814 obtained from step 852. From a top-down perspective, the second combined substrate 814 is arranged with the following layers (in sequence): the first semiconductor substrate 802, the layer of dielectric material 806, the layer of III-V compound semiconductor 808, the germanium layer 810 and the second semiconductor substrate 812. After bonding, the second combined substrate 814 may optionally be annealed to further increase/enhance the bonding strength between the first semiconductor substrate 802 and the layer of dielectric material 806. The annealing is performed (for about three hours) using nitrogen (N.sub.2) at a temperature of about 300 C. and at ambient atmosphere pressure. Not limited to the above, other alternative suitable gases such as O.sub.2, H.sub.2, forming gas, He or Ar may also be used for the annealing, depending on requirements. For variant embodiments where the layer of dielectric material 806 is formed on the first semiconductor substrate 802, the annealing is carried out to increase the bonding strength between the layer of dielectric material 806 and the layer of III-V compound semiconductor 808.

[0068] It is also to be highlighted that optionally, subsequent to step 850 and prior to step 852, plasma cleaning (e.g. using oxygen plasma, hydrogen plasma, argon plasma, or nitrogen plasma) may be performed on the first semiconductor substrate 802, and first combined substrate 804 for about 15 seconds each, followed by washing the cleaned first semiconductor substrate 802, and first combined substrate 804 with a deionized fluid (e.g. deionized water), and finally drying (e.g. spin-drying) the washed first semiconductor substrate 802, and first combined substrate 804. These additional steps are taken to prepare the first semiconductor substrate 802, and first combined substrate 804 for the bonding at step 852.

[0069] Next at step 854 (i.e. FIG. 8c), the second combined substrate 814 is vertically inverted, so that the sequence of the layers of the second combined substrate 814 is now vertically reversed, from the top-down perspective. At further step 856 (i.e. FIG. 8d), the second semiconductor substrate 812 is removed from the second combined substrate 814 to expose at least a portion of the germanium layer 810 to obtain a third combined substrate 816. In this case, the entire top surface of the germanium layer 810 is exposed, and the top surface is arranged in opposition to the bottom surface of the germanium layer 810 that is adjacent to and in contact with the layer of III-V compound semiconductor 808. The second semiconductor substrate 812 is removed from the second combined substrate 814 by submerging the second combined substrate 814 in a solution of TMAH heated to about 80 C. for the removal. Upon completion, etch stopping is performed on the germanium layer 810. Alternatively, the second semiconductor substrate 812 may also be removed using a combination of mechanical grinding and wet etching.

[0070] It is to be appreciated that subsequent to step 854 and prior to step 856, a layer of protective material (not shown) (e.g. ProTEK B3-25, SiO.sub.2, SiN, or combinations thereof) may optionally be deposited on the first semiconductor substrate 802. Specifically, the protective material is spin coated on a first surface of the first semiconductor substrate 802, the first surface opposing a second surface (of the first semiconductor substrate 802) on which the dielectric material 806 is arranged adjacent, to act as a protection layer during the process of removing the second semiconductor substrate 812.

[0071] After the second semiconductor substrate 812 has been completely removed with no existence of bubbles observed, the coating of protective material is then removed from the first semiconductor substrate 802 using oxygen plasma configured with an operating power of about 800 W. Alternatively, the coating of protective material may also be removed using acetone. Then, at subsequent step 858 (i.e. FIG. 8e), the germanium layer 810 is removed from the third combined substrate 816, using (for example) a solution which includes 10% of hydrogen peroxide (H.sub.2O.sub.2), to obtain a fourth combined substrate 818. This then means that the entire top surface of the layer of III-V compound semiconductor 808 is now exposed, after the germanium layer 810 has been removed.

[0072] At step 860 (i.e. FIG. 8f), the fourth combined substrate 818 is annealed at a temperature about 250 C. to 1000 C. (for one or several cycles) to reduce threading dislocation density (TDD) of the layer of III-V compound semiconductor 808 to obtain the hybrid substrate 880. To clarify, the hybrid substrate 880 is the fourth combined substrate 818 that has undergone annealing. From a top-down perspective, the hybrid substrate 880 consists of: the layer of III-V compound semiconductor 808, the layer of dielectric material 806, and the first semiconductor substrate 802. It is to be appreciated that annealing is carried out using a gas selected from the group consisting of O.sub.2, H.sub.2, N.sub.2, forming gas, He and Ar. For the variant method 800, only steps 852, 856, 858, and 860 are needed as a bare minimum; the other steps are either optional or may not be performed as part of the method 800.

[0073] FIG. 10 is an X-SEM micrograph 1000 of a fabricated sample of the hybrid substrate 880 manufactured using the variant method 800. In this case, the layer of III-V compound semiconductor 808 is GaAs (e.g. 310 nm thick), and the layer of dielectric material 806 is SiO.sub.2 (e.g. 320 nm thick). FIG. 11 is a graph 1100 depicting HRXRD profiles measuring the FWHM of a GaAs/Ge/Si substrate, and a GaAs-OI substrate (before and after annealing). For FIG. 11, #1, #2 and #3 in the legend column respectively represent GaAs/Ge/Si, GaAs-OI before annealing, and GaAs-OI after annealing. The GaAs-OI substrate is the hybrid substrate 880 manufactured using the variant method 800, and OI is an abbreviation for on-insulator. Specifically, it is observed that the FWHM as measured has decreased from 180 arcsec to 155 arcsec (i.e. a reduction of about 15%) after annealing, as shown in FIG. 11. The decrease in the FWHM is due to the fact that a better improved crystal structure of the GaAs has more reflective planes. Also, the electron mobility measured by way of hall-effect has increased by 20% (i.e. from 900 cm.sup.2/V.Math.s to 1130 cm.sup.2/V.Math.s) compared to the as-grown GaAs/Ge/Si substrate. It is to be appreciated that all these improved material characteristics are achieved without need for a graded buffer, e.g. SiGe or lithography. Additional advantages enjoyed by the resulting GaAs-OI substrate as manufactured include having lower parasitic capacitance and lower electrical leakage characteristics.

[0074] FIG. 12 then depicts a graph 1200 of photoluminescence (PL) intensity measurement of the same GaAs/Ge/Si substrate and GaAs-OI substrate (before and after annealing). For FIG. 12, #1, #2 and #3 in the legend column respectively represent GaAs/Ge/Si, GaAs-OI before annealing, and GaAs-OI after annealing. It is observed that the PL intensity has increased by at least 2 times after annealing, which affirms that a better GaAs crystal quality is obtained after annealing.

[0075] With reference to the variant method 800, FIG. 13a is a first photograph 1300 showing EPD of a GaAs-OI substrate (mentioned in relevant text of FIG. 11) before annealing, which was measured to be about 210.sup.7/cm.sup.2. FIG. 13b is a second photograph 1310 showing EPD of the same GaAs-OI substrate after annealing, which was accordingly measured to be about 810.sup.5/cm.sup.2 showing that the EPD has been significantly reduced (i.e. improved crystal quality of the GaAs layer).

[0076] In summary, the proposed method 100, 800 discloses a way to improve the crystal quality of GaAs (or the like) through thermal cycling, or annealing. It is envisaged that similar mechanism is expected and so the method 100, 800 should be applicable also to improve the crystal quality of other III-As/P-based materials system, e.g. InGaAs, InP, InGaP, InGaAsP and etc. To briefly reiterate, the proposed method 100, 800 broadly requires bonding a GaAs/Si or a GaAs/Ge/Si donor substrate (i.e. if the layer of III-V compound semiconductor 108, 808 is GaAs in one case) to a Si handler substrate via at least one layer of dielectric material 106, 806, and then followed by releasing the Si donor substrate to form a GaAs-OI substrate (i.e. the hybrid substrate 180, 880). More specifically, the method 100, 800 allows the GaAs crystal to undergo re-crystallization at a sufficient high temperature, since the GaAs layer is not restricted by the donor substrate (which is Si in this case) anymore, after removal of the donor substrate.

[0077] It is to be appreciated the potential commercial applications for the hybrid substrate 180, 880 (obtained by means of the proposed method 100, 800) include usage as a base substrate for subsequent III-V materials growth (e.g. InGaAs, InP and etc), usage in silicon photonics (e.g. GaAs lasers and detectors), and usage as a higher mobility channel for advanced CMOS devices.

[0078] While the invention has been illustrated and described in detail in the drawings and foregoing description, such illustration and description are to be considered illustrative or exemplary, and not restrictive; the invention is not limited to the disclosed embodiments. Other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practising the claimed invention. For avoidance of doubt, the relative thicknesses of the different layers shown in FIGS. 1a to 1e, and FIGS. 8a to if are not to be construed as being representative of dimensions of the corresponding layers in actual samples that may be manufactured via the proposed method 100, 800 and have instead been drawn exaggerated for illustration purposes. Also, a one step/cycle annealing process may alternatively be adopted at step 158/860 for the annealing to be carried out.

[0079] Further, at step 150, the first combined substrate 104 may instead be provided above the first semiconductor substrate 102, and the vertical orientation of the first combined substrate 104 is such that the layers are now arranged as (from top to bottom sequentially): the second semiconductor substrate 110, the layer of III-V compound semiconductor 108, and the layer of dielectric material 106. With this, step 154 can be skipped, and the method progresses directly to step 156. To clarify, this is a matter of simply orientating the first combined substrate 104 and the first semiconductor substrate 102, and does not in any way affect performance of the disclosed method 100. The above said also applies similarly, mutatis mutandis, to step 850 of the second embodiment.