LOW DROPOUT REGULATOR

Abstract

A circuit for converting a first voltage to a second voltage in a communication system is disclosed. The circuit includes a pass transistor including a first terminal, a second terminal and a gate, wherein the first terminal is coupled with the first voltage. The circuit is also includes an error amplifier. The error amplifier includes a first input that is coupled with a constant reference voltage and a second input that is coupled with a first switch that is coupled with an output port. A second switch is included and is coupled between the first voltage and an output of the error amplifier. The output of the error amplifier is coupled with the gate of the pass transistor. A third switch is included and is coupled between ground and the output of the error amplifier. The second switch is configured to be driven by a first one shot pulse generated from an input signal of the communication system and the third switch is configured to be driven by a second one shot pulse generated from the input signal.

Claims

1. A circuit for converting a first voltage to a second voltage in a communication system, comprising: a pass transistor including a first terminal, a second terminal and a gate, wherein the first terminal is coupled with the first voltage; an error amplifier including a first input that is coupled with a constant reference voltage and a second input that is coupled with a first switch that is coupled with an output port; a second switch coupled between the first voltage and an output of the error amplifier, wherein the output of the error amplifier is coupled with the gate of the pass transistor; a third switch coupled between ground and the output of the error amplifier; and wherein the second switch is configured to be driven by a first one shot pulse generated from an input signal of the communication system and the third switch is configured to be driven by a second one shot pulse generated from the input signal.

2. The circuit of claim 1, wherein the constant reference voltage is generated by a bandgap reference voltage generator.

3. The circuit of claim 1, wherein a value of the constant reference voltage is equal to the second voltage.

4. The circuit of claim 1, wherein the first one shot pulse is generated at a rising edge of the input signal.

5. The circuit of claim 1, wherein the second one shot pulse is generated at a falling edge of the input signal.

6. The circuit of claim 1, wherein the first one shot pulse has a configurable width.

7. The circuit of claim 1, wherein the second one shot pulse has a configurable width.

8. The circuit of claim 6, wherein the second switch is configured to pull up a voltage at the gate of the pass transistor during the configurable width of the first one shot pulse.

9. The circuit of claim 7, wherein the second switch is configured to pull down a voltage at the gate of the pass transistor during the configurable width of the second one shot pulse by coupling the gate of the pass transistor to ground.

10. The circuit of claim 1, wherein the first one shot pulse is generated by a one shot pulse generator by inputting the input signal to the one shot pulse generator.

11. The circuit of claim 1, wherein the second one shot pulse is generated by a one shot pulse generator by inputting an inverse of the input signal to the one shot pulse generator.

12. The circuit of claim 1, wherein the first switch is driven by the input signal and is configured to connect or disconnect a load from the output port.

13. A method for converting a first voltage to a second voltage in a system, the method comprising: comparing an output voltage with a constant reference voltage using an error amplifier and generating a driving voltage to drive a pass transistor to bring the output voltage equal to the second voltage; generating a first one shot pulse from an input signal of the system; generating a second one shot pulse from the input signal of the system; pulling up the driving voltage during a width of the first one shot pulse; and pulling down the driving voltage during a width of the second one shot pulse.

14. The method of claim 13, wherein a value of the constant reference voltage is equal to the second voltage.

15. The method of claim 13, wherein the first one shot pulse is generated at a rising edge of the input signal.

16. The method of claim 13, wherein the second one shot pulse is generated at a falling edge of the input signal.

17. The method of claim 13, wherein the width of the first one shot pulse is configurable or programmable.

18. The method of claim 13, wherein the width of the second one shot pulse configurable or programmable.

19. The method of claim 13, wherein the width of the first one shot pulse is equal to the width of the second one shot pulse.

20. The method of claim 13, wherein the width of the second one shot pulse is different from the width of the second one shot pulse.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0007] FIG. 1 illustrates a bidirectional eUSB2/USB2 repeater including a capless low dropout (LDO) regulator in accordance with one or more embodiments of the present disclosure.

[0008] FIG. 2A illustrates the internal circuit of the capless LDO regulator in FIG. 1 in accordance with one or more embodiments of the present disclosure.

[0009] FIG. 2B shows an example of a one shot generator circuit to be used with the internal circuit of the LDO regulator of FIG. 2.

[0010] FIG. 3 shows the output characteristics of the capless LDO regulator of FIG. 2.

[0011] FIG. 4 illustrates another example of the internal circuit of the LDO regulator in FIG. 1 in accordance with one or more embodiments of the present disclosure.

[0012] Throughout the description, similar reference numbers may be used to identify similar elements.

DETAILED DESCRIPTION

[0013] It will be readily understood that the components of the embodiments as generally described herein and illustrated in the appended Figs. could be arranged and designed in a wide variety of different configurations. Thus, the following more detailed description of various embodiments, as represented in the Figs., is not intended to limit the scope of the present disclosure, but is merely representative of various embodiments. While the various aspects of the embodiments are presented in drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

[0014] The present invention may be embodied in other specific forms without departing from its spirit or essential characteristics. The described embodiments are to be considered in all respects only as illustrative and not restrictive. The scope of the invention is, therefore, indicated by the appended claims rather than by this detailed description. All changes which come within the meaning and range of equivalency of the claims are to be embraced within their scope.

[0015] Reference throughout this specification to features, advantages, or similar language does not imply that all of the features and advantages that may be realized with the present invention should be or are in any single embodiment of the invention. Rather, language referring to the features and advantages is understood to mean that a specific feature, advantage, or characteristic described in connection with an embodiment is included in at least one embodiment of the present invention. Thus, discussions of the features and advantages, and similar language, throughout this specification may, but do not necessarily, refer to the same embodiment.

[0016] Furthermore, the described features, advantages, and characteristics of the invention may be combined in any suitable manner in one or more embodiments. One skilled in the relevant art will recognize, in light of the description herein, that the invention can be practiced without one or more of the specific features or advantages of a particular embodiment. In other instances, additional features and advantages may be recognized in certain embodiments that may not be present in all embodiments of the invention.

[0017] Reference throughout this specification to “one embodiment”, “an embodiment”, or similar language means that a particular feature, structure, or characteristic described in connection with the indicated embodiment is included in at least one embodiment of the present invention. Thus, the phrases “in one embodiment”, “in an embodiment”, and similar language throughout this specification may, but do not necessarily, all refer to the same embodiment.

[0018] Traditional low dropout (LDO) regulators are simple to design and provide good regulated output, but are area consuming and usually need off-chip capacitors which increase the overall component count and need a dedicated pin. Capless LDO regulators are attractive due to their small area footprints and they don't require an off-chip capacitor. The embodiments described herein provide a capless LDO regulator which is suitable for a variable load of I.sub.MAX/I.sub.MIN (e.g., 10 mA/0 mA). The capless LDO regulator uses simple one-shot circuit with pull-up/pull-down switches to partially adjust output voltage variation during I.sub.MAX/I.sub.MIN transition. Typical LDO regulator generally use a feedback loop to sense the output voltage and are configured to adjust the output voltage through the feedback loop. However, the embodiments of a capless LDO regulator described herein do not use a feedback loop to adjust the output voltage. The capless LDO regulator uses a one-shot circuit for (that uses positive and negative edges of to be transmitted input signal) a quick adjustment of the output voltage when load changes by switching a pass transistor. It should be noted that even though the capless LDO regulator is described herein in the context of a eUSB2/USB2 repeater, the introduced capless LDO regulator may be used in other applications that requires a voltage conversion from a first voltage to a second voltage with a fast tracking of load changes.

[0019] FIG. 1 shows a block diagram of a bidirectional eUSB2/USB2 repeater 100 including a low dropout (LDO) regulator 200. The eUSB2/USB2 repeater 100 may be housed in a system on chip (SOC). In one example, the SoC provides two voltage sources V.sub.DD1 and V.sub.DD2. V.sub.DD1 may be 1.8V and V.sub.DD2 may be 3.3V. USB2 typically works on 3.3V and eUSB2 operates on 1.2V. If the SoC does not provide a 1.2V source, 1.2V needs to be generated for eUSB2. For efficiency reasons, 1.2V is generated from 1.8V source than 3.3V source.

[0020] The eUSB2/USB2 repeater 100 includes a eUSB2 port that outputs eD+/eD− signals and a USB2 port that outputs D+/D− signals. A logic block is coupled between the eUSB2 port and the USB2 port. The operations of these two ports and the switch are known to a person skilled in the art. A capless LDO 200 is included to convert V.sub.DD1 to a voltage different from V.sub.DD1. In this example, the capless LDO 200 may convert 1.8V to 1.2V. However, the capless LDO may also be used for converting other voltage values if needed. The capless LDO 200 provides advantages over a typical solution because the capless LDO does not require an additional external capacitor or large internal capacitor and the capless LDO provides a fast tracking of load changes so that the output signal's rise and fall time improves. The capless LDO 200 also removes a need for a 1.2V input port or pin.

[0021] FIG. 2A illustrates the internal circuit of the LDO regulator 200. The LDO regulator 200 includes an error amplifier 202 that receives a reference voltage Vref. Vref may be generated using a bandgap voltage reference circuit (not shown). A bandgap voltage reference is an on-chip reference with minimum variation. It produces a fixed (constant) voltage regardless of power supply variations, temperature changes, or circuit loading from a device (with some acceptable variation depending on the system requirement and design). Vref should be the same or substantially same to the required output voltage. For example, if the capless LDO regulator 200 is configured to convert 1.8V to 1.2V, Vref should be 1.2V. The capless LDO regulator 200 is configured to keep the output voltage equal to Vref. The load 204 may be a component external to the capless LDO regulator 200. The load has an impedance Z.sub.L that may include C.sub.L and R.sub.L. In the example of FIG. 1, the load 204 may be the eUSB2 port.

[0022] The capless LDO regulator 200 includes a pass transistor M that allows the current I.sub.L from a power source V.sub.DD to pass through it when it is conducting. The capless LDO regulator 200 converts V.sub.DD to V.sub.LDO. A (fairly small) capacitor C.sub.LDO coupled with the first terminal of the pass transistor M is included. The second terminal of the pass transistor M is coupled with the voltage source V.sub.DD. The other end of the capacitor C.sub.LDO is coupled with ground. V.sub.LDO represents the voltage at the first terminal of the pass transistor M. The rising and falling edges of V.sub.LDO should be rise and fall fast as close to the ideal square wave signal as possible. When S.sub.WL is enabled, the rising edge of the signal S.sub.L, the load Z.sub.LDO (e.g., the impedance of the capacitor C.sub.LDO in parallel with Z.sub.L=C.sub.L∥R.sub.L) sinks current from pass transistor of the LDO, but since Z.sub.L is small at the beginning (due to C.sub.L), V.sub.LDO drops and V.sub.G drops too. It takes some time for the OTA to adjust V.sub.G since it doesn't have enough juice to charge the effective cap at the gate of the pass transistor M.

[0023] The capless LDO regulator 200 includes a switch S.sub.WU coupled with a resistor R.sub.U at the output of the error amplifier 202. The switch S.sub.WU is controlled by a signal S.sub.U. The signal S.sub.U may be generated using a one shot circuit 250 shown in FIG. 2B. The one shot signal is generated from the input signal S.sub.L (the signal being transmitted) at the rising edge of the input signal. A one shot circuit is well known in the art, hence a detailed discussion is being omitted. A switch S.sub.WD is included and is coupled with a resistor RD. The switch S.sub.WD is driven by a signal S.sub.D. The signal S.sub.D is a one shot signal that is generated at the falling edge of the input signal, that is the inverse of the input signal may be inputted to the one shot circuit 250 to generate the signal S.sub.D. The resistor R.sub.D is coupled with the output of the error amplifier 202. The output of the error amplifier 202 provides the voltage V.sub.G to drive the gate of the pass transistor M. A switch S.sub.WL is included at the output of the capless LDO 200. The switch S.sub.WL is driven by the input signal S.sub.L. In one example, the switch S.sub.WU may be of type N or NMOS and the switch S.sub.WD may be of type P or PMOS. The switch S.sub.WU needs to be of different type (e.g., NMOS or PMOS) than the switch S.sub.WD.

[0024] The one shot signals S.sub.U and S.sub.D turns on the switches S.sub.WU and S.sub.WD at rising and falling edges respectively to lift V.sub.G that would otherwise fall during the rising and falling edges. This boost in V.sub.G at the rising and falling edges results in faster rising and falling edges of the output voltage V.sub.O. The switches S.sub.WU and S.sub.WD turns on only for the duration of the one shot pulse (which may be adjusted to adjust rising and falling edges slops), the current path including the switches S.sub.WU and S.sub.WD remains disconnected during the input signal pulse width other than for a period equal to the width of the one shot pulse at the rising and falling edges. Hence, the introduction of the current path including the switches S.sub.WU and S.sub.WD does not cause any significantly additional consumption of power.

[0025] The value of the resistor R.sub.U can be as close to 0 as possible to prevent the resistor R.sup.U from limiting the current flow significantly to prevent connecting V.sub.G to V.sub.DD. The value of R.sub.U may be calculated based on specific application requirement to achieve a desired output voltage characteristics (e.g., optimized rising and falling edges). In some examples, the value of R.sub.U may be programmable or trimmable so that the value of R.sub.U may be set or changed at run time. Similarly, to enable the error amplifier 202 to provide fast tracking of the input signal, the width of the one shot pulse may be programmable to allow an optimization of the output voltage characteristics at run time. At the falling edge of signal S.sub.L, the switch S.sub.WL will be shut down, then already flowing I.sub.L will see an impedance increase (C.sub.LDO∥Z.sub.L<C.sub.LDO, Z.sub.L is the impedance of the load 204) that causes V.sub.G and V.sub.LDO to spike for a short period of time. Practically, the error amplifier 202 is not fast enough to adjust V.sub.G. The S.sub.D signal that is generated by negative edge of the input signal S.sub.L, by the one-shot circuit 250 enables the switch S.sub.WD for the duration of the one shot pulse and pulls V.sub.G down to cause V.sub.LDO to drop until the error amplifier 202 reacts to the falling edge of the input signal S.sub.L. The resistor R.sub.D may be high enough to prevent connecting V.sub.G to ground during the falling edge. The use of one shot pulse to boost and pulldown V.sub.G during rising and falling edges respectively provides a significantly stable V.sub.O between load changes.

[0026] FIG. 3 shows the voltage-time waveforms 300 and output characteristics of the capless LDO regulator 200. As shown, at the rising edge of the input signal S.sub.L, a one shot pulse signal S.sub.U is generated using a one shot circuit which may be the one shot circuit 250 or any other type of known one shot pulse circuit. The one shot pulse has a configurable or programmable duration T.sub.wup. The switch S.sub.WU remains on during the duration T.sub.wup and that causes a boost in V.sub.G during the duration T.sub.wup. The boost in V.sub.G pulls up V.sub.LDO faster than it could rise without the one shot pulse. The faster pull up of V.sub.LDO causes the output voltage V.sub.O also rises faster (e.g., the curve 304) than it would have been without the signal S.sub.U (e.g., the curve 302). At the falling edge, the one shot pulse (e.g., the signal S.sub.D) is generated at the falling edge of the input signal S.sub.L. The falling edge one shot pulse has the configurable or programmable width T.sub.wdn. As explained above, the falling edge one shot pulse causes a faster pull down of the capacitor C.sub.LDO and as shown, thus causing the spike in V.sub.LDO to be smaller compared to the spike without the falling edge one shot pulse.

[0027] FIG. 4 illustrates an example implementation of the internal circuit of the capless LDO regulator 400. The capless LDO regulator 400 includes an error amplifier 402 and coupled with a load 406. The capless LDO regulator 400 functions the same manner as the capless LDO regulator 200. In one example, the switch S.sub.WU may be implemented using a PMOS transistor M.sub.P and the switch S.sub.WD may be implemented using a NMOS switch M.sub.N. And the switch S.sub.WL may be implemented using a transmitter driver 404 including at least two transistors of different types (e.g., NMOS and PMOS). The gates of the transistors of the transistor pairs are driven by the input signal S.sub.L (or an inverse of the input signal S.sub.L depending on the configuration of the differential transistor pair or the TX driver 404).

[0028] Although the operations of the method(s) herein are shown and described in a particular order, the order of the operations of each method may be altered so that certain operations may be performed in an inverse order or so that certain operations may be performed, at least in part, concurrently with other operations. In another embodiment, instructions or sub-operations of distinct operations may be implemented in an intermittent and/or alternating manner.

[0029] Although specific embodiments of the invention have been described and illustrated, the invention is not to be limited to the specific forms or arrangements of parts so described and illustrated. The scope of the invention is to be defined by the claims appended hereto and their equivalents.