SEMICONDUCTOR PACKAGE STRUCTURE, FABRICATING METHOD THEREOF, AND MEMORY SYSTEM

Abstract

The present disclosure provides a semiconductor package structure, a fabricating method thereof, and a memory system. The fabricating method comprises: providing an initial semiconductor package structure comprising: an initial substrate, a die device on the initial substrate and electrically connected with the initial substrate, and an initial package layer on the initial substrate and covers the die device; removing the initial substrate to obtain a die package device including the die device and at least a portion of the initial package layer; attaching a package substrate on the die device and electrically connecting the die device with the package substrate; and forming a first package layer on the package substrate to cover the die package device.

Claims

1. A method for fabricating a semiconductor package structure, comprising: providing an initial semiconductor package structure comprising: an initial substrate, a die device on the initial substrate and electrically connected with the initial substrate, and an initial package layer on the initial substrate and covers the die device; removing the initial substrate to obtain a die package device including the die device and at least a portion of the initial package layer; attaching a package substrate on the die device and electrically connecting the die device with the package substrate; and forming a first package layer on the package substrate to cover the die package device.

2. The method of claim 1, wherein: the die device is electrically connected with the initial substrate through first connection lines; removing the initial substrate comprises exposing at least portions of the first connection lines; electrically connecting the die device with the package substrate comprises connecting the exposed portions of the first connection lines with package substrate through second connection lines; and the first package layer covers the second connection lines.

3. The method of claim 1, wherein: the initial substrate is removed from a first side of the die package device; attaching the package substrate comprises attaching the package substrate to a second side of the die package device opposite to the first side.

4. The method of claim 1, wherein: the initial substrate is removed from a first side of the die package device; attaching the package substrate comprises attaching the package substrate to the first side of the die package device.

5. The method of claim 2, wherein: the initial semiconductor package structure further comprises a chip structure sandwiched between the initial substrate and the die device and electrically connected with the initial substrate; after the removing the initial substrate, the method further comprising removing the chip structure.

6. The method of claim 5, wherein: the chip structure comprises a chip and a first initial adhesive layer covering the chip and adhering the die device to the initial substrate and cladding the chip; removing the chip structure comprises removing the chip and at least portions of the first initial adhesive layer, such that a remaining portion of the first initial adhesive layer on the die device forms a residual adhesive layer.

7. The method of claim 6, further comprising: during a same process of removing the chip structure, removing at least portions of the initial package layer, such that a remaining portion of the initial package layer forms a second package layer.

8. The method of claim 7, further comprising: during a same process of removing the chip structure, removing portions of the first connection lines; wherein surfaces of the second package layer, the residual adhesive layer and the exposed portions of the first connection lines are coplanar.

9. The method of claim 2, wherein: the die device comprises a plurality of dies and a plurality of connection pads disposed on the plurality of dies; after attaching the package substrate to the die package device, the plurality of connection pads face the package substrate.

10. The method of claim 9, wherein: a vertical distance from a highest point of the second connection lines to the package substrate is greater than a thickness of the die package device in a stacking direction.

11. The method of claim 9, wherein the package substrate is connected with the die package device through a second adhesive layer.

12. A semiconductor package structure, comprising: a package substrate; a first package layer formed on the package substrate; and a die package device comprising a second package layer and a die device and in the package layer; wherein the first package layer completely covers the die package device, and the die device is electrically connected with the package substrate.

13. The semiconductor package structure of claim 12, further comprising: first connection lines embedded in the second package layer and electrically connected with the die device; and second connection lines electrically connected between the first connection lines and the package substrate.

14. The semiconductor package structure of claim 13, wherein the die device comprises: a plurality of dies stacked with each other by first adhesive layers; and a plurality of connection pads on each of the plurality of dies and electrically connected with the first connection lines.

15. The semiconductor package structure of claim 14, wherein: the plurality of connection pads face the package substrate; the second package layer is attached to package substrate by a second adhesive layer.

16. The semiconductor package structure of claim 15, further comprising: a residual adhesive layer on a first side of the die device away from the package substrate, and sandwiched between the first package layer and the die device.

17. The semiconductor package structure of claim 16, wherein: the second connection lines are embedded in the first package layer; the first connection lines and the second connection lines are connected with each other at an interface between the first package layer and the second package layer; and a vertical distance from a highest point of the second connection lines to the package substrate is greater than a thickness of the die package device in a stacking direction.

18. The semiconductor package structure of claim 14, further comprising: a residual adhesive layer on a second side of the die device adjacent to the package substrate; and a second adhesive layer sandwiched between the package substrate and the die device; wherein the residual adhesive layer is in contact with the adhesive layer.

19. The semiconductor package structure of claim 18, wherein: the second connection lines are embedded in the second adhesive layer; and the plurality of connection pads face away the package substrate.

20. A memory system, comprising: a memory device package structure, comprising: a package substrate; a first package layer formed on the package substrate; and a die package device comprising a second package layer and a memory device and in the package layer; wherein the first package layer completely covers the die package device, and the die device is electrically connected with the package substrate; and a controller configured to control the memory device package structure.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The drawings to be used in the description of implementations will be briefly introduced below in order to illustrate the technical solutions in some implementations of the present disclosure more clearly. Apparently, the drawings described below are only some implementations of the present disclosure. Those skilled in the art may also obtain other drawings according to these drawings without creative work.

[0029] FIG. 1 is a flow diagram of a fabricating method of a semiconductor package structure provided by implementations of the present disclosure.

[0030] FIGS. 2A and 2B are sectional views of two initial semiconductor package structures provided by some implementations of the present disclosure.

[0031] FIG. 3 is a sectional view after removing an initial substrate of an initial semiconductor package structure as shown in FIG. 2A.

[0032] FIG. 4 is a sectional view after obtaining a die package device by removing a chip of an initial semiconductor package structure as shown in FIG. 3 or removing an initial substrate as shown in FIG. 2B.

[0033] FIG. 5 is a sectional view of a die package device as shown in FIG. 4 after being flipped 1800.

[0034] FIG. 6A is a sectional view after forming a flipped die package device as shown in FIG. 5 on one side of a substrate.

[0035] FIG. 6B is a sectional view after forming a die package device as shown in FIG. 4 on one side of a substrate.

[0036] FIG. 7A is a sectional view of a semiconductor package structure obtained by forming a first package layer cladding a die package device on a substrate as shown in FIG. 6A.

[0037] FIG. 7B is a sectional view of a semiconductor package structure obtained by forming a first package layer cladding a die package device on a substrate as shown in FIG. 6B.

[0038] FIG. 8 is a module schematic diagram of a memory system provided by the present disclosure.

DETAILED DESCRIPTION

[0039] The technical solutions in some implementations of the present disclosure will be described below clearly and completely in conjunction with the drawings in some implementations of the present disclosure. Apparently, the implementations described are only a part of, but not all of the implementations of the present disclosure. All other implementations obtained by those skilled in the art based on the implementations in the present disclosure without creative work shall fall in the scope of protection of the present disclosure.

[0040] In the description of the present disclosure, it is to be understood that orientations or position relationships indicated by the terms upper, lower, etc. that are based on the orientations or position relationships as shown in the drawings, are only intended to facilitate description of the present disclosure and to simplify the description, instead of indicating or implying that the device or element indicated must have a specific orientation and be configured and operated in a specific orientation, and thus cannot be understood as limiting the present disclosure. Furthermore, the terms first and second are only for the purpose of description, and cannot be construed as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, features defined by first and second may explicitly or implicitly include one or more of the features. In the description of the present disclosure, a plurality of means two or more, unless otherwise specifically defined.

[0041] The present disclosure may repeat the reference numerals and/or reference letters in different implementations, and such repetitions are for the purpose of simplification and clarity, and do not indicate the relationships between various implementations and/or settings as discussed by themselves.

[0042] The present disclosure aims at the technical problem that initial semiconductor package structures returned in batches cannot be used on platforms of other clients. A new semiconductor package structure capable of being used on the platforms of the other clients may be formed by removing an initial substrate of the initial semiconductor package structure to obtain a die package device, then designing a new substrate capable of meeting demands of the other clients, forming the die package device on one side of package substrate and electrically connecting the die package device with the package substrate and fitting with the packaging process. As such, the batch reuse of the returned semiconductor package structure can be achieved.

[0043] With reference to FIGS. 1 to 7B, some implementations of the present disclosure provide a fabricating method of a semiconductor package structure 100, which comprises:

[0044] Step S1: with reference to FIGS. 1-2B, providing an initial semiconductor package structure 10 that comprises an initial substrate 11, a die device 12, and an initial package layer 13, wherein the die device 12 is located on one side of the initial substrate 11 and electrically connected with the initial substrate 11, and the initial package layer 13 is located on the initial substrate 11 and clads the die device 12.

[0045] Initial electrical connections 16 are further formed on the initial substrate 11, electrically connected with the initial substrate 11, and located on a side of the initial substrate 11 far away from the die device 12. The initial electrical connections 16 are used to electrically connect with external electronic components.

[0046] In the present disclosure, the initial substrate 11 may be either an ordinary carrier substrate, or a substrate with a circuit structure. When the initial substrate 11 is an ordinary carrier substrate, a lead frame to be externally connected with devices is needed on the carrier substrate in order to be electrically connected with the die device 12.

[0047] In some implementations of the present disclosure, the die device 12 comprises a plurality of dies 121 and a plurality of first adhesive layers 122 between two adjacent ones of the dies 121, wherein the first adhesive layers 122 are used to adhere two adjacent ones of the dies 121. The dies 121 and the first adhesive layers 122 are alternately stacked together, and a stacking direction of the dies 121 and the first adhesive layers 122 is consistent with a stacking direction of the initial substrate 11 and the die device 12. Two adjacent ones of the dies 121 are disposed in an interleaved manner, and one end of one of the two adjacent dies 121 protrudes out from one end of the other die 121.

[0048] In some implementations of the present disclosure, the die device 12 may also comprise only one die 121, and accordingly, the die device 12 does not comprise a first adhesive layer 122.

[0049] In some implementations of the present disclosure, there is a connection pad (not numbered in the figures) on each die 121, and surfaces of the dies 121 having the connection pads face away from the initial substrate 11. In other implementations, the surfaces of the dies 121 having the connection pads may also face the initial substrate 11; alternatively, the surfaces of a part of the dies 121 having the connection pads face away from the initial substrate 11, and the surfaces of the other part of the dies 121 having the connection pads face the initial substrate 11.

[0050] The die device 12 further comprises first connection lines 14, and is electrically connected with the initial substrate 11 through the first connection lines 14. In particular, the first connection lines 14 are electrically connected with the dies 121 at one end, and electrically connected with the initial substrate 11 at the other end.

[0051] In some implementations of the present disclosure, there are multiple first connection lines 14, and part of the dies 121 are connected in series through one first connection line 14, and then electrically connected with the dies being connected in series and the initial substrate 11 through another first connection line 14. The dies 121 being connected in series may be adjacent or may be nonadjacent. In this implementation, the dies 121 being connected in series are two adjacent dies. It is certain that, the number of the dies 121 being connected in series is not limited to two. The dies 121 being connected in series are defined as a set of dies, and then, there may be one or more sets of dies in one die device 12.

[0052] The initial package layer 13 clads the dies 121 and the first connection lines 14. In this implementation, the initial package layer 13 further clads the first adhesive layers 122.

[0053] The initial package layer 13 comprises a first side 132 far away from the initial substrate 11.

[0054] With reference to FIG. 2A, in some implementations of the present disclosure, the initial semiconductor package structure 10 further comprises a chip structure 15 that is located between the die device 12 and the initial substrate 11 and electrically connected with the initial substrate 11. The initial package layer 13 further clads the chip structure 15. The chip structure 15 comprises a chip 151, a first initial adhesive layer 152, third connection lines 153 and a second initial adhesive layer 154, wherein the second initial adhesive layer 154 is located on the initial substrate 11; the chip 151 is located on the second initial adhesive layer 154 and electrically connected with the initial substrate 11 through the third connection lines 153; and the first initial adhesive layer 152 is adhered to the die device 12 and the initial substrate 11 and clads the chip 151, the second initial adhesive layer 154 and the third connection lines 153. The first initial adhesive layer 152 is further adhered to the initial package layer 13.

[0055] In some implementations of the present disclosure, the chip 151 may be either a control chip, or other chip without a control function that is directly connected with the initial substrate 11.

[0056] With reference to FIG. 2B, in some implementations of the present disclosure, the initial semiconductor package structure 10 does not comprise the chip structure 15, and the die device 12 is directly connected onto the initial substrate 11 through the second initial adhesive layer 154.

[0057] Step S2: with reference to FIGS. 1 and 3 to 4, removing the initial substrate 11 to obtain a die package device 20.

[0058] The die package device 20 comprises a first side 132 and a second side 201 far away from the first side 132.

[0059] With reference to FIGS. 2A, 3 and 4, in some implementations of the present disclosure, since the initial semiconductor package structure 10 further comprises the chip structure 15, in Step S2, after removing the initial substrate 11, the fabricating method further comprises the step of: removing the chip structure 15.

[0060] The step of removing the chip structure 15 comprises: removing the chip 151, the second initial adhesive layer 154 and at least part of the first initial adhesive layer 152.

[0061] In this implementation, part of the first initial adhesive layer 152 is remained on the die package device 20, and the first initial adhesive layer 152 remained on the die package device 20 is a residual adhesive layer 17. In other implementations, the first initial adhesive layer 152 may also be removed completely.

[0062] A function of the residual adhesive layer 17 is to protect the dies 121 against wearing in a process of removing the chip structure 15 or removing the chip structure 15 and the initial substrate 11.

[0063] At the same time as removing the chip structure 15, the fabricating method further comprises: removing part of the initial package layer 13, wherein a remainder of the initial package layer 13 is a second package layer 131.

[0064] The second side 201 comprises a surface of the second package layer 131 far away from the first side 132 and a surface of the residual adhesive layer 17 far away from the first side 132.

[0065] In some implementations of the present disclosure, the surface of the second package layer 131 far away from the first side 132 is flush with the surface of the residual adhesive layer 17 far away from the first side 132. That is, the second side 201 is a plane.

[0066] At the same time as removing part of the initial package layer 13, the fabricating method further comprises the step of: removing part of the first connection lines 14.

[0067] The surfaces of the second package layer 131, the residual adhesive layer 17 and the first connection lines 14 far away from the first side 132 are flush.

[0068] With reference to FIG. 2B, in some other implementations of the present disclosure, the initial semiconductor package structure 30 is similar to the initial semiconductor package structure 10 in structure, except that the initial semiconductor package structure 30 does not comprise a chip structure 15. After removing the initial substrate 11, the chip structure 15 is not required to be removed, but part of the initial package layer 13 will be removed.

[0069] In some other implementations of the present disclosure, the chip structure 15, the initial substrate 11 and part of the initial package layer 13 are removed by a mechanical polishing process or a mechanical polishing process in conjunction with a wet or dry etching process.

[0070] Step S3: with reference to FIGS. 1 and 5 to 6B, providing a package substrate 19, forming the die package device 20 on one side of the package substrate 19, and electrically connecting the die package device 20 with the package substrate 19.

[0071] In particular, the die package device 20 is connected to a side of the package substrate 19 facing the die package device 20 through a second adhesive layer 21.

[0072] In some implementations of the present disclosure, the package substrate 19 may be either an ordinary carrier substrate, or a substrate with a circuit structure. When the package substrate 19 is an ordinary carrier substrate, a lead frame to be externally connected with devices is needed on the carrier substrate in order to be electrically connected with the die device 12.

[0073] With reference to FIGS. 1, 2A, 5 and 6A, in some implementations of the present disclosure, the step of forming the die package device 20 on one side of the package substrate 19, and electrically connecting the die package device 20 with the package substrate 19 comprises: firstly, with reference to FIG. 5, turning the die package device 20 upside down to enable the second side 201 of the die package device 20 to be far away from the package substrate 19; secondly, with reference to FIG. 6A, enabling the first side 132 of the die package device 20 to face the package substrate 19 and to be fixed on the package substrate 19; and thirdly, with reference to FIG. 6A, providing second connection lines 18 and electrically connecting two ends of the second connection lines 18 with the first connection lines 14 exposed from the second side 201 of the die package device 20 and the package substrate 19 respectively.

[0074] With reference to FIG. 6A, in some implementations of the present disclosure, the second side 201 of the die package device 20 faces the package substrate 19. Vertical distances from highest points of the second connection lines 18 to the package substrate 19 are greater than a thickness of the die package device 20 in a stacking direction. That is, lengths of the second connection lines 18 are greater than a vertical distance from a side of the die package device 20 far away from the package substrate 19 to the substrate, so that it can be avoided that the second connection lines 18 are easily detached from the first connection lines 14 due to the overtightened second connection lines 18, thereby ensuring connection firmness between the second connection lines 18 and the first connection lines 14.

[0075] In particular, the first connection lines 14 are connected with the connection pads of the die package device 20 at one end and connected with the second connection lines 18 at the other end. Accordingly, in this implementation, the connection pads of the die package device 20 face the package substrate 19.

[0076] With reference to FIGS. 1, 4 and 6B, in some other implementations of the present disclosure, at the step of forming the die package device 20 on one side of the package substrate 19, the die package device 20 may also be not turned upside down, and the die package device 20 is directly disposed on the package substrate 19 through the second adhesive layer 21, and at this point, the residual adhesive layer 17 is adhered to the second adhesive layer 21. Accordingly, the first side 132 of the die package device 20 faces the package substrate 19, and the lengths of the second connection lines 18 in FIG. 6B are shorter than the lengths of the second connection lines 18 in FIG. 6A.

[0077] Step S4: with reference to FIGS. 1, 7A and 7B, forming a first package layer 22 on the package substrate 19, and enabling the first package layer 22 to clad the die package device 20.

[0078] The first package layer 22 further clads the second connection lines 18 and the second adhesive layer 21 to protect the second connection lines 18 and improve connection firmness of the semiconductor package structure 100.

[0079] It is certain that, after Step S4, the fabricating method further comprises the step of: forming a plurality of package electrical connections 23 electrically connected with the package substrate 19 respectively on a side of the package substrate 19 far away from the die package device 20. The package electrical connections 23 may be or may not be protected by a protection layer.

[0080] It is certain that, after Step S4, the fabricating method may further comprise other steps for fabricating the semiconductor package structure, and these steps may be set according to actual situations, which is not repeated herein.

[0081] The fabricating method of the semiconductor package structure of the present disclosure can form a new semiconductor package structure capable of being used on the platforms of other clients by removing the initial substrate of the initial semiconductor package structure (the returned semiconductor package structure) to obtain the die package device, designing a new substrate capable of meeting demands of other clients, forming the die package device on one side of the package substrate and electrically connecting the die package device with the package substrate and fitting with the packaging process. As such, the batch reuse of the returned semiconductor package structure can be achieved.

[0082] With reference to FIG. 7A, some implementations of the present disclosure further provide a semiconductor package structure 100 that comprises a package substrate 19, a package layer 101 and a die package device 20, wherein the package layer 101 is formed on the package substrate 19, and the die package device 20 comprises a die device 12 and is embedded within the package layer 101. The package layer 101 completely clads the die package device 20; the die package device 20 and the package substrate 19 have part of the package layer 101 therebetween; and the die package device 20 is electrically connected with the package substrate 19.

[0083] In particular, the package layer 101 comprises a first package layer 22 and a second package layer 131; the die device 12 is embedded within the second package layer 131, and the die device 12 and the second package layer 131 are embedded within the first package layer 22.

[0084] In particular, the die device 12 comprises a plurality of dies 121 and a plurality of first adhesive layers 122 between two adjacent ones of the dies 121. The first adhesive layers 122 are used to adhere two adjacent ones of the dies 121. The dies 121 and the first adhesive layers 122 are alternately stacked together, and a stacking direction of the dies 121 and the first adhesive layers 122 is consistent with a stacking direction of the initial substrate 11 and the die device 12. Two adjacent ones of the dies 121 are disposed in an interleaved manner, and one end of one of the two adjacent dies 121 protrudes out from one end of the other die 121.

[0085] The die device 12 further comprises a residual adhesive layer 17 that is located on a side of one die 121 far away from the package substrate 19 that is the one farthest away from the package substrate 19; a surface of the residual adhesive layer 17 far away from the package substrate 19 is flush with a surface of the second package layer 131 far away from the package substrate 19; and the surface of the residual adhesive layer 17 far away from the package substrate 19 and the surface of the second package layer 131 far away from the package substrate 19 are in contact with the first package layer 22.

[0086] The die device 12 further comprises a first side 132 and a second side 201 far away from the first side 132. The first side 132 comprises a surface of the second package layer 131 far away from the residual adhesive layer 17, and the second side 201 comprises a surface of the second package layer 131 far away from the first side 132, and a surface of the residual adhesive layer 17 far away from the first side 132. The first side 132 of the die device 12 is in contact with the first package layer 22, and the second side 201 of the die device 12 and a surface of the first package layer 22 in contact with the package substrate 19 have a level difference therebetween.

[0087] In particular, the die package device 20 is connected to a side of the package substrate 19 facing the die package device 20 through a second adhesive layer 21. The second adhesive layer 21 is located in a space formed by the level difference between the second side 201 of the die device 12 and the surface of the first package layer 22 in contact with the package substrate 19.

[0088] In some implementations of the present disclosure, the die device 12 may also comprise only one die 121, and accordingly, the die device 12 does not comprise a first adhesive layer 122.

[0089] The die device 12 further comprises first connection lines 14 and second connection lines 18, and is electrically connected with the package substrate 19 through the first connection lines 14 and the second connection lines 18. In particular, the first connection lines 14 are electrically connected with the dies 121 at one end, and electrically connected with one end of the second connection lines 18 at the other end, and the other end of the second connection lines 18 is electrically connected with the package substrate 19.

[0090] In some implementations of the present disclosure, there are multiple first connection lines 14, and part of the dies 121 are connected in series through one first connection line 14, and then electrically connected with the dies being connected in series and the initial substrate 11 through another first connection line 14. The dies 121 being connected in series may be adjacent or may be nonadjacent. In this implementation, the dies 121 being connected in series are two adjacent dies. It is certain that, the number of the dies 121 being connected in series is not limited to two. The dies 121 being connected in series are defined as a set of dies, and then, there may be one or more sets of dies in one die device 12.

[0091] In some implementations of the present disclosure, the second side 201 of the die package device 20 faces the package substrate 19. Vertical distances from highest points of the second connection lines 18 to the package substrate 19 are greater than a thickness of the die package device 20 in a stacking direction. That is, lengths of the second connection lines 18 are greater than a vertical distance from a side of the die package device 20 far away from the package substrate 19 to the substrate, so that it can be avoided that the second connection lines 18 are easily detached from the first connection lines 14 due to the overtightened second connection lines 18, thereby ensuring connection firmness between the second connection lines 18 and the first connection lines 14.

[0092] In some implementations of the present disclosure, there is a connection pad (not numbered in the figures) on each die 121, and the first connection lines 14 are connected with the connection pads of the die package device 20 at one end and are connected with the second connection lines 18 at the other end. Accordingly, in this implementation, the connection pads of the die package device 20 face the package substrate 19. The first package layer 22 further clads the second connection lines 18 and the second adhesive layer 21 to protect the second connection lines 18 and improve connection firmness of the semiconductor package structure 100.

[0093] There are also a plurality of package electrical connections 23 electrically connected with the package substrate 19 on a side of the package substrate 19 far away from the die package device 20. The package electrical connections 23 may be or may not be protected by a protection layer. The package electrical connections 23 are used to externally connect with electronic components.

[0094] With reference to FIG. 7B, some implementations of the present disclosure further provide a semiconductor package structure 200 which is similar to the semiconductor package structure 100 in structure, except that: the second side 201 of the die package device 20 is in contact with the first package layer 22; the first side 132 of the die package device 20 is adhered together with the package substrate 19 through the second adhesive layer 21; the connection pads of the die package device 20 are located on a side of the dies 121 far away from the package substrate 19; the second adhesive layer 21 clads the second connection lines 18; and lengths of the second connection lines 18 in FIG. 7B are shorter than those of the second connection lines 18 in FIG. 7A.

[0095] With reference to FIG. 8, the present disclosure further provides a memory system 1000 which comprises one or more semiconductor package structures 100 or 200 as described above and a controller 300, wherein the controller 300 is located within or external to package layers 101 of the semiconductor package structures 100 or 200, and configured to control the semiconductor package structures 100 or 200.

[0096] When the controller 300 is located within the package layers 101 of the semiconductor package structures 100 or 200, the semiconductor package structures 100 or 200 may be considered as also having functions of the controller 300. When the controller 300 is located external to the package layers 101 of the semiconductor package structures 100 or 200, the semiconductor package structures 100 or 200 may be considered as not having functions of the controller 300, and are independent of the controller 300.

[0097] The memory system 1000 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a gaming console, a printer, a positioning apparatus, a wearable electronic apparatus, a smart sensor, a Virtual Reality (VR) apparatus, an Augmented Reality (AR) apparatus, or any other suitable electronic apparatuses having memories therein. The controller may be configured to control operations of the semiconductor package structures, such as reading, erasing, and programming operations.

[0098] In some implementations, the controller is designed for operating in a low duty-cycle environment such as Secure Digital (SD) cards, Compact Flash (CF) cards, Universal Serial Bus (USB) flash drives, or other media for use in electronic apparatuses, such as personal computers, digital cameras, mobile phones, etc.

[0099] In some implementations, the controller is designed for operating in high duty-cycle environment Solid-State Disks (SSDs) or Embedded Multi Media Cards (eMMCs) used as data memories for mobile apparatuses, such as smartphones, tablets, laptop computers, etc., and enterprise memory arrays.

[0100] According to the semiconductor package structure, the fabricating method thereof, and the memory system provided by the present disclosure, a new semiconductor package structure capable of being used on the platforms of other clients can be formed by removing the initial substrate of the initial semiconductor package structure (the returned semiconductor package structure) to obtain the die package device, designing a new substrate capable of meeting demands of the other clients, forming the die package device on one side of the package substrate and electrically connecting the die package device with the package substrate and fitting with the packaging process. As such, the batch reuse of the returned semiconductor package structure can be achieved.

[0101] To sum up, although the present disclosure has been disclosed as above with preferred implementations, the above preferred implementations are not used to limit the present disclosure. Those of ordinary skill in the art may make various changes and modifications without departing from the spirits and scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be defined by the claims.