System for the characterisation of a flash memory cell

Abstract

A system for characterising a NOR flash memory cell provided with a floating gate transistor, includes a voltage generator having an output connected to the gate electrode that generates as output an erase signal; and a dynamic measurement apparatus including a first channel connected to the gate electrode and a second channel connected to the drain electrode. The dynamic measurement apparatus generates on the first and second channels write signals and measures a current flowing in the drain electrode during the writing of the memory cell. Only the gate electrode of the floating gate transistor is connected to the voltage generator and to the dynamic measurement apparatus by a CMOS switch, which switches between a first position, where the output of the voltage generator is electrically coupled to the gate electrode, and a second position, where the first channel of the measurement device is electrically coupled to the gate electrode.

Claims

1. A system for characterising a NOR-type flash memory cell provided with a floating gate transistor, the floating gate transistor comprising a gate electrode and a drain electrode, the characterisation system comprising: a voltage generator including an output connected to the gate electrode and configured to generate as output an erase signal of the memory cell ; and a dynamic measurement apparatus comprising a first channel connected to the gate electrode and a second channel connected to the drain electrode, the dynamic measurement apparatus being configured to generate on the first and second channels write signals of the memory cell and to measure a current flowing in the drain electrode during the writing of the memory cell; wherein only the gate electrode of the floating gate transistor is connected to the voltage generator and to the dynamic measurement apparatus by the intermediary of a switch, the switch being of the CMOS type and able to switch between a first position, in which the output of the voltage generator is electrically coupled to the gate electrode, and a second position, in which the first channel of the dynamic measurement apparatus is electrically coupled to the gate electrode, and wherein the dynamic measurement apparatus is configured to generate a synchronisation signal transmitted to the voltage generator and to the switch in order to simultaneously control the generation of the erase signal and the switching of the switch to the first position.

2. The system according to claim 1, wherein the dynamic measurement apparatus is configured to generate on the first and second channels read signals of the memory cell and to measure the current flowing in the drain electrode during the read of the memory cell.

3. The system according to claim 1, wherein the second channel of the dynamic measurement apparatus is connected directly to the drain electrode of the floating gate transistor.

4. The system according to claim 1, wherein the dynamic measurement apparatus further comprises third and fourth channels connected respectively to a substrate of the floating gate transistor and to a source electrode of the floating gate transistor, the dynamic measurement apparatus being configured to measure currents in the substrate and in the source electrode.

Description

BRIEF DESCRIPTION OF THE FIGURES

(1) Other characteristics and benefits of the invention shall appear clearly in the description which is given of them hereinbelow, for the purposes of information and in no way limiting, in reference to the annexed figures, among which:

(2) FIG. 1, described hereinabove, shows the signals applied to the gate and drain electrodes of a floating gate transistor, in order to write, erase and read a NOR flash memory cell;

(3) FIG. 2, described hereinabove, is a graph of the endurance measurement of a flash memory cell, showing the change in the threshold voltage of the floating gate transistor in the written state and in the erased state;

(4) FIG. 3, described hereinabove, shows a first characterisation system of a flash memory cell according to prior art;

(5) FIG. 4, described hereinabove, shows a second characterisation system of a flash memory cell according to prior art;

(6) FIGS. 5A and 5B, described hereinabove, show two endurance sequences implemented by the characterisation system of FIG. 4;

(7) FIG. 6 schematically shows a characterisation system of a NOR flash memory cell, according to an embodiment of the invention;

(8) FIGS. 7A and 7B are chronograms of the signals used in the characterisation system of FIG. 6, in order to perform the write, erase and read operations of the memory cell;

(9) FIG. 8 shows an optimum endurance measurement that can be implemented thanks to the characterisation system of FIG. 6;

(10) FIG. 9 is a flowchart of a software that allows to control the characterisation system of FIG. 6; and

(11) FIGS. 10A and 10B are examples of curves obtained thanks to the characterisation system of FIG. 6.

(12) For increased clarity, identical or similar elements are marked by identical reference signs over all of the figures.

DETAILED DESCRIPTION

(13) FIG. 6 shows an embodiment of a characterisation system allowing to accurately measure the endurance of an EEPROM-Flash memory cell (commonly called a flash memory), of the NOR type. The cell comprises a NMOS floating gate transistor 30 provided with four electrodes: the control gate G, the drain D, the source S and the bulk B (the floating gate and the conduction channel do not form control electrodes of the transistor 30). The storage of the information is based on the trapping of electrical charges in the floating gate, which causes a variation in the threshold voltage of the transistor between the written state (or programed state) and the erased state of the memory cell.

(14) This characterisation system comprises a dynamic measurement apparatus 34, commonly referred to as PIV (Pulsed I(V) system) or FMU (Fast Measurement Unit), making it possible to generate voltages between 10 V and 10 V and to simultaneously measure currents. Mention can be made by way of example of the model FMU B1530 sold by Agilent Technology or the model PIV 4225-RPM sold by Keithley Instruments.

(15) The dynamic measurement apparatus 34 is provided with two main channels ch1-ch2 and a secondary channel trig. The channel ch1 is connected to the gate electrode G of the floating gate transistor 30, by the intermediary of a switch 60 of the CMOS type, while the channel ch2 is connected to the drain electrode D of the transistor 30.

(16) The apparatus 34 is configured to generate on the channels ch1-ch2 signals allowing to write to the NOR-type memory cell, and more exactly: on the channel ch1 (i.e. to bias the gate electrode G), a voltage pulse with amplitude between 6 V and 10 V during a duration between 1 s and 10 s; and on the channel ch2 (i.e. to bias the drain electrode D), a voltage pulse with amplitude between 3 V and 5 V for a duration between 1 s and 10 s.

(17) In other terms, the apparatus 34 is programed to control the write operations of the memory cell, by suitably biasing the electrodes G and D of the transistor 30.

(18) The apparatus 34 is furthermore capable of dynamically measuring the current I.sub.D flowing in the drain electrode D (and in the channel ch2), called drain current hereinafter, during a write operation. A dynamic measurement of the current is taken at a sampling frequency that is much higher that a so-called static measurement (or DC). In an embodiment, the period of time that separates two samplings of the drain current I.sub.D is between 1 ns and 100 ns, for example 10 ns. For the purposes of comparison, the sampling period in a static measurement is about several tens of milliseconds. The apparatus 34 thus allows for a reliable measurement of the write current, from which stems in particular the calculation of the electrical power consumption. Indeed, using the measurement of the drain current I.sub.D and knowing the voltage V.sub.D applied on the drain by means of the channel ch2, it is possible to calculate the energy E.sub.C consumed by the memory cell when it is written to, thanks to the following relationship:
E.sub.C=.sub.t=0.sup.t=tpV.sub.D(t).Math.I.sub.D(t).Math.dt(1)

(19) where tp is the write time, i.e. the shortest duration between the pulses on the electrodes G and D (between 1 s and 10 s).

(20) In an embodiment, the drain electrode D is connected directly to the dynamic measurement apparatus 34, i.e. no device is arranged between the electrode D and the channel ch2. Thus, nothing can disturb the dynamic measurement of the drain current taken by the apparatus 34.

(21) The characterisation system of FIG. 6 further comprises a voltage generator 31, whose the only output used ch0 is connected to the gate electrode G of the transistor 30 by the intermediary of the CMOS switch 60. This generator 31 is capable of providing as output ch0 voltages between 20V and +20 V. Furthermore, it operation can be controlled by an external signal. To this effect, it has a control input, generally designated as trigger in the off-the-shelf apparatuses. The pulse and sequence generator Agilent 81110A sold by Agilent Technology is an example of a voltage generator that can be used in the characterisation system.

(22) The voltage generator 31 is configured to deliver on the output ch0 an erase signal of the memory cell, which is a voltage pulse with amplitude between 10 V and 20 V for a duration between 1 ms and 200 ms. This pulse is applied on the gate electrode G of the transistor 30, when the CMOS switch 60 is in the suitable configuration.

(23) The CMOS switch 60 can indeed switch between a first position, in which the output ch0 of the generator 31 is electrically coupled to the gate electrode G, and a second position, wherein the channel ch1 of the apparatus 34 is electrically coupled to the electrode G. The switch 60 therefore makes it possible to pass from an erase operation to a write operation, and vice versa. It comprises one or several MOSFET transistors capable of withstanding voltages of at least 20 V in amplitude. Its switching time is, in an embodiment, less than 100 ns. By way of example, the switch 60 of FIG. 6 is an analogue CMOS switch sold by Maxim under reference MAX333A.

(24) In addition to being fast, the switching of the switch 60 between the first and second positions is carried out in synchronisation with the operation of the voltage generator 31, thanks to a synchronisation signal coming from the channel trig of the apparatus 34. This synchronisation signal is directed as input trigger in of the generator 31 on the one hand, and on a control input Cmd of the CMOS switch 60 on the other hand. It controls the turning on and the standby mode of the generator 31, at the same time as the switching of the switch 60 between the first and second positions.

(25) FIG. 7A groups together chronograms corresponding to the signals on the channels ch1-ch2 of the dynamic measurement apparatus (PIV), of the signal at output ch0 of the voltage generator (GEN) and of the synchronisation signal on the secondary channel trig of the dynamic measurement apparatus. On the left are shown the chronograms during a write operation and on the right are shown the chronograms during an erase operation of the memory cell of the NOR type. For reasons of clarity, the signals are designated hereinafter by using the references of the channels/outputs from which they come.

(26) The signals ch0 and ch1 are addressed alternating to the gate electrode G, while the signal ch2 is sent to the drain electrode D. The trig signal is sent simultaneously to the control input Cmd of the switch 60 and to the input trigger in of the generator 31.

(27) The synchronisation signal trig becomes active (for example V=5V) when it is desired to erase the memory cell, for example immediately after a write operation during an endurance measurement. The active state of the synchronisation signal trig triggers the establishment of an erase pulse 70 as output ch0 of the generator 31. The floating gate transistor 30 being of the NMOS type, the voltage pulse 70 is negative, typically between 10 V and 20 V. Simultaneously, the CMOS switch 60 is switched to the first position. The output ch0 is then electrically connected to the electrode G in order to apply thereon the pulse 70, while the channel ch1 is decoupled from this same electrode G. Then, the signal ch1 can be of any, for example a zero voltage such as is shown in FIG. 7A. The signal ch2, coming from the dynamic measurement apparatus PIV and applied on the drain electrode D, is a zero voltage during the erase operation. The erase pulse 70 ends shortly before the trig signal passes from the active state to the inactive state (for example 0 V). When the trig signal becomes inactive, the generator 31 is placed on standby until the next activation of the trig signal, i.e. until the next erase operation, and the switch 60 is switched to the second position, where the channel ch1 is coupled to the electrode G (as a replacement for the channel ch0).

(28) The dynamic measurement apparatus PIV then takes the relay for the voltage generator GEN and alone controls the write operation of the memory cell. During this write, the signals trig and ch0 are inactive. On the other hand, a pulse 71 of short duration and of high amplitude (between 7-10 V) is generated by the measurement device PIV on its channel ch1, intended for the gate electrode G. Furthermore, a pulse 72 of lower amplitude (3-5 V) comes from its channel ch2 and transmitted to the drain electrode D. The pulses 71 and 72 are positive, as the transistor 30 is of the NMOS type. In an embodiment, the pulse of the drain 72 starts before and finishes after the gate pulse 71, so that the bias of the drain D is well established when the pulse 71 is applied on the gate G. Consequently, it has a longer duration than the gate pulse 71. By way of example, the pulse 72 lasts about 2 s, while the pulse 71 only last about 1 s.

(29) In an embodiment, the channel trigger of the apparatus PIV is synchronised to the nearest 5 ns with the first of the channels ch1-ch2, i.e. the channel ch2 in the embodiment implemented of FIG. 7A. In other terms, the time between the deactivating of the signal trigger and the activating of the signal ch2 (erase=>write), or the deactivating of the write signal ch2 and the activating of the trigger signal (write=>erase), is at most 5 ns.

(30) Thus, contrary to the characterisation systems of prior art, the control signal of the switch, allowing for the transition between writing and erasing, is not the result of a computer command. It is here generated by the dynamic measurement apparatus and transmitted directly to the voltage generator, which guarantees an excellent synchronisation between these two pieces of equipment.

(31) In addition to the dynamic write, which corresponds to a conventional write operation combined with a dynamic measurement of the write current, the dynamic measurement apparatus 34 of FIG. 6 can control a read operation of the memory cell. This read is accomplished without making use of the voltage generator 31. The CMOS switch 60 is therefore placed in its second position, so that the channel ch1 of the apparatus 34 is coupled to the gate electrode C.

(32) FIG. 7B groups together, in the same way as FIG. 7A, the chronograms of the signals trig, ch0 to ch2 during the read of the memory cell. The signals trig and ch0 are inactive (0 V). The signal ch1 applied on the gate electrode G is a voltage ramp 73, starting from 0 V and reaching about 10 V at the end of a read time t.sub.L between 10 s and 100 is. During the voltage ramp 73, the signal ch2 biases the drain D at a voltage of about 0.5 V.

(33) The apparatus 34, in an embodiment, measures the drain current I.sub.D during the read of the memory cell. This allows to extract the threshold voltage of the floating gate transistor 30, by tracing the current-voltage characteristic I.sub.D(V.sub.G), V.sub.G being the voltage applied on the gate G, and therefore to determine the state of the memory cell. As the read operation is controlled by the apparatus 34 only, it can be carried out in a very short lapse of time (10-100 s). Any distortion in the measurement of the read current is thus overcome.

(34) FIG. 8 shows an embodiment for measuring the endurance by the characterisation system of FIG. 6. This endurance measurement is comprised of erase-dynamic write cycles C1, and of erase-dynamic write cycles C2 in which read operations have been introduced. Each cycle C1 allows to establish a current characteristic I.sub.D(t) of the floating gate transistor and therefore to calculate the energy consumed by the memory cell during the write operation of the cycle. A monitoring of the electrical consumption as cycles C1 unfold, i.e. during the ageing of the memory cell, can therefore be carried out thanks to the characterisation system. Each cycle C2 allows for the establishment of a current-voltage characteristic I.sub.D (V.sub.G) and the determination of the voltage thresholds V.sub.T in the erased state (read after erase) and in the written state (read after write).

(35) Contrary to the characterisation systems of prior art, the various operations in the measuring of endurance can be chained together without any waiting time. This is made possible thanks to the fact that a CMOS switch synchronised with the operation of the voltage generator is used, in order to switch between erase and dynamic write or between erase and read, and thanks to the fact that the read is performed with the same equipment as the dynamic write (with regards to the read dynamic write transition). Thus, it is now possible to prevent the relaxation of the memory cell between two successive operations of the endurance measurement, regardless of what these operations are. The endurance measurement hence reflects the ageing of the memory cell with more fidelity.

(36) The characterisation system of FIG. 6 offers the possibility of studying the impact of a relaxation of the memory cell between the write and erase operations on the reliability of the memory cell. Indeed, a period of time in which the duration is controlledcontrary to the period of time DL of FIGS. 5A and 5Bcan be introduced voluntarily between these two operations, by adapting the synchronisation signal of the dynamic measurement apparatus 34.

(37) During the dynamic write, erase and read operations hereinabove, the source electrode S and the bulk B of the floating gate transistor 30 can both be connected to the ground. Indeed, the voltage needed on each of these electrodes is zero.

(38) However, in the embodiment of FIG. 6, the dynamic measurement apparatus 34 is provided with two other main channels ch3 and ch4, connected respectively to the source electrode S and to the bulk B of the transistor 30. The channels ch3 and ch4 allows to bias at a zero voltage the electrodes S and B and, simultaneously, to dynamically measure the currents of the source S and of the bulk B. Measurement of the source and/or bulk current is of great use in studying the mechanisms of ionisation by impact in the channel of the transistor. Indeed, this ionisation generates electron-hole pairs which are dissociated under the effect of the electric field in the channel, with the holes being recovered by the bulk B. Like the drain electrode D, the electrodes S and B are, in an embodiment, connected directly to the measurement device 34, so that the current measurements are not disturbed by any device.

(39) Like the characterisation system shown in FIG. 4, the connections on the bulk and the source make it possible to study other write (ex. application of a non-zero bias on the bulk B during a conventional write) or read (ex. measurement of the source current according to the gate voltage V.sub.G) mechanisms.

(40) Although it is schematically shown by a single element in FIG. 6, it is easily understood that the apparatus 34 can be comprised of two modules that each have two main channels, with these modules being interconnected in order to operate simultaneously.

(41) FIG. 9 is a flowchart, or execution diagram, of a program implemented by computer in order to control the characterisation system of FIG. 6. In an embodiment, the computer includes a physical memory and a physical processor. The physical memory includes hardware circuit components to perform its functions. The memory is encoded with code instructions for implementing or causing to implement, via the processor, the different steps of the flowchart explained below.

(42) This program displays on the computer a user interface that requires, during a step F1, the entry of parameters by the user. The parameters to be entered can concern conditions for writing, erasing and reading (such as the duration of the operations and the corresponding voltage level), measurement calibres (for example 1 A, 100 A, 10 mA) and/or endurance parameters (number of write/erase cycles, number and position of the read operations, any delays between the write and erase operations, etc.).

(43) Once the parameters are entered, the computer calculates during a step F2 the chronograms of the signals of the dynamic measurement apparatus PIV and of the voltage generator GEN, at least the chronograms of the signals ch0, ch1, ch2 and trig (cf. FIG. 7A-7B).

(44) These chronograms are then converted into instructions that can be executed by the dynamic measurement apparatus and by the voltage generator, during a step F3. These instructions define the configuration of the two pieces of equipment needed to correctly perform the endurance measurement desired by the user.

(45) Then, in F4 and F4, this configuration is loaded into each piece of equipment, the dynamic measurement apparatus PIV and the voltage generator GEN respectively.

(46) During a step F5, the computer triggers the execution of instructions stored in the apparatus PIV. This has for effect to initiate the endurance measurement. The voltage generator GEN is not controlled by the computer during the measurement of endurance, but by the apparatus PIV thanks to the synchronisation signal. Once the sequence of cycles is initiated, the endurance measurement is conducted by the apparatus PTV only and the characterisation system is autonomous.

(47) As soon as the endurance measurement is completed, data is extracted from the apparatus PIV by the computer and displayed for the user, during a step F6. In an embodiment, this data includes: a set of current characteristics I.sub.D(t), each characteristic I.sub.D(t) corresponding to the plot of the drain current during a write operation, after a variable number of write/erase cycles; and beneficially, a set of characteristics I.sub.D(V.sub.G), with each characteristic I.sub.D(V.sub.G) corresponding to a read operation during which the drain current I.sub.D is measured according to the voltage V.sub.G.

(48) FIG. 10A is a graph that shows a plurality of current characteristics I.sub.D(t). Five characteristics are shown, after respectively 1, 10, 100, 1,000 and 10,000 write and erase cycles. The drain current I.sub.D (represented on the y-axis on the right) is expressed as a relative value, from 0 to 1 (without a unit). The write time (on the x-axis) is the same for all of the cycles. Moreover, the voltage V.sub.G applied on the gate during write operations (y-axis scale on the left) was superposed on these characteristics I.sub.D(t). The voltage pulse V.sub.G has a duration of about 3 s.

(49) It is observed on this graph the increase in the drain current I.sub.D as the number of write and erase cycles increases, which is representative of the ageing of the memory cell.

(50) Each characteristic I.sub.D(t) allows to determine the energy E.sub.C consumed by the cell during a write operation, by calculating (cf. relation (1) hereinabove) the integral of the current I.sub.D(t) multiplied by the voltage V.sub.D (with the latter being constant during the write operation). The change in the electrical power consumption of the memory cell can thus be monitored all throughout its ageing. The graph of FIG. 10B is an example of a plot showing that this energy consumed E.sub.C increases as the write and erase cycles occur.

(51) The characteristics I.sub.D(t) further allows to monitor the changes in the threshold voltage V.sub.T(t) during the write operation, from the erased state at t1.5 ps to the written state at t4.5 s. The threshold voltage values of the transistor in the erased state and in the written state can be calculated using values of the drain current (respectively at t4.5 s and t4.5 s).

(52) It is therefore not required to read the characteristic I.sub.D(V.sub.G), and therefore to proceed with reads of the memory cell, in order to follow the change in the voltage thresholds of the floating gate transistor. The endurance measurement could consequently be comprised solely of dynamic write and erase cycles C1.

(53) It nevertheless remains beneficial to perform read operations of the memory cell as they provide the user with parameters other than the threshold voltage, in particular the mobility of the charge carriers and the concentrations in traps in the gate oxide and at the interface between the gate oxide and the bulk. Indeed, these various parameters can be extracted from the characteristics I.sub.D(V.sub.G).