Semiconductor device and method of manufacturing semiconductor device

Abstract

An active region through which current flows in a semiconductor device includes an n.sup.-type silicon carbide epitaxial layer formed on a front surface of an n.sup.+-type silicon carbide semiconductor substrate; a p-type layer becoming a channel region; a trench formed so as to be in contact with a p-type layer and having an oxide film and a gate electrode embedded therein; a p.sup.+-type layer arranged beneath the trench and between trenches; an n.sup.-type layer in contact with the p-type layer, a p.sup.+-type layer, and the trench, and arranged in contact with a p.sup.+-type layer or on a surface side of the semiconductor substrate; an n-type layer in contact with the n.sup.-type silicon carbide epitaxial layer and the p.sup.+-type layer, and having an impurity concentration higher than that of the n.sup.-type layer and that of the n.sup.-type silicon carbide epitaxial layer.

Claims

1. A semiconductor device having an active region through which current flows, the semiconductor device comprising in the active region: a semiconductor substrate of a first conductivity type; a first first-conductivity-type semiconductor layer formed on a front surface of the semiconductor substrate, the first first-conductivity-type semiconductor layer having a concentration lower than that of the semiconductor substrate; a second first-conductivity-type semiconductor layer located above the first first-conductivity-type semiconductor layer; a third first-conductivity-type semiconductor layer located between the first first-conductivity-type semiconductor layer and the second first-conductivity-type semiconductor layer, the third first-conductivity-type semiconductor layer having an impurity concentration higher than that of second first-conductivity-type semiconductor layer and that of first first-conductivity-type semiconductor layer, and the third first-conductivity-type semiconductor layer being in contact with the second first-conductivity-type semiconductor layer and the first first-conductivity-type semiconductor layer; a channel region of a second conductivity type located above the second first-conductivity-type semiconductor layer, contacting a surface of the second first-conductivity-type semiconductor layer opposite the third first-conductivity-type semiconductor layer; a plurality of trenches extending through channel region and the second first-conductivity-type semiconductor layer, the trenches having an oxide film and a gate electrode embedded therein; a plurality of first second-conductivity-type semiconductor regions, including at least one first second-conductivity-type semiconductor region arranged beneath one of the plurality of trenches, and at least another of the first second-conductivity-type semiconductor regions arranged between adjacent trenches of the plurality of trenches, the plurality of first second-conductivity-type semiconductor regions formed in the third first-conductivity-type semiconductor layer; and a second second-conductivity-type semiconductor region formed in the second first-conductivity-type semiconductor layer and contacting the at least another first second-conductivity-type semiconductor region located between the adjacent trenches of the plurality of trenches, wherein the second first-conductivity-type semiconductor layer is in contact with the channel region, the second second-conductivity-type semiconductor layer, and the plurality of trenches.

2. The semiconductor device according to claim 1, wherein the second first-conductivity-type semiconductor layer has an impurity concentration that is less than 1.0 times, and equal to or greater than 0.5 times, that of the third first-conductivity-type semiconductor layer.

3. The semiconductor device according to claim 1, wherein the plurality of first second-conductivity-type semiconductor regions and the second second-conductivity-type semiconductor region have a same impurity concentration.

4. A method of manufacturing a semiconductor device having an active region through which current flows, the method comprising: forming a first first-conductivity-type semiconductor layer in the active region on a front surface of a semiconductor substrate of a first conductivity type, the first first-conductivity-type semiconductor layer having a concentration lower than that of the semiconductor substrate; forming a third first-conductivity-type semiconductor layer on a front surface of the first first-conductivity-type semiconductor layer, the third first-conductivity-type semiconductor layer having an impurity concentration higher than that of the first first-conductivity-type semiconductor layer; forming a plurality of first second-conductivity-type semiconductor layers in the third first-conductivity-type semiconductor layer; forming a second first-conductivity-type semiconductor layer on a front surface of the third first-conductivity-type semiconductor layer, the second first-conductivity-type semiconductor layer having an impurity concentration lower than that of the third first-conductivity-type semiconductor layer; forming a second second-conductivity-type semiconductor layer in the second first-conductivity-type semiconductor layer so as to contact a first second-conductivity-type semiconductor layer of the plurality of first second-conductivity-type semiconductor layers; forming a channel region of a second conductivity type on a front surface of the second first-conductivity-type semiconductor layer; and forming a trench so as to be in contact with the channel region and have a depth reaching at least one of the plurality of first second-conductivity-type semiconductor layers, the trench having an oxide film and gate electrode embedded therein.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a cross-sectional view of an active region of a trench-type MOSFET according to an embodiment of the present invention;

(2) FIG. 2 is a graph depicting the relationship of an impurity concentration ratio of a two-layer n-type CSL and DIBL, and parasitic resistance;

(3) FIGS. 3, 4, 5, 6, and 7 are cross-sectional views of the state of the active region of the silicon carbide semiconductor device according to the embodiment during manufacture;

(4) FIGS. 8 and 9 are cross-sectional views of an example of an edge termination structure region of the semiconductor device; and

(5) FIG. 10 is a cross-sectional view of an active region of a conventional trench-type MOSFET.

DETAILED DESCRIPTION OF THE INVENTION

(6) Embodiments of a semiconductor device and a method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings. In the present description and accompanying drawings, layers and regions prefixed with n or p mean that majority carriers are electrons or holes. Additionally, + or appended to n or p means that the impurity concentration is higher or lower, respectively, than layers and regions without + or . When the notations of n and/or p including + or are the same, this indicates that the concentrations are close, but does not necessarily mean that the concentrations are equal. In the description of the embodiments below and the accompanying drawings, main portions that are identical will be given the same reference numerals and will not be repeatedly described. Further, in the present description, when Miller indices are described, means a bar added to an index immediately after the , and a negative index is expressed by prefixing to the index.

(7) The semiconductor device according to the present invention uses a wide bandgap semiconductor. In an embodiment, a MOSFET will be described as an example of a silicon carbide semiconductor device produced using, for example, silicon carbide (SiC) as a wide bandgap semiconductor. Hereinafter, a structure of the active region according to the embodiment will be described taking an example in which a first conductivity type is assumed as an n-type and a second conductivity type is assumed as a p-type.

(8) FIG. 1 is a cross-sectional view of the active region of a trench-type MOSFET according to the embodiment of the present invention. In the embodiment, mainly, by reducing the impurity concentration of an n-type CSL layer (n-type layer) 15 (15a, 15b) (FIG. 7) in contact with a p-type base region 3 (3a, 3b) (FIG. 7), a threshold value decrease originating from a short channel effect called drain induced-barrier lowering (DIBL) is suppressed, in an ON state.

(9) As shown in FIG. 1, an n.sup.-type silicon carbide epitaxial layer (wide bandgap semiconductor deposition layer) 1 (also referred to as a first first-conductivity-type semiconductor layer) is stacked on a first main surface, e.g., a (0001) face (Si face), of an n.sup.+-type silicon carbide substrate (wide bandgap semiconductor substrate) 2. On the first main surface of the n.sup.-type silicon carbide epitaxial layer 1, plural p.sup.+-type base regions 3a and 3b are formed.

(10) On the first main surface (front surface) side of the n.sup.-type silicon carbide epitaxial layer, a p-type channel region 16 and an n.sup.+-type source region 17 are formed. Further, plural trenches 19 are formed and a gate electrode 20 of poly-silicon is embedded in each trench 19. Further, on the first main surface (front surface) of the n.sup.-type silicon carbide epitaxial layer 1, a field insulating film 21 and a source electrode 22 are formed.

(11) When the impurity concentration of the n-type layer 15 is lowered, a depletion layer from a p-type layer spreads easily, blocking the current path whereby the ON resistance of the trench-type MOSFET suddenly increases. To prevent this, the n-type layer (CSL layer) 15 (15a, 15b)(FIG. 7) is provided having a two-layer structure in a height direction contacting a second semiconductor region (p.sup.+-type regions 3a, 3b) of the second conductivity type. The n-type layer (CSL layer) 15 has a lowered impurity concentration in an n.sup.-type layer (also referred to as a second CSL layer, or as a second first-conductivity-type semiconductor layer) 15b in proximity to a channel p-type layer 16 having greater effect on DIBL suppression than the impurity concentration of an n-type layer (also referred to as a first CSL layer, or as a third first-conductivity-type semiconductor layer) 15a.

(12) The n-type layer (second CSL layer) 15b is in contact with the channel region 16, the p.sup.+-type region 3b, and the trench 19. Further, the n-type layer (second CSL layer) 15b is arranged to be in contact with the p.sup.+-type region 3a or on a surface (front surface) side of the n.sup.-type silicon carbide semiconductor substrate 2. The n-type layer (first CSL layer) 15a is in contact with the second CSL layer 15b, the n.sup.-type silicon carbide epitaxial layer 1, and the p.sup.+-type region 3a, and has an impurity concentration that is higher than that of the second CSL layer 15b and that of the n.sup.-type silicon carbide epitaxial layer 1. Other reference characters indicated in FIG. 1 will be described in detail hereinafter (refer to FIG. 7).

(13) FIG. 2 is a graph depicting the relationship of the impurity concentration ratio of the two-layer n-type CSL and DIBL, and parasitic resistance. The X axis represents the impurity concentration ratio of n.sup.-type layer 15b and the n-type layer 15a. The Y axis represents prescribed resistance and Vth. Vth is an index representing the magnitude of DIBL and preferably, may be a small value.

(14) As indicated in FIG. 2, the greater the impurity concentration ratio is reduced below 1.0, the more DIBL may be reduced. However, when the impurity concentration ratio is less than 0.5, the parasitic resistance suddenly increases. This is consequent to the increase in the parasitic resistance of a region of the n.sup.-type layer 15b sandwiched by the p.sup.+-type region 3 (3a, 3b). As a result, it is found that when the impurity concentration ratio of the n.sup.-type layer 15b and the n-type layer 15a is made to be 1.0 to 0.5, the short channel effect is suppressed and the increase of the parasitic resistance may be suppressed.

(15) FIGS. 3, 4, 5, 6, and 7 are cross-sectional views of the state of the active region of the silicon carbide semiconductor device according to the embodiment during manufacture.

(16) First, as depicted in FIG. 3, on the first main surface, e.g., (0001) face (Si face), of the n.sup.+-type silicon carbide substrate (also referred to as a high-concentration semiconductor substrate of the first conductivity type) 2 of a wide bandgap material, the n.sup.-type silicon carbide epitaxial layer (first first-conductivity-type semiconductor layer of a low concentration) 1 is deposited.

(17) The n.sup.+-type silicon carbide substrate 2, for example, is a silicon carbide single-crystal substrate doped with nitrogen (N). The n.sup.-type silicon carbide epitaxial layer 1 is a low-concentration n-type drift layer doped with, for example, nitrogen to have an impurity concentration that is lower than that of the n.sup.+-type silicon carbide substrate 2. Hereinafter, the n.sup.+-type silicon carbide substrate 2 alone or the n.sup.+-type silicon carbide substrate 2 in combination with the n.sup.-type silicon carbide epitaxial layer 1 is regarded as a silicon carbide semiconductor substrate.

(18) Next, as depicted in FIG. 4, on the first main surface side of the n.sup.-type silicon carbide epitaxial layer 1, the dense n-type region (first CSL layer) 15a is formed by patterning by photolithography and ion implantation of nitrogen. The dense n-type region 15 has an impurity concentration that is lower than that of the n.sup.+-type silicon carbide substrate 2 and higher than that of the n.sup.-type silicon carbide epitaxial layer 1; and, for example, is formed by doping nitrogen. The activated impurity concentration of the n-type layer 15a may be preferably about 1.010.sup.16 to 1.010.sup.19cm.sup.3 and the depth thereof may be preferably about 0.1 to 2.0 m.

(19) Next, the n-type layer 15a is patterned and ion implanted with aluminum, forming plural p-type base regions (p.sup.+-type regions) 3a along a length direction. 3a is a first p-type base region. The activated impurity concentration of the p.sup.+-type region 3a may be preferably about 1.010.sup.17 to 1.010.sup.19cm.sup.3, and the depth thereof may be preferably about 0.1 to 1.5 m.

(20) Further, on a surface of the n.sup.+-type silicon carbide substrate 2 on the side (rear surface of a silicon carbide semiconductor base) opposite the n-type silicon carbide epitaxial layer 1 side, a rear electrode is provided, forming a drain electrode.

(21) Next, as depicted in FIG. 5, on the front surface of the n-type layer 15a, silicon carbide of a concentration equal to that of the n.sup.-type layer 1 is deposited by nitrogen-added epitaxial growth to have a thickness of about 0.1 to 1.5 m and the n.sup.-type layer 15b is formed by patterning by photolithography and ion implantation of nitrogen. The n.sup.-type layer 15b is formed to have a concentration ratio of 1.0 to 0.5 with respect to the n-type layer 15a. The depth of the n.sup.-type layer 15b may be preferably about 0.1 to 2.0 m.

(22) Next, on the front side of the p.sup.+-type region 3a, the p-type base layer (p.sup.+-type region 3b) is formed by patterning and ion implantation of aluminum so as to be electrically connected to the p.sup.+-type region 3a. 3b is a second p-type base region. The activated impurity concentration of the p.sup.+-type region 3b may be preferably about 1.010.sup.17 to 1.010.sup.19cm.sup.3 and the depth thereof may be preferably about 0.2 to 2.0 m. Further, the n.sup.-type layer 15b may be formed by epitaxial growth without using ion implantation, so as to have a concentration ratio of 1.0 to 0.5 with respect to the n-type layer 15a.

(23) Next, as depicted in FIG. 6, silicon carbide is deposited on the front surface of the n.sup.-type layer 15b to have a thickness of about 0.1 to 1.5 m by nitrogen-added or aluminum-added epitaxial growth whereby the p-type channel region (p-type layer, channel region of the second conductivity type) 16 is formed. The activated impurity concentration of the p-type layer 16 may be preferably about 1.010.sup.16 to 1.010.sup.19cm.sup.3 and the depth thereof may be preferably about 0.3 to 1.5 m. The p-type layer 16 may be formed to have a concentration of about 1.010.sup.16 to 1.010.sup.19cm.sup.3 by aluminum-added epitaxial growth and ion implantation of aluminum may be omitted.

(24) Next, the front surface of the p-type layer 16 is patterned by photolithography and ion implanted with phosphorus or arsenic, or is ion implanted with nitrogen whereby the n-type source region (n.sup.+-type layer) 17 is formed. The activated impurity concentration of the n.sup.+-type layer 17 may be preferably about 1.010.sup.19 to 1.010.sup.20cm.sup.3 and the depth thereof may be preferably about 0.05 to 0.5 m.

(25) Next, the front surface of the n.sup.+-type layer 17 is patterned by photolithography and ion implanted with aluminum whereby the p.sup.+-type layer 18 is formed so as to be electrically connected to the p.sup.+-type region 3b. The activated impurity concentration of the p.sup.+-type layer 18 may be preferably about 1.010.sup.17to 1.010.sup.20 cm.sup.3 and the depth thereof may be preferably about 0.2 to 2.0 m. After a carbon film (not shown) is deposited to have a thickness of about 0.01 to 5.0 m, annealing at a temperature from 1500 to 1900 degrees C. is performed, activating the ion implanted impurities.

(26) Next, as depicted in FIG. 7, the trenches 19 are formed from the front surface of the silicon carbide semiconductor substrate by patterning by photolithography and dry etching so as to not penetrate the p.sup.+-type region 3a. The trenches 19 may preferably have a width of about 0.1 to 1.5 m and a depth of about 0.2 to 2.0 m. The trenches 19 may be formed to penetrate into, but not through, the p.sup.+-type region 3a in the n-type layer 15a. An interlayer insulating film 19a is deposited so as to cover the inside of the trenches 19. The interlayer insulating film 21, for example, is formed by a high-temperature oxide (HTO) film formed at a high temperature of about 600 to 900 degrees C. by a low-pressure CVD method to have a thickness of 30 nm to 200 nm.

(27) After poly-silicon is deposited so as to be embedded in the trenches 19, etching is performed leaving the poly-silicon in at least of the depth of the trenches 19 thereby forming the gate electrodes 20. On the gate electrode 20, after an oxide film having a thickness of about 0.1 to 3.0 m is deposited, patterning and etching are performed, forming the interlayer insulating film (field insulating film) 21. In one embodiment, the interlayer insulating film 21 and the interlayer insulating film 19a are formed of the same material.

(28) Thereafter, on the front surface of the silicon carbide semiconductor substrate, one or more of titanium, nickel, tungsten, and aluminum are deposited by a deposition method or a sputtering method to have a total thickness of about 0.5 to 8.0 m and patterning and etching are performed, forming the source electrode 22.

(29) As described, the structure of the active region depicted in the embodiment may be formed. Further, by the semiconductor production method above, the active region (FIG. 1) of the trench-type MOSFET of the embodiment may be formed.

(30) In FIG. 7 (and FIG. 1), although a structure of only three trenches is depicted, more trench MOS structures may be arranged in parallel, and embodiments of the invention encompass any number of trench MOS structures arranged in parallel.

(31) To retain the breakdown voltage in the OFF state, there are configurations in which an edge termination structure region is provided at an element outer periphery region of the active region as an edge termination structure. A typical example is a method of forming a junction termination extension (JTE) at a mesa portion.

(32) FIGS. 8 and 9 are cross-sectional views of an example of an edge termination structure region of the semiconductor device. An edge termination structure region 1101 depicted in FIG. 8 is formed on the silicon carbide semiconductor substrate 2, outside the active region 1102 described above. The edge termination structure region 1101 has the p.sup.+-type base layer 3, an n.sup.+-type channel stopper region 4, an interlayer insulating film 5, a first JTE region (p-type layer) 6, and a second JTE region (p.sup.-type layer) 7 formed on the front side of the n.sup.-type silicon carbide epitaxial layer 1 formed on the n.sup.+-type silicon carbide substrate 2.

(33) In the case of the edge termination structure region 1101 depicted in FIG. 8, when patterning is performed in a region having a height different from the active region 1102, like a mesa portion, the depth of focus of the photolithography differs and process difficulty is improved. In contrast, as depicted in FIG. 9, there is a further structure in which the edge termination structure region 1101 and the active region 1102 have the same height and no mesa portion is formed. In this manner, the structure of the edge termination structure region 1101 may be implemented by various types of structures.

(34) According to the structure of the active region described, the n-type layer is double-layered and is provided having an impurity concentration that is lower in the n.sup.-type layer 15b near the channel p-type layer 16 than in the n-type layer 15a. According to this structure, the overall impurity concentration of the n-type layer 15 (15a, 15b) is reduced and in the ON state, a threshold value decrease originating in the short channel effect of DIBL may be suppressed.

(35) Here, when the impurity concentration of the n-type layer 15 having a single-layer structure is simply reduced, the depletion layer spreads easily from the p-type layer, the current path is blocked, and the ON resistance suddenly increases. However, in the embodiment, the two-layer structure is provided in which the impurity concentration of the n.sup.-type layer 15b near the channel p-type layer 16 is lower with respect to the n-type layer 15a enables DI BL to be suppressed.

(36) Concerning this point, in a conventional trench-type MOSFET, when the channel length is reduced to reduce the ON resistance, short channel effects such as decreased threshold occur. However, by setting the impurity concentration ratio of the n.sup.-type layer 15b and the n-type layer 15a to be 1.0 to 0.5, short channel effects and increases of parasitic resistance may be suppressed.

(37) As described, according to the embodiment of the present invention, increases of parasitic resistance and the occurrence of short channel effects may be suppressed, and the channel length may be further reduced, enabling reduction of the ON resistance.

(38) However, with a conventional trench-type MOSFET, since short channel effects such as decreased threshold occur when the channel length is reduced to reduce the ON resistance, a new problem of suppressing short channel effects arises. For example, short channel effects occur in regions in which the channel length is less than 1.0 m.

(39) According to the embodiment, the semiconductor layer of the first conductivity type near the channel region of the second conductivity type and effective in suppressing DIBL is provided as two layers in which the second semiconductor layer, which is the upper layer and of the first conductivity type, has an impurity concentration that is reduced more than the impurity concentration of the third semiconductor layer, which is the lower layer and of the first conductivity type. The impurity concentration ratio of these semiconductor layers of the first conductivity type are set to be, for example, 1.0 to 0.5 whereby short channel effects and increases in parasitic resistance may be suppressed.

(40) The semiconductor device according to the present invention achieves an effect in that increases of parasitic resistance and the occurrence of short channel effects may be suppressed, and the ON resistance may be reduced by further reducing the channel length.

(41) As described, the semiconductor device according to the present invention is useful for high voltage semiconductor devices used in power converting equipment and power supply devices such as those in various industrial machines.

(42) Although the invention has been described with respect to a specific embodiment for a complete and clear disclosure, the appended claims are not to be thus limited but are to be construed as embodying all modifications and alternative constructions that may occur to one skilled in the art which fairly fall within the basic teaching herein set forth.