Low temperature poly-silicon thin film transistor and method of manufacturing the same

Abstract

The present disclosure relates to a low temperature poly-silicon thin film transistor and a method of preparing the same. The low temperature poly-silicon thin film transistor includes a substrate, a metal induction layer formed on the substrate, a barrier layer formed on the metal induction layer, and an amorphous silicon film layer formed on the barrier layer, the amorphous silicon film layer being converted into a poly-silicon film layer under the inducing effect of the metal induction layer, and the poly-silicon film layer being an active layer. In the present disclosure, although the active layer is obtained by using the metal induction method, the metal induction layer is provided below the amorphous silicon film layer, and a barrier layer is provided between the metal induction layer and the amorphous silicon film layer.

Claims

1. A low temperature poly-silicon thin film transistor comprising a substrate and a metal induction layer formed on the substrate, wherein the low temperature poly-silicon thin film transistor further comprises: a barrier layer formed on the metal induction layer; an amorphous silicon film layer formed on the barrier layer; wherein the amorphous silicon film layer being converted into a poly-silicon film layer under the inducing effect of the metal induction layer, and the poly-silicon film layer being an active layer; and wherein the metal induction layer is patterned to obtain a patterned metal induction layer.

2. The low temperature poly-silicon thin film transistor according to claim 1, wherein a material chosen for the metal induction layer is one of nickel and nickel silicon alloy.

3. The low temperature poly-silicon thin film transistor according to claim 2, wherein a material chosen for the metal induction layer is nickel silicon alloy, and in a top of the metal induction layer, a mass percentage of the nickel in the nickel silicon alloy is 1%-15%.

4. The low temperature poly-silicon thin film transistor according to claim 1, wherein a thickness of the metal induction layer is 200 -1200 .

5. The low temperature poly-silicon thin film transistor according to claim 1, wherein a material chosen for the barrier layer is SiO.sub.x.

6. The low temperature poly-silicon thin film transistor according to claim 1, wherein a material chosen for the barrier layer is SiO.sub.x.

7. The low temperature poly-silicon thin film transistor according to claim 2, wherein a material chosen for the barrier layer is SiO.sub.x.

8. The low temperature poly-silicon thin film transistor according to claim 3, wherein a material chosen for the barrier layer is SiO.sub.x.

9. The low temperature poly-silicon thin film transistor according to claim 4, wherein a material chosen for the barrier layer is SiO.sub.x.

10. The low temperature poly-silicon thin film transistor according to claim 1, wherein a thickness of the barrier layer is 20 -200 .

11. The low temperature poly-silicon thin film transistor according to claim 1, wherein a thickness of the barrier layer is 20 -200 .

12. The low temperature poly-silicon thin film transistor according to claim 2, wherein a thickness of the barrier layer is 20 -200 .

13. The low temperature poly-silicon thin film transistor according to claim 3, wherein a thickness of the barrier layer is 20 -200 .

14. The low temperature poly-silicon thin film transistor according to claim 4, wherein a thickness of the barrier layer is 20 -200 .

15. A method of preparing a low temperature poly-silicon thin film transistor, wherein the method comprises: providing a substrate; forming a metal induction layer on the substrate; forming a barrier layer on the metal induction layer; forming an amorphous silicon film layer on the barrier layer, and converting the amorphous silicon film layer into a poly-silicon film layer under the inducing effect of the metal induction layer, and the poly-silicon film layer being an active layer; and wherein after forming the active layer, an upper surface film layer of the active layer is removed; and performing photoetching and etching on the active layer to obtain the patterned active layer.

16. The preparation method according to claim 15, wherein converting the amorphous silicon film layer into the poly-silicon film layer under the inducing effect of the metal induction layer refers to diffusing the metal ions of the metal induction layer into the amorphous silicon film layer by using a rapid thermal annealing process, and converting the amorphous silicon film layer into the poly-silicon film layer through the induction of the metal ions.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIGS. 1-7 illustrate the process of the method for manufacturing a low temperature poly-silicon thin film transistor according to the embodiments of the present disclosure.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

Embodiments

(2) The present embodiment provides a low temperature poly-silicon thin film transistor, and FIG. 7 is a cross-section structural diagram of the low temperature poly-silicon thin film transistor, including: a substrate 1, a buffer layer 2 formed on the substrate 1, a metal induction layer 3 formed on the buffer layer 2, a barrier layer 4 formed on the metal induction layer 3, an active layer 52 formed on the barrier layer 4.

(3) Wherein the buffer layer 2 is formed on the substrate 1 by using the chemical vapor deposition process.

(4) Wherein the metal induction layer 3 is formed on the buffer layer 2 by using a physical deposition process, then the metal induction layer 3 is patterned by coating photoresist and performing exposure, development and etching, to obtain the patterned metal induction layer 3, the patterned metal induction layer also being a light shielding layer of the low temperature poly-silicon thin film transistor of the present embodiment. In the present embodiment, the thickness of the metal induction layer is 300 -1000 , and is preferably 450 , which adopts a material of a nickel silicon alloy, also, in the top of the metal induction layer, the mass percentage of the nickel in the nickel silicon alloy is 1%-10%, and is preferably 5%.

(5) Wherein the barrier layer 4 is formed on the patterned metal induction layer 3 by using a plasma enhanced chemical vapor deposition process. In the present embodiment, the barrier layer is provided to allow the metal ions in the metal induction layer to pass through the barrier layer and enter the amorphous silicon film layer at a beginning stage in the process of converting the amorphous silicon film layer into the poly-silicon film layer, and as the conversion proceeds, the barrier layer gradually forms a dense film structure so as to prevent too many metal ions from entering into the amorphous silicon film layer, hence preventing a large amount of residues of metal ions, and preventing the metal ions from further diffusing into the active layer in other subsequent processes. For this purpose, the barrier layer should not be too thick or too thin. If the barrier layer is too thick, it may block the diffusion of the metal ions in the metal induction layer, hence affecting the crystallization effect when converting the amorphous silicon film layer into the poly-silicon film layer, and causing the crystallized grain to be too small. If the barrier layer is too thin, then in a later stage of the conversion, the dense film structure can hardly be formed to prevent too many metal ions from entering the amorphous silicon film layer. In the present embodiment, a thickness of the barrier layer 4 is 20 -200 , and is preferably 40 , a material chosen for the barrier layer is SiO.sub.x, and the O in SiO.sub.x and the Si in the metal induction layer may form a dense silicon oxide film layer structure.

(6) Wherein the forming of the active layer is as follows: depositing and forming the amorphous silicon film layer on the barrier layer 4 by using the plasma enhanced chemical vapor deposition process, the amorphous silicon film layer may have a proper thickness for the need of mass production, for example, a thickness of the amorphous silicon film layer in the present embodiment is 300 -800 , and preferably, the thickness of the amorphous silicon film layer is 500 . Then, after forming the amorphous silicon layer 51, under the inducing effect of the metal induction layer, and by adopting the rapid thermal annealing process, the amorphous silicon film layer 51 is heated at a temperature of 500 C.-700 C., and is then cooled rapidly to convert the amorphous silicon film layer into the poly-silicon film layer, the poly-silicon film layer being the active layer 52.

(7) In a process of converting the amorphous silicon film layer into the poly-silicon film layer, since the metal induction layer is provided below the amorphous silicon film layer, the nickel ions in the metal induction layer may diffuse upward and around in the amorphous silicon film layer. Eventually, after the amorphous silicon film layer is converted into the poly-silicon film layer, as shown in FIG. 6, an upper surface film layer 53 having residues of nickel ions is formed on an upper surface of the active layer 52, and a peripheral film layer 54 having the residues of nickel ions is formed around the active layer 52 (since FIG. 6 is a sectional view, only the left and right sides of the active layer are shown in FIG. 6).

(8) Therefore, in the present embodiment, as shown in FIG. 7, an HF cleaner is adopted to remove the upper surface film layer; then a photo etching and a dry etching process are performed on the active layer 52 to obtain the patterned active layer 52. In the above procedure, the peripheral film layer is the active layer in the non-patterned region, hence it is removed during the process of patterning. Through processing the upper surface film layer and the peripheral film layer above mentioned, the residual metal ions in the active layer can be effectively removed.

(9) Next, a gate insulating layer, a gate and a dielectric layer are formed on the patterned active layer, the dielectric layer being provided with a source contact hole and a drain contact hole capable of partially exposing the active layer, and a source being formed in the source contact hole, the source contacting the active layer through the source contact hole, and a drain being formed in the drain contact hole, the drain contacting the active layer through the drain contact hole. A passivation layer is provided on the dielectric layer, the passivation layer forming an opening for partially exposing the drain electrode in a region corresponding to the drain; the low temperature poly-silicon thin film transistor of the present embodiment is also formed with a pixel electrode contacting the drain through the opening. Understandably it may serve as a prior art in the field to form structures such as the gate insulating layer, the gate, the dielectric layer, the source, the drain, the passivation layer, the pixel electrode and the like, sequentially after obtaining the patterned active layer, which will not be repeated hereby.

(10) The present embodiment provides a method of manufacturing the above mentioned low temperature poly-silicon thin film transistor, the method comprising:

(11) As shown in FIG. 1, a substrate 1 is provided, and a buffer layer 2 is formed on the substrate 1 by using the chemical vapor deposition process.

(12) As shown in FIG. 2, a metal induction layer 3 is formed on the buffer layer 2 by using the physical deposition process, and the metal induction layer 3 is patterned by coating photo resist and performing exposure, development and etching, to obtain the patterned metal induction layer 3 as shown in FIG. 3, and the patterned metal induction layer is a light shielding layer of the low temperature poly-silicon thin film transistor of the present embodiment. In the present embodiment, the thickness of the metal induction layer is 300 -1000 , and is preferably 450 , which adopts a material of a nickel silicon alloy, also, in the top of the metal induction layer, the mass percentage of the nickel in the nickel silicon alloy is 1%-10%, and is preferably 5%.

(13) As shown in FIG. 4, the barrier layer 4 is formed on the patterned metal induction layer 3 by using a plasma enhanced chemical vapor deposition process, a thickness of the barrier layer 4 is 20 -200 , and is preferably 40 , and a material chosen for the barrier layer is SiO.sub.x.

(14) As shown in FIG. 5, amorphous silicon film layer 51 is formed on the barrier layer 4 by using the plasma enhanced chemical vapor deposition process, the amorphous silicon film layer may have a proper thickness for the need of mass production, for example, a thickness of the amorphous silicon film layer in the present embodiment is 300 -800 , preferably, a thickness of the amorphous silicon film layer is 500 .

(15) As shown in FIG. 6, the amorphous silicon film layer is converted into a poly-silicon film layer under the inducing effect of the metal induction layer. More particularly, by adopting the rapid thermal annealing process, the amorphous silicon layer 51 is heated at a temperature of 500 C.-700 C., so that the nickel ions in the metal induction layer 3 may diffuse into the amorphous silicon film layer 51, and the amorphous silicon film layer 51 is converted into the poly-silicon film layer through the induction of the nickel ions, the poly-silicon film layer being the active layer 52.

(16) In a process of converting the amorphous silicon film layer into the poly-silicon film layer, since the metal induction layer is provided below the amorphous silicon film layer, the nickel ions in the metal induction layer may diffuse upward and around in the amorphous silicon film layer. Eventually, after the amorphous silicon film layer is converted into the poly-silicon film layer, As shown in FIG. 6, an upper surface film layer 53 having residues of nickel ions is formed on an upper surface of the active layer 52, and a peripheral film layer 54 having the residues of nickel ions is formed around the active layer 52 (since FIG. 6 is a sectional view, only the left and right sides of the active layer are shown in FIG. 6).

(17) Therefore, in the present embodiment, as shown in FIG. 7, an HF cleaner is adopted to remove the upper surface film layer 53; then a photo etching and a dry etching process are performed on the active layer 52 to obtain the patterned active layer 52. In the above procedure, the peripheral film layer 54 is the active layer in the non-patterned region, hence it is removed during the process of patterning. Through the processing on the upper surface film layer and the peripheral film layer, the residual metal ions in the active layer can be effectively removed.

(18) Next, a gate insulating layer, a gate and a dielectric layer are formed sequentially on the patterned active layer through deposition, a source contact hole and a drain contact hole capable of partially exposing the active layer being formed in the dielectric layer. A source is formed in the source contact hole, the source contacting the active layer through the source contact hole, and a drain is formed in the drain contact hole, the drain contacting the active layer through the drain contact hole. A passivation layer is formed on the dielectric layer through deposition, the passivation layer forming an opening for partially exposing the drain electrode in a region corresponding to the drain; the low temperature poly-silicon thin film transistor of the present embodiment is also formed with a pixel electrode contacting the drain through the opening. Understandably it may serve as a prior art in the field to form structures such as the gate insulating layer, the gate, the dielectric layer, the source, the drain, the passivation layer, the pixel electrode, and the like, subsequently after obtaining the patterned active layer, which will not be repeated hereby.

(19) Here, a principle of the present embodiment effectively solving the problem of residues of metal ions in the active layer is described.

(20) First, the principle of the present embodiment converting the amorphous silicon film layer into the poly-silicon film layer under the inducing effect of the metal induction layer is as follows: under the high temperature, the Ni ions in the metal induction layer contact with the amorphous silicon film layer to form the contact interface, and the Ni may interact with the Si to form the Ni.sub.ySi compound (namely, the metal silicide); in forming the NiySi compound, due to the release of heat energy, and a difference in change of the lattice position of a-Si at an interface, the a-Si atoms may recrystallize at the interface to form p-Si, hence causing the Ni.sub.ySi compound to be damaged, the Ni ions may further diffuse to the uncrystallized a-Si, and the procedure of forming the Ni.sub.ySi compound, forming p-Si through recrystallization of a-Si and damaging the Ni.sub.ySi compound may be repeated, until the a-Si is completely converted into p-Si (namely, the poly-silicon film layer).

(21) Secondly, the principle of the barrier layer is as follows: a material chosen for the barrier layer in the present embodiment is SiO.sub.x, and the film layer is relatively thin. During the metal induction, an early stage is a heating process, in which a length of the SiO bond in the SiO.sub.x structure is relatively long, hence the Ni ions in the metal induction layer under the barrier layer can pass through the barrier layer quickly and enter the a-Si layer to perform induction; while as the temperature rises and the induction proceeds, the remaining Si in the metal induction layer may combine with the O in the barrier layer to form the thermal oxidized dense silicon oxide, and the length of the SiO bond in the SiO.sub.x gradually decreases, so that the Ni ions in the metal induction layer can hardly enter the amorphous silicon film layer through the barrier layer. Accordingly, the barrier layer can realize control over the content of the metal ions entering the amorphous silicon film layer, which can perform the barrier function.

(22) Understandably the above contents only describe the main structure of the low temperature poly-silicon thin film transistor, while the low temperature poly-silicon thin film transistor may also include other conventional function structures, which will not be repeated in the present disclosure.

(23) The embodiments of the present disclosure as mentioned above are only the examples made for clearly illustrate the present disclosure, rather than definitions made on the embodiments of the present disclosure. To those skilled in the art, other changes or modifications of different forms can be made based on the above description. Here, it is unnecessary to enumerate all the embodiments. Any modifications, substitutions and improvements made within the spirit and principle of the present disclosure shall fall within the protection scope of the claims of the present disclosure.