TECHNIQUE FOR REDUCING GATE INDUCED DRAIN LEAKAGE IN DRAM CELLS

Abstract

A method of forming a metal oxide semiconductor field effect transistor with improved gate-induced drain leakage performance, the method including providing a semiconductor substrate having a gate trench formed therein, performing an ion implantation process on upper portions of sidewalls of the gate trench to make the upper portions more susceptible to oxidation relative to non-implanted lower portions of the sidewalls, and performing an oxidation process on surfaces of the substrate, wherein the implanted upper portions of the sidewalls develop a thicker layer of oxidation relative to the non-implanted lower portions of the sidewalls.

Claims

1. A method of forming a metal oxide semiconductor field effect transistor, the method comprising: providing a semiconductor substrate having a gate trench formed therein; performing an ion implantation process on upper portions of sidewalls of the gate trench to make the upper portions more susceptible to oxidation relative to non-implanted lower portions of the sidewalls; and performing an oxidation process on surfaces of the substrate, wherein the implanted upper portions of the sidewalls develop a thicker layer of oxidation relative to the non-implanted lower portions of the sidewalls.

2. The method of claim 1, wherein the ion implantation process comprises directing an ion beam at the substrate at oblique angles relative to a top surface of the substrate.

3. The method of claim 2, wherein the oblique angles are in a range of 20 degrees to 65 degrees.

4. The method of claim 2, wherein the ion beam is directed at the substrate in two opposing directions.

5. The method of claim 1, further comprising depositing a work function metal layer in the gate trench.

6. The method of claim 5, wherein the work function metal layer is formed of one of TiN, TiAlC, are TiC.

7. The method of claim 6, further comprising recessing the work function metal layer to a predetermined height.

8. The method of claim 5, further comprising depositing a polysilicon layer on top of the work function metal layer.

9. The method of claim 8, further comprising recessing the polysilicon layer to a predetermined height.

10. The method of claim 1, further comprising depositing a capping layer in the gate trench.

11. The method of claim 10, further comprising performing a planarization process on the capping layer.

12. The method of claim 1, wherein the oxidation process comprises one of in-situ steam generation, rapid thermal oxidation, atomic layer deposition, physical vapor deposition, and chemical vapor deposition.

13. A method of forming metal oxide semiconductor field effect transistors, the method comprising: providing a semiconductor substrate having a first gate trench and a second gate trench formed therein; performing an ion implantation process on upper portions of sidewalls of the first and second gate trenches to make the upper portions more susceptible to oxidation relative to non-implanted lower portions of the sidewalls, the ion implantation process comprising directing an ion beam at the substrate at oblique angles in a range of 20 degrees to 65 degrees relative to a top surface of the substrate; performing an oxidation process on surfaces of the substrate via one of in-situ steam generation, rapid thermal oxidation, atomic layer deposition, physical vapor deposition, and chemical vapor deposition, wherein the implanted upper portions of the sidewalls develop a thicker layer of oxidation relative to the non-implanted lower portions of the sidewalls; and depositing work function metal layers in the first and second gate trenches.

14. A method of forming a metal oxide semiconductor field effect transistor, the method comprising: providing a semiconductor substrate having a gate trench formed therein, the gate trench having a source side sidewall, an opposing drain side sidewall, and a floor; performing an ion implantation process on an upper portion of the drain side sidewall of the gate trench to make the upper portion more susceptible to oxidation relative to the non-implanted source side sidewall, floor, and lower portion of the drain side sidewall; and performing an oxidation process on surfaces of the substrate, wherein the implanted upper portion of the drain side sidewall develops a thicker layer of oxidation relative to the non-implanted source side sidewall, floor, and lower portion of the drain side sidewall.

15. The method of claim 14, wherein the ion implantation process comprises directing an ion beam at the substrate at an oblique angle relative to a top surface of the substrate.

16. The method of claim 15, wherein the oblique angle is in a range of 20 degrees to 65 degrees.

17. The method of claim 14, further comprising depositing a work function metal layer in the gate trench.

18. The method of claim 17, further comprising depositing a polysilicon layer on top of the work function metal layer.

19. The method of claim 14, further comprising depositing a capping layer in the gate trench.

20. The method of claim 14, wherein the oxidation process comprises one of in-situ steam generation, rapid thermal oxidation, atomic layer deposition, physical vapor deposition, and chemical vapor deposition.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0009] By way of example, various embodiments of the disclosed techniques will now be described with reference to the accompanying drawings, wherein:

[0010] FIGS. 1A-1H are a series of cross-sectional views illustrating a method of producing MOSFETs having relatively thick gate oxide films formed on gate-to-drain and/or gate-to-source overlap regions thereof in accordance with exemplary embodiments of the present disclosure;

[0011] FIG. 2 is a flow diagram summarizing the processes shown in FIGS. 1A-1F.

DETAILED DESCRIPTION

[0012] The present embodiments will now be described more fully hereinafter with reference to the accompanying drawings, wherein some exemplary embodiments are shown. The subject matter of the present disclosure may be embodied in many different forms and are not to be construed as limited to the embodiments set forth herein. These embodiments are provided so this disclosure will be thorough and complete, and will fully convey the scope of the subject matter to those skilled in the art. In the drawings, like numbers refer to like elements throughout.

[0013] As used herein, an element or operation recited in the singular and proceeded with the word “a” or “an” are understood as possibly including plural elements or operations, except as otherwise indicated. Furthermore, various embodiments herein have been described in the context of one or more elements or components. An element or component may comprise any structure arranged to perform certain operations. Although an embodiment may be described with a limited number of elements in a certain topology by way of example, the embodiment may include more or less elements in alternate topologies as desired for a given implementation. Note any reference to “one embodiment” or “an embodiment” means a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. The appearances of the phrases “in one embodiment,” “in some embodiments,” and “in various embodiments” in various places in the specification are not necessarily all referring to the same embodiment.

[0014] The present embodiments provide novel techniques for forming Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs), and in particular novel techniques for forming MOSFETs with improved gate-induced drain leakage (GIDL) performance. MOSFETs produced using the techniques described herein may be beneficial in the manufacture of transistors used in dynamic random-access memory (DRAM) cells, for example, wherein the reduction of GIDL is of particular importance. The present disclosure is not limited in this regard.

[0015] Referring to FIGS. 1A-1H, a series of cross-sectional views illustrating an exemplary process for producing MOSFETs having relatively thick gate oxide films formed on gate-to-source and gate-to-drain overlap regions thereof is shown. Referring to FIG. 2, a flow diagram summarizing the exemplary processes illustrated in FIGS. 1A-1H is provided. For the sake of convenience and clarity, terms such as “top,” “bottom,” “upper,” “lower,” “vertical,” “horizontal,” “lateral,” and “longitudinal,” may be used herein to describe the relative position and orientation of various structures, all with respect to the geometry and orientation of the structures as they appear in the views shown in FIGS. 1A-1F. Said terminology is not intended to be limiting and includes the words specifically mentioned, derivatives thereof, and words of similar import.

[0016] Referring to FIG. 1A and block 100 in FIG. 2, a semiconductor substrate 10 (hereinafter “the substrate 10”) may be provided. The substrate 10 may have one or more trenches formed therein, e.g., horizontally adjacent, spaced-apart trenches 12, 14. The trenches 12, 14, hereinafter referred to as “the first gate trench 12” and “the second gate trench 14,” may have angled sidewalls 12a, 12b and 14a, 14b (i.e., angled relative to a top surface 16 of the substrate) providing the first gate trench 12 and the second gate trench 14 with tapered, generally V-shaped profiles as shown. For the purposes of the following description, the first gate trench 12 and the second gate trench 14 provide the basis for two adjacent MOSFETs having respective sources of the left sides of the first gate trench 12 and the second gate trench 14 and having respective drains on the right sides of the first gate trench 12 and the second gate trench 14. Thus, the left-side sidewalls 12a, 14a may be referred to herein as “the source side sidewalls 12a, 14a,” and the right-side sidewalls 12b, 14b may be referred to herein as “the drain side sidewalls 12a, 14a.” In various alternative embodiments, the first gate trench 12 and the second gate trench 14 may provide the basis for two adjacent MOSFETs having a shared drain located between the first gate trench 12 and the second gate trench 14, a first source on the left side of the first gate trench 12, and a second source on the right side of the second gate trench 14 (as in a conventional DRAM transistor structure). In other alternative embodiments, the first gate trench 12 and the second gate trench 14 may provide the basis for two adjacent MOSFETs having a shared source located between the first gate trench 12 and the second gate trench 14, a first drain on the left side of the first gate trench 12, and a second drain on the right side of the second gate trench 14. The present disclosure is not limited in this regard.

[0017] In various embodiments, the tops of the first gate trench 12 and the second gate trench 14 may have widths in a range of 30 nm to 60 nm, and the bottoms of the first gate trench 12 and the second gate trench 14 may have widths in a range of 10 nm to 40 nm. The present disclosure is not limited in this regard. The substrate 10 may be formed of any suitable semiconductor material, including, and not limited to, silicon (e.g., crystalline silicon), germanium, silicon carbide, gallium arsenide, gallium nitride, etc.

[0018] Referring to FIG. 1B and block 110 in FIG. 2, an ion implantation process may be performed on the substrate 10, wherein an ion beam 18 formed of an ionized dopant species may be directed at the substrate 10 at oblique angles relative to the top surface 16 of the substrate 10. For example, the source of the ion beam 18 may be tilted relative to the substrate 10 (e.g., 20 degrees to 65 degrees), or the substrate 10 may be tilted relative to the source of the ion beam 18 to achieve the desired angles of implantation. As shown, the ion beam 18 may be directed at the substrate 10 in two opposing directions (e.g., right-to-left and left-to-right). This may be achieved by performing two sequential exposures, wherein one ion beam source (not shown) is repositioned relative to the substrate 10 between exposures, or by implementing two ion beam sources facing opposing directions. The present disclosure is not limited in this regard.

[0019] Thus, the ion beam 18 may impinge on the top surface 16 of the substrate 10 as well as on upper portions of the sidewalls 12a, 12b and 14a, 14b of the first gate trench 12 and the second gate trench 14, while lower portions of the sidewalls 12a, 12b and 14a, 14b and floors 34, 36 of the first gate trench 12 and the second gate trench 14 are shielded from the ion beam 18. The dopant species transmitted in the ion beam 18 may be selected to make the implanted surfaces of the substrate 10 more susceptible to oxidation relative to the non-implanted surfaces of the substrate 10. More specifically, the implanted top surface 16 of the substrate 10 and upper portions of the sidewalls 12a, 12b and 14a, 14b may become more susceptible to oxidation than the lower portions of the sidewalls 12a, 12b and 14a, 14b and floors 34, 36. In various examples, the dopant species may be one or more of germanium, phosphorus, arsenic, boron, gallium, antimony, etc. The present disclosure is not limited in this regard.

[0020] While the ion implantation process of FIG. 1B has been shown and described as being performed on the top surface 16 of the substrate 10 and upper portions of all of the sidewalls 12a, 12b and 14a, 14b of the first gate trench 12 and the second gate trench 14, alternative embodiments of the present disclosure are contemplated wherein the upper portions of the drain side sidewalls 12b, 14b are implanted while the upper portions of the source side sidewalls 12a, 12b are not implanted as shown in FIG. 1C. Thus, above described ion implantation is performed in one tilted direction instead of two.

[0021] Referring to FIG. 1D and block 120 in FIG. 2, an oxidation process may be performed wherein thermal or ionized oxygen atoms 20 may react with the substrate 10 or be deposited on the substrate 10 to oxidize surfaces thereof, including the top surface 16, the sidewalls 12a, 12b of the first gate trench 12, and the sidewalls 14a, 14b of the second gate trench 14. Such deposition may be achieved using various deposition processes familiar to those of ordinary skill in the art, including, and not limited to, in-situ steam generation (ISSG), rapid thermal oxidation (RTO), atomic layer deposition (ALD), physical vapor deposition (PVD), and chemical vapor deposition (CVD). The present disclosure is not limited in this regard.

[0022] Owning to the ion implantation process previously performed on the top surface 16 of the substrate 10 and upper portions of the sidewalls 12a, 12b and 14a, 14b (as described above and as illustrated in FIG. 1B), the top surface 16 of the substrate 10 and upper portions of the sidewalls 12a, 12b and 14a, 14b may be more susceptible to oxidation than the lower portions of the sidewalls 12a, 12b and 14a, 14b. Thus, as the various surfaces of the substrate 10 are oxidized, the top surface 16 of the substrate 10 and upper portions of the sidewalls 12a, 12b and 14a, 14b may oxidize more rapidly than the lower portions of the sidewalls 12a, 12b and 14a, resulting in the formation of oxidation layers 22, 24a, 24b, and 26a, 26b on the top surface 16 of the substrate 10 and upper portions of the sidewalls 12a, 12b and 14a, 14b thicker than oxidation layers 28a, 28b, 30a, 30b, 32, and 33 formed on the lower portions of the sidewalls 12a, 12b and 14a, 14b and floors 34, 36 of the first gate trench 12 and the second gate trench 14, respectively. Of course, if the above-described ion implantation process was performed on the drain side sidewalls 12b, 14b and not on the source side sidewalls 12a, 14a (see FIG. 1C), the thicker oxidation layers will form on the drain side sidewalls 12b, 14b and not on the source side sidewalls 12a, 14a as shown in FIG. 1E.

[0023] Referring to FIG. 1F and block 130 in FIG. 2, work function metal layers 40a, 40b may be deposited within the first gate trench 12 and the second gate trench 14, respectively. The work function metal layers 40a, 40b may be formed of a transition metal nitride compound, such as TiN, TiAlC, or TiC, for example. Deposition may be achieved using physical vapor deposition, chemical vapor deposition, atomic layer deposition, etc. The present disclosure is not limited in this regard. After the first gate trench 12 and the second gate trench 14 are partially or entirely filled with the work function metal layers 40a, 40b a recessing or chamfering process may be performed wherein the work function metal layers 40a, 40b are etched back to a predetermined height within the trenches. For example, the work function metal layers 40a, 40b may be etched back to the heights of the lowermost edges of the thicker oxidation layers 24a, 24b, and 26a, 26b on the upper portions of the sidewalls 12a, 12b and 14a, 14b as shown in FIG. 1F. The present disclosure is not limited in this regard. The recessing or chamfering may be achieved using any of a wet etching, dry etching, or an ion etching process, for example.

[0024] Referring to FIG. 1G and block 140 in FIG. 2, polysilicon layers 42a, 42b may be deposited within the first gate trench 12 and the second gate trench 14 atop the work function metal layers 40a, 40b, respectively. Deposition may be achieved using physical vapor deposition, chemical vapor deposition, atomic layer deposition, etc. The present disclosure is not limited in this regard. After the polysilicon layers 42a, 42b have been deposited, a recessing or chamfering process may be performed wherein the polysilicon layers 42a, 42b are etched back to a predetermined height within the trenches. For example, the polysilicon layers 42a, 42b may be etched back to a height above the lowermost edges of the thicker oxidation layers 24a, 24b, and 26a, 26b on the upper portions of the sidewalls 12a, 12b and 14a, 14b and below the tops of trenches as shown in FIG. 1G. The present disclosure is not limited in this regard. The recessing or chamfering may be achieved using any of a wet etching process, a dry etching process, or an ion etching process, for example. In various embodiments of the present disclosure, the polysilicon layers 42a, 42b and the associated recessing process may be entirely omitted.

[0025] Referring to FIG. 1H and block 150 in FIG. 2, capping layers 44a, 44b may be deposited within the first gate trench 12 and the second gate trench 14 atop the polysilicon layers 42a, 42b, respectively. The capping layers 44a, 44b may be formed of any suitable capping material familiar to those of ordinary skill in the art, such as SiN, SiCN, SiC, SiON, for example. Deposition may be achieved using physical vapor deposition, chemical vapor deposition, atomic layer deposition, etc. The present disclosure is not limited in this regard. After the capping layers 44a, 44b have been deposited, a planarization process may be performed wherein the capping layers 44a, 44b are removed to a predetermined height. For example, the capping layers 44a, 44b may be polished back to make the top surfaces of the capping layers 44a, 44b coplanar with the top surface 16 of the substrate 10 as shown in FIG. 1H. The present disclosure is not limited in this regard. The planarization may be achieved using any of a chemical mechanical planarization process, a mechanical polishing process, a dry etching, or an ion etching process, for example.

[0026] Referring to block 160 in FIG. 2, additional processes may be performed on the substrate 10, the first gate trench 12, and the second gate trench 14 to produce complete transistor devices (e.g., a DRAM cell). These processes may include the formation of source and drain terminals adjacent the first and second gate trenches 12, 14, for example. Such processes will be familiar to those of ordinary skill in the art and will thus not be described in further detail herein.

[0027] The exemplary method described above and illustrated in FIGS. 1A-1H and FIG. 2 may produce a MOSFETs having relatively thick gate oxide films formed on gate-to-drain and/or gate-to-source overlap regions thereof, thus providing several advantages in the art. For example, GIDL may be improved (i.e., reduced) in the completed MOSFETs, thus improving the performance of a device (e.g., a DRAM cell) incorporating the MOSFETs. Additionally, the method illustrated in FIGS. 1A-1H and FIG. 2 may be incorporated into existing MOSFET manufacturing processes conveniently and at relatively low cost, resulting in a relatively low impact on the manufacturing cost of MOSFETs.

[0028] The present disclosure is not to be limited in scope by the specific embodiments described herein. Indeed, other various embodiments of and modifications to the present disclosure, in addition to those described herein, will be apparent to those of ordinary skill in the art from the foregoing description and accompanying drawings. Thus, such other embodiments and modifications are intended to fall within the scope of the present disclosure. Furthermore, while the present disclosure has been described herein in the context of a particular implementation in a particular environment for a particular purpose, those of ordinary skill in the art will recognize its usefulness is not limited thereto. Embodiments of the present disclosure may be beneficially implemented in any number of environments for any number of purposes. Accordingly, the claims set forth below shall be construed in view of the full breadth and spirit of the present disclosure as described herein.