TFT substrate manufacturing method

Abstract

Disclosed is a TFT substrate manufacturing method, which first forms a pixel electrode, a data line, and source/drain terminals on a base plate and then forms a channel protection layer and an oxide semiconductor layer; or alternatively first forming a buffer layer on the base plate to prevent characteristics of a TFT from being affected by direct contact between an oxide semiconductor layer and the base plate, and then forming the oxide semiconductor layer directly after formation of source/drain terminals so as to save one etch stopper layer, thus preventing damages induced in the oxide semiconductor layer by an etching operation of the source/drain terminals; and further, through forming a protective layer that covers a surface of a gate terminal to protect the gate terminal from corrosion at the same time of forming a common electrode, formation of an insulation protective layer can be saved.

Claims

1. A thin-film transistor (TFT) substrate manufacturing method, comprising the following steps: (1) providing a base plate, depositing a first transparent conductive layer on the base plate and patterning the first transparent conductive layer to form a pixel electrode; (2) depositing a first metal layer on the base plate and the pixel electrode and patterning the first metal layer to form source/drain terminals and a data line, wherein the data line comprises a data line terminal formed in a peripheral area of the base plate; (3) depositing a channel protection layer on the base plate, the pixel electrode, the source/drain terminals, and the data line and forming first vias in the channel protection layer at locations above and corresponding to the source/drain terminals; (4) depositing an oxide semiconductor layer on the channel protection layer and the source/drain terminals and patterning the oxide semiconductor layer to form an active layer such that the active layer is in contact engagement with the source/drain terminals through the first vias; (5) depositing a gate insulation layer on the channel protection layer and the active layer; (6) depositing a second metal layer on the gate insulation layer and patterning the second metal layer to form a gate terminal and a gate scan line, wherein the gate scan line comprises a scan line terminal formed in a peripheral area of the base plate; and forming a second via in the channel protection layer and the gate insulation layer at a location above and corresponding to the data line terminal; and (7) depositing a second transparent conductive layer on the gate insulation layer, the gate terminal, and the gate scan line and patterning the second transparent conductive layer to form a common electrode, a protective layer set on and covering the gate terminal and the gate scan line, and a conductive connection line set in contact engagement with the data line terminal through the second via.

2. The TFT substrate manufacturing method as claimed in claim 1, wherein the first transparent conductive layer and the second transparent conductive layer each have a thickness of 100-1000 ; and the first metal layer and the second metal layer each have a thickness of 1000-6000 .

3. The TFT substrate manufacturing method as claimed in claim 1, wherein the channel protection layer has a thickness of 1000-4000 ; the gate insulation layer has a thickness of 2000-4000 ; and the active layer has a thickness of 200-2000 .

4. The TFT substrate manufacturing method as claimed in claim 1, wherein the first transparent conductive layer and the second transparent conductive layer are each formed of a material comprising ITO or IZO; and the first metal layer and the second metal layer are each formed of a material comprising Cr, Mo, Al, or Cu.

5. The TFT substrate manufacturing method as claimed in claim 1, wherein the channel protection layer is formed of a material comprising silicon oxide; the gate insulation layer is formed of a material comprising silicon oxide, silicon nitride or a combination thereof; and the active layer is formed of a material comprising ZnO, InZnO, ZnSnO, GaInZnO, or ZrInZnO.

6. A thin-film transistor (TFT) substrate manufacturing method, comprising the following steps: (1) providing a base plate and depositing a buffer layer on the base plate; (2) depositing a first transparent conductive layer on the buffer layer and patterning the first transparent conductive layer to form a pixel electrode; (3) depositing a first metal layer on the buffer layer and the pixel electrode and patterning the first metal layer to form source/drain terminals and a data line, wherein the data line comprises a data line terminal formed in a peripheral area of the base plate; (4) depositing an oxide semiconductor layer on the buffer layer, the pixel electrode, the source/drain terminals, and the data line and patterning the oxide semiconductor layer to form an active layer such that the active layer is in contact engagement with the source/drain terminals; (5) depositing a gate insulation layer on the buffer layer, the pixel electrode, the source/drain terminals, the data line, and the active layer; (6) depositing a second metal layer on the gate insulation layer and patterning the second metal layer to form a gate terminal and a gate scan line, wherein the gate scan line comprises a scan line terminal formed in a peripheral area of the base plate; and forming a via in the gate insulation layer at a location above and corresponding to the data line terminal; and (7) depositing a second transparent conductive layer on the gate insulation layer, the gate terminal, and the gate scan line and patterning the second transparent conductive layer to form a common electrode, a protective layer set on and covering the gate terminal and the gate scan line, and a conductive connection line set in contact engagement with the data line terminal through the via.

7. The TFT substrate manufacturing method as claimed in claim 6, wherein the first transparent conductive layer and the second transparent conductive layer each have a thickness of 100-1000 ; and the first metal layer and the second metal layer each have a thickness of 1000-6000 .

8. The TFT substrate manufacturing method as claimed in claim 6, wherein the buffer layer has a thickness of 1000-2000 ; the gate insulation layer has a thickness of 2000-4000 ; and the active layer has a thickness of 200-2000 .

9. The TFT substrate manufacturing method as claimed in claim 6, wherein the first transparent conductive layer and the second transparent conductive layer are each formed of a material comprising ITO or IZO; and the first metal layer and the second metal layer are each formed of a material comprising Cr, Mo, Al, or Cu.

10. The TFT substrate manufacturing method as claimed in claim 6, wherein the buffer layer is formed of a material comprising silicon oxide; the gate insulation layer is formed of a material comprising silicon oxide, silicon nitride or a combination thereof; and the active layer is formed of a material comprising ZnO, InZnO, ZnSnO, GaInZnO, or ZrInZnO.

11. A thin-film transistor (TFT) substrate manufacturing method, comprising the following steps: (1) providing a base plate, depositing a first transparent conductive layer on the base plate and patterning the first transparent conductive layer to form a pixel electrode; (2) depositing a first metal layer on the base plate and the pixel electrode and patterning the first metal layer to form source/drain terminals and a data line, wherein the data line comprises a data line terminal formed in a peripheral area of the base plate; (3) depositing a channel protection layer on the base plate, the pixel electrode, the source/drain terminals, and the data line and forming first vias in the channel protection layer at locations above and corresponding to the source/drain terminals; (4) depositing an oxide semiconductor layer on the channel protection layer and the source/drain terminals and patterning the oxide semiconductor layer to form an active layer such that the active layer is in contact engagement with the source/drain terminals through the first vias; (5) depositing a gate insulation layer on the channel protection layer and the active layer; (6) depositing a second metal layer on the gate insulation layer and patterning the second metal layer to form a gate terminal and a gate scan line, wherein the gate scan line comprises a scan line terminal formed in a peripheral area of the base plate; and forming a second via in the channel protection layer and the gate insulation layer at a location above and corresponding to the data line terminal; and (7) depositing a second transparent conductive layer on the gate insulation layer, the gate terminal, and the gate scan line and patterning the second transparent conductive layer to form a common electrode, a protective layer set on and covering the gate terminal and the gate scan line, and a conductive connection line set in contact engagement with the data line terminal through the second via; wherein the first transparent conductive layer and the second transparent conductive layer each have a thickness of 100-1000 and the first metal layer and the second metal layer each have a thickness of 1000-6000 ; and wherein the channel protection layer has a thickness of 1000-4000 ; the gate insulation layer has a thickness of 2000-4000 ; and the active layer has a thickness of 200-2000 .

12. The TFT substrate manufacturing method as claimed in claim 11, wherein the first transparent conductive layer and the second transparent conductive layer are each formed of a material comprising ITO or IZO; and the first metal layer and the second metal layer are each formed of a material comprising Cr, Mo, Al, or Cu.

13. The TFT substrate manufacturing method as claimed in claim 11, wherein the channel protection layer is formed of a material comprising silicon oxide; the gate insulation layer is formed of a material comprising silicon oxide, silicon nitride or a combination thereof; and the active layer is formed of a material comprising ZnO, InZnO, ZnSnO, GaInZnO, or ZrInZnO.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The features and technical contents of the present invention will be better understood by referring to the following detailed description and drawings the present invention. However, the drawings are provided for the purpose of reference and illustration and are not intended to limit the scope of the present invention. In the drawing:

(2) FIG. 1 is a flow chart illustrating a TFT substrate manufacturing method according to the present invention

(3) FIG. 2 is a schematic top plan view illustrating step 1 of the TFT substrate manufacturing method according to the present invention;

(4) FIG. 3 is a schematic top plan view illustrating step 2 of the TFT substrate manufacturing method according to the present invention;

(5) FIG. 4 is a schematic top plan view illustrating step 3 of the TFT substrate manufacturing method according to the present invention;

(6) FIG. 5 is a schematic top plan view illustrating step 4 of the TFT substrate manufacturing method according to the present invention;

(7) FIG. 6 is a schematic top plan view illustrating step 5 of the TFT substrate manufacturing method according to the present invention;

(8) FIG. 7 is a schematic top plan view illustrating step 6 of the TFT substrate manufacturing method according to the present invention;

(9) FIG. 8 is a schematic top plan view illustrating step 7 of the TFT substrate manufacturing method according to the present invention;

(10) FIG. 9 is a flow chart illustrating another TFT substrate manufacturing method according to the present invention

(11) FIG. 10 is a schematic top plan view illustrating step 1 of said another TFT substrate manufacturing method according to the present invention;

(12) FIG. 11 is a schematic top plan view illustrating step 2 of said another TFT substrate manufacturing method according to the present invention;

(13) FIG. 12 is a schematic top plan view illustrating step 3 of the said another TFT substrate manufacturing method according to the present invention;

(14) FIG. 13 is a schematic top plan view illustrating step 4 of said another TFT substrate manufacturing method according to the present invention;

(15) FIG. 14 is a schematic top plan view illustrating step 5 of said another TFT substrate manufacturing method according to the present invention;

(16) FIG. 15 is a schematic top plan view illustrating step 6 of said another TFT substrate manufacturing method according to the present invention; and

(17) FIG. 16 is a schematic top plan view illustrating step 7 of said another TFT substrate manufacturing method according to the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

(18) To further expound the technical solution adopted in the present invention and the advantages thereof, a detailed description is given to a preferred embodiment of the present invention with reference to the attached drawings.

(19) Referring to FIG. 1, firstly, the present invention provides a thin-film transistor (TFT) substrate manufacturing method, which comprises the following steps:

(20) Step 1: as shown in FIG. 2, providing a base plate 1, depositing a first transparent conductive layer on the base plate 1 and patterning the first transparent conductive layer to form a pixel electrode 2.

(21) Specifically, the base plate 1 comprises a glass plate.

(22) Specifically, the first transparent conductive layer has a thickness of 100-1000 .

(23) Specifically, the first transparent conductive layer is formed of a material comprising ITO (indium tin oxide) or IZO (indium zinc oxide).

(24) Step 2: as shown in FIG. 3, depositing a first metal layer on the base plate 1 and the pixel electrode 2 and patterning the first metal layer to form source/drain terminals 3 and a data line 31, wherein the data line 31 comprises a data line terminal 312 formed in a peripheral area of the base plate 1.

(25) Specifically, the first metal layer has a thickness of 1000-6000 .

(26) Specifically, the first metal layer is formed of a material comprising Cr (chromium), Mo (molybdenum), Al (aluminum), or Cu (copper).

(27) Step 3: as shown in FIG. 4, depositing a channel protection layer 4 on the base plate 1, the pixel electrode 2, the source/drain terminals 3, and the data line 31 and forming first vias 41 in the channel protection layer 4 at locations above and corresponding to the source/drain terminals 3.

(28) Specifically, the channel protection layer 4 has a thickness of 1000-4000 .

(29) Specifically, the channel protection layer 4 is formed of a material comprising silicon oxide.

(30) Step 4: as shown in FIG. 5, depositing an oxide semiconductor layer on the channel protection layer 4 and the source/drain terminals 3 and patterning the oxide semiconductor layer to form an active layer 5 such that the active layer 5 is in contact engagement with the source/drain terminals 3 through the first vias 41. The present invention adopts a process that first forms the pixel electrode, the data line and the source/drain terminals on the base plate and then forms the channel protection layer and the oxide semiconductor layer, so that it is possible to avoid damages induced in the oxide semiconductor layer during etching operations applied in forming the pixel electrode and the source/drain terminals.

(31) Specifically, the active layer 5 has a thickness of 200-2000 .

(32) Specifically, the active layer 5 is formed of a material comprising ZnO, InZnO, ZnSnO, GaInZnO, or ZrInZnO.

(33) Step 5: as shown in FIG. 6, depositing a gate insulation layer 6 on the channel protection layer 4 and the active layer 5.

(34) Specifically, the gate insulation layer 6 has a thickness of 2000-4000 .

(35) Specifically, the gate insulation layer 6 is formed of a material comprising silicon oxide, silicon nitride or a combination thereof.

(36) Step 6: as shown in FIG. 7, depositing a second metal layer on the gate insulation layer 6 and patterning the second metal layer to form a gate terminal 7 and a gate scan line 71, wherein the gate scan line 71 comprises a scan line terminal 712 formed in a peripheral area of the base plate 1; and forming a second via 8 in the channel protection layer 4 and the gate insulation layer 6 at a location above and corresponding to the data line terminal 312.

(37) Specifically, the second metal layer has a thickness of 1000-6000 .

(38) Specifically, the second metal layer is formed of a material comprising Cr, Mo, Al, or Cu.

(39) Step 7: as shown in FIG. 8, depositing a second transparent conductive layer on the gate insulation layer 6, the gate terminal 7, and the gate scan line 71 and patterning the second transparent conductive layer to form a common electrode 9, a protective layer 91 set on and covering the gate terminal 7 and the gate scan line 71, and a conductive connection line 92 set in contact engagement with the data line terminal 312 through the second via 8. Through forming the protective layer that is set on and covers a surface of the gate terminal to protect the gate terminal against corrosion at the same time of forming the common electrode, it is possible to save the use of one insulation protective layer. Specifically, the conductive connection line 92 provides connection between data line 31 and an integrated circuit (IC) chip.

(40) Specifically, the second transparent conductive layer has a thickness of 100-1000 .

(41) Specifically, the second transparent conductive layer is formed of a material comprising ITO or IZO.

(42) Referring to FIG. 9, the present invention also provides another TFT substrate manufacturing method, which comprises the following steps:

(43) Step 1: as shown in FIG. 10, providing a base plate 1 and depositing a buffer layer 10 on the base plate 1. The buffer layer 10 helps prevent direct contact of the oxide semiconductor layer with the base plate 1, which might affects the characteristics of a TFT.

(44) Specifically, the base plate 1 comprises a glass plate.

(45) Specifically, the buffer layer 10 has a thickness of 1000-2000 .

(46) Specifically, the buffer layer 10 is formed of a material comprising silicon oxide.

(47) Step 2: as shown in FIG. 11, depositing a first transparent conductive layer on the buffer layer 10 and patterning the first transparent conductive layer to form a pixel electrode 2.

(48) Specifically, the first transparent conductive layer has a thickness of 100-1000 .

(49) Specifically, the first transparent conductive layer is formed of a material comprising ITO or IZO.

(50) Step 3: as shown in FIG. 12, depositing a first metal layer on the buffer layer 10 and the pixel electrode 2 and patterning the first metal layer to form source/drain terminals 3 and a data line 31, wherein the data line 31 comprises a data line terminal 312 formed in a peripheral area of the base plate 1.

(51) Specifically, the first metal layer has a thickness of 1000-6000 .

(52) Specifically, the first metal layer is formed of a material comprising Cr, Mo, Al, or Cu.

(53) Step 4: as shown in FIG. 13, depositing an oxide semiconductor layer on the buffer layer 10, the pixel electrode 2, the source/drain terminals 3, and the data line 31 and patterning the oxide semiconductor layer to form an active layer 5 such that the active layer 5 is in contact engagement with the source/drain terminals 3, whereby one etch stopper layer can be saved and damage induced in the oxide semiconductor layer by an etching operation applied to form the source/drain terminals can be avoided.

(54) Specifically, the active layer 5 has a thickness of 200-2000 .

(55) Specifically, the active layer 5 is formed of a material comprising ZnO, InZnO, ZnSnO, GaInZnO, or ZrInZnO.

(56) Step 5: as shown in FIG. 14 depositing a gate insulation layer 6 on the buffer layer 10, the pixel electrode 2, the source/drain terminals 3, the data line 31, and the active layer 5.

(57) Specifically, the gate insulation layer 6 has a thickness of 2000-4000 .

(58) Specifically, the gate insulation layer 6 is formed of a material comprising silicon oxide, silicon nitride or a combination thereof.

(59) Step 6: as shown in FIG. 15, depositing a second metal layer on the gate insulation layer 6 and patterning the second metal layer to form a gate terminal 7 and a gate scan line 71, wherein the gate scan line 71 comprises a scan line terminal 712 formed in a peripheral area of the base plate 1; and forming a third via 81 in the gate insulation layer 6 at a location above and corresponding to the data line terminal 312.

(60) Specifically, the second metal layer has a thickness of 1000-6000 .

(61) Specifically, the second metal layer is formed of a material comprising Cr, Mo, Al, or Cu.

(62) Step 7: as shown in FIG. 16, depositing a second transparent conductive layer on the gate insulation layer 6, the gate terminal 7, and the gate scan line 71 and patterning the second transparent conductive layer to form a common electrode 9, a protective layer 91 set on and covering the gate terminal 7 and the gate scan line 71, and a conductive connection line 92 set in contact engagement with the data line terminal 312 through the third via 81. Through forming the protective layer that is set on and covers a surface of the gate terminal to protect the gate terminal against corrosion at the same time of forming the common electrode, it is possible to save the use of one insulation protective layer. Specifically, the conductive connection line 92 provides connection between data line 31 and an integrated circuit (IC) chip.

(63) Specifically, the second transparent conductive layer has a thickness of 100-1000 .

(64) Specifically, the second transparent conductive layer is formed of a material comprising ITO or IZO.

(65) In summary, the present invention provides a TFT substrate manufacturing method, which first forms a pixel electrode, a data line, and source/drain terminals on the base plate and then forms a channel protection layer and an oxide semiconductor layer; or alternatively first forming a buffer layer on a base plate to prevent characteristics of a TFT from being affected by direct contact between an oxide semiconductor layer and the base plate, and then forming the oxide semiconductor layer directly after formation of source/drain terminals so as to save one etch stopper layer, thus preventing damages induced in the oxide semiconductor layer by an etching operation of the source/drain terminals; and further, through forming a protective layer that covers a surface of a gate terminal to protect the gate terminal from corrosion at the same time of forming a common electrode, formation of an insulation protective layer can be saved so as to greatly simplify the manufacturing process and improve reliability of a TFT substrate.

(66) Based on the description given above, those having ordinary skills of the art may easily contemplate various changes and modifications of the technical solution and technical ideas of the present invention and all these changes and modifications are considered within the protection scope of right for the present invention.