Radar based fill-level sensor
11573115 ยท 2023-02-07
Assignee
Inventors
Cpc classification
H01Q1/2283
ELECTRICITY
G01S13/88
PHYSICS
H01L2924/00014
ELECTRICITY
H01L2924/00014
ELECTRICITY
H01L21/4825
ELECTRICITY
H01P3/16
ELECTRICITY
H01Q1/225
ELECTRICITY
H01L2224/0603
ELECTRICITY
H01L2223/6627
ELECTRICITY
H01L2223/6677
ELECTRICITY
H01Q9/0407
ELECTRICITY
G01S7/027
PHYSICS
International classification
H01P3/16
ELECTRICITY
H01L21/48
ELECTRICITY
H01Q1/22
ELECTRICITY
Abstract
A radar based, fill-level sensor comprising at least one semiconductor element, including at least a semiconductor chip and a chip package, in which the at least one semiconductor chip is arranged, wherein the at least one semiconductor chip has at least one coupling element, which serves as a signal gate for electromagnetic waves, preferably in the millimeter wave region, characterized in that at least one first resonator structure is arranged on a surface portion of the chip package.
Claims
1. A method for manufacturing a radar based fill-level sensor, the radar based fill-level sensor comprising: at least one semiconductor element, including at least a semiconductor chip and a chip package, in which the at least one semiconductor chip is arranged, wherein the at least one semiconductor chip has at least one coupling element, which serves as a signal gate for electromagnetic waves, wherein at least one first resonator structure is arranged on a surface portion of the chip package and wherein the first resonator structure is embodied as a dielectric resonator structure, and the first resonator structure is arranged in such a way on the surface portion of the chip package that the chip package separates the resonator structure from the coupling element, the method comprising steps as follows: sending radiation through the semiconductor element for determining a position of the semiconductor chip relative to the chip package; partially removing the chip package until a surface portion of the chip package has at least one depression; producing the first resonator structure in the at least one depression, so that the separation between the at least one first resonator structure and the at least one coupling element of the semiconductor chip is lessened.
2. The method as claimed in claim 1, wherein: at least one second resonator structure is arranged between said semiconductor chip and said at least one first resonator structure.
3. The method as claimed claim 1, wherein: said depression extends in the direction of said at least one semiconductor chip.
4. The method as claimed in claim 1, wherein: said depression extends in the direction of said at least one second resonator structure.
5. The method as claimed in claim 1, wherein: said at least one semiconductor element is arranged on a printed circuit board; and a dielectric lens is secured on said printed circuit board in such a way that said at least one semiconductor element lies in the focal point of said dielectric lens.
6. The method as claimed in claim 1, wherein: said semiconductor element is arranged on a printed circuit board; and at least one hollow conductor is arranged on the printed circuit board transferring the electromagnetic waves produced by said semiconductor element.
7. The method as claimed in claim 6, further comprising: a dielectric waveguide arranged said the depression, so that electromagnetic waves out-coupled from said coupling element are led by means of a dielectric waveguide into the hollow conductor.
8. The method as claimed in claim 1, wherein: said producing of the first resonator structure in the at least one depression is performed by means of a 2D or 3D printing method or an MID method.
9. The method as claimed in claim 1, wherein: said sending of radiation through the semiconductor element is performed by means of x-rays.
10. The method as claimed in claim 1, wherein: said partial removing of the chip package is performed by means of milling or laser beam machining.
11. The method as claimed in claim 1, wherein: the first resonator structure comprises a rectangular metal platelet; and an edge length of the first resonator structure corresponds to a half wavelength or an integer multiple half wavelength of the electromagnetic waves.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
(1) The invention will now be explained in greater detail based on the appended drawing, the figures of which show as follows:
(2)
(3)
(4)
(5)
(6)
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(9)
DETAILED DISCUSSION IN CONJUNCTION WITH THE DRAWINGS
(10)
(11) The chip package 4 includes on the surface portion, on which the first resonator structure 6 is arranged, a depression 8 deepening toward the coupling element 5, so that the separation 9 between the first resonator structure 6 and the coupling element 5 is lessened at the position of the depression 8.
(12) The coupling element 5 on the semiconductor chip 3 is embodied as a short circuited, very wide, lambda/4 transformer. The radiation into free space occurs via a resonator structure 6, which is embodied as a patch or dielectric resonator structure.
(13) Furthermore, leads 15 of the chip package 4 are connected by means of bond wires 19 with bond pads of the semiconductor chip 3 for low frequency signals and power supply.
(14)
(15) This is an option supplemental to the embodiment of
(16) The method of the invention will now be explained in detail based on
(17) Compared to a conventional semiconductor element, the semiconductor element 2 differs only by containing coupler structures in the form of two coupling elements 5 as signal gates at millimeter wave frequencies. The semiconductor element 2 is first installed in a typical chip package, wherein the three steps illustrated in
(18) The steps of the invention are shown in
(19) The provided depressions 8 have in the method the following central functions:
(20) a. Producing a defined distance between the first resonator structure 6 and an associated coupling element 5 and therewith the correction of possible thickness fluctuations in the potting material.
(21) b. Mechanical orientation and securement of the resonator structures.
(22) c. High electrical coupling between the coupling elements 5 and the associated resonator structures 6 by thinning the layer of potting material, whose thickness in the region of the coupling elements 5 can be less than the loop heights of the bond wires 19.
(23) By the procedure of the invention using the dimensional relationships ascertained from an x-ray image, the horizontal tolerances of the position of the first resonator structures 6 to the coupling elements 5 can be individually minimized. In case the vertical position tolerances, in spite of the small thickness tolerances of the lead frame and the adhesive layer for the semiconductor mounting are still too large, they can likewise be individually compensated based on a second, vertical, x-ray image.
(24) The electrical checking of the semiconductor element 2 manufactured according to the method of the invention can be performed with a self-test integrated in the semiconductor chip 3. In such case, a power measurement detects whether the radiation at the first resonator structure 6 on the semiconductor chip 3 is properly functioning or that a malfunction is present at the first resonator structure 6.
(25)
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(27) For better evaluation of an x-ray image of the packaged semiconductor element, special marker structures in the vicinity of the coupling elements can be installed in the chip layout, marker structures which because of metal density or pattern show up with especially high contrast in an x-ray image.
(28)
(29) The hollow conductor 12 has a terminal structure 25, which enables a low loss transition via the dielectric waveguide 24 into the hollow conductor 12. The waveguide 24 provides supplementally a galvanic isolation between the radar front end and a metal antenna structure, a feature which in the case of radar device process measurements technology is frequently specified for reasons of Ex protection.