CLIP AND RELATED METHODS
20180197836 · 2018-07-12
Assignee
Inventors
Cpc classification
H01L23/49524
ELECTRICITY
H01L2224/83193
ELECTRICITY
H01L2224/83438
ELECTRICITY
H01L2924/00012
ELECTRICITY
H01L2224/27312
ELECTRICITY
H01L2224/291
ELECTRICITY
H01L2224/29294
ELECTRICITY
H01L2224/84438
ELECTRICITY
H01L2224/293
ELECTRICITY
H01L2224/83438
ELECTRICITY
H01L2924/13091
ELECTRICITY
H01L2224/27312
ELECTRICITY
H01L2924/00
ELECTRICITY
H01L2224/83101
ELECTRICITY
H01L2924/00
ELECTRICITY
H01L2224/83101
ELECTRICITY
H01L2224/29294
ELECTRICITY
H01L2224/293
ELECTRICITY
H01L2924/00014
ELECTRICITY
H01L2924/13091
ELECTRICITY
H01L2224/92246
ELECTRICITY
H01L2224/84438
ELECTRICITY
H01L2924/00014
ELECTRICITY
H01L2924/00012
ELECTRICITY
H01L2224/40139
ELECTRICITY
H01L2224/291
ELECTRICITY
International classification
H01L25/07
ELECTRICITY
Abstract
Implementations of a clip for a semiconductor package may include: an electrically conductive clip having a first end and a second end and a middle section between the first end and the second end. The first end may be configured to couple to a first die through a bonding material. The second end may be configured to couple to a second die through a bonding material. The middle section may be configured to couple to an emitter structure through a bonding material. The clip may include an integrally formed electrically conductive material and include an M-shape. A middle of the M-shape may be coupled to the emitter structure.
Claims
1. A method of making a semiconductor package, the method comprising: patterning and etching a substrate to form a first collector, a second collector, and an emitter; applying bonding material to the first collector, the second collector, and the emitter; coupling a first die to the first collector and a second die to the second collector; applying bonding material to the first die and to the second die; and simultaneously mechanically and electrically coupling the first collector, the second collector, and the emitter through bonding an integrally formed clip to the first die, to the second die, and to the emitter through the bonding material.
2. The method of claim 1, wherein the substrate comprises of at least one of copper, silicon, and any combination thereof.
3. The method of claim 1, wherein the bonding material is selected from the group consisting of a solder paste, a solder wire, a preform solder, a sintered Ag metal, a sintered Ag laminate, and any combination thereof.
4. The method of claim 1, wherein the clip comprises an electrically conductive material selected from the group consisting of copper, copper alloy, aluminum, aluminum alloy, steel, brass, nickel, tin, and any combination thereof.
5. The method of claim 1, wherein the first die is one of an insulated gate bipolar transistor (IGBT) and a rectifier.
6. The method of claim 1, wherein the second die is one of an IGBT and a rectifier. The method of claim 1, wherein the second end of the clip is coupled to a terminal.
8. The method of claim 1, wherein the emitter is comprised of silicon.
9. A method of making a semiconductor package, the method comprising: patterning and etching a substrate to form a first collector, a second collector, and an emitter therein where the emitter is located between the first collector and the second collector; applying bonding material to the first collector, the second collector, and the emitter; coupling a first die to the first collector and a second die to the second collector; applying bonding material to the first die and to the second die; and simultaneously mechanically and electrically coupling the first collector, the second collector, and the emitter through bonding an integrally formed clip to the first die, to the second die, and to the emitter through the bonding material.
10. The method of claim 9, wherein the substrate comprises of at least one of copper, silicon, and any combination thereof.
11. The method of claim 9, wherein the bonding material is selected from the group consisting of a solder paste, a solder wire, a preform solder, a sintered Ag metal, a sintered Ag laminate, and any combination thereof.
12. The method of claim 9, wherein the clip comprises an electrically conductive material selected from the group consisting of copper, copper alloy, aluminum, aluminum alloy, steel, brass, nickel, tin, and any combination thereof.
13. The method of claim 9, wherein the first die is one of an insulated gate bipolar transistor (IGBT) and a rectifier.
14. The method of claim 9, wherein the second die is one of an IGBT and a rectifier.
15. The method of claim 9, wherein the second end of the clip is coupled to a terminal.
16. The method of claim 9, wherein the emitter is comprised of silicon.
17. A method of making a semiconductor package, the method comprising: patterning and etching a substrate to form a first collector, a second collector, and an emitter therein where the emitter is located between the first collector and the second collector; applying bonding material to the first collector, the second collector, and the emitter; coupling a first die to the first collector and a second die to the second collector; applying bonding material to the first die and to the second die; and simultaneously mechanically and electrically coupling the first collector, the second collector, and the emitter through bonding an integrally formed clip comprising an M-shape to the first die, to the second die, and to the emitter through the bonding material.
18. The method of claim 17, wherein the substrate comprises of at least one of copper, silicon, and any combination thereof.
19. The method of claim 17, wherein the bonding material is selected from the group consisting of a solder paste, a solder wire, a preform solder, a sintered Ag metal, a sintered Ag laminate, and any combination thereof.
20. The method of claim 17, wherein the clip comprises an electrically conductive material selected from the group consisting of copper, copper alloy, aluminum, aluminum alloy, steel, brass, nickel, tin, and any combination thereof.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
[0025] Implementations will hereinafter be described in conjunction with the appended drawings, where like designations denote like elements, and:
[0026]
[0027]
[0028]
[0029]
DESCRIPTION
[0030] This disclosure, its aspects and implementations, are not limited to the specific components, assembly procedures or method elements disclosed herein. Many additional components, assembly procedures and/or method elements known in the art consistent with the intended clip for a semiconductor package will become apparent for use with particular implementations from this disclosure. Accordingly, for example, although particular implementations are disclosed, such implementations and implementing components may comprise any shape, size, style, type, model, version, measurement, concentration, material, quantity, method element, step, and/or the like as is known in the art for such a clip, and implementing components and methods, consistent with the intended operation and methods.
[0031]
[0032] Referring to
[0033] Referring to
[0034] Clip implementations disclosed herein may be made of any electrically conductive material capable of carrying current between each component of the semiconductor package and mechanically holding its shape. These may include, in various implementations, copper, copper alloy, aluminum, aluminum alloy, steel, brass, nickel, tin, or any combination of these materials. The clip may be in the shape of an M. This shape is achieved by having a convex curvature in a middle section of the clip in order to allow the middle section to make contact with a portion of the package between the first end and second end of the clip while still being a single integral piece. Clip implementations may be made by a variety of techniques, including, by non-limiting example, bending, casting, molding, and any other method for integrally forming a metal or other electrically conductive material.
[0035] Semiconductor packages that utilize clip implementations like those disclosed herein may be formed using various implementations of methods of manufacturing semiconductor packages. In such method implementations, the method includes patterning and etching a substrate to form a first collector, second collector, and an emitter where the emitter is located between the first collector and the second collector. This patterning and etching can be done using a wide variety of techniques including photolithography, wet etching, dry etching, electroplating, and the like. The substrate can include in whole or in part copper, silicon, or any combination thereof. The method also includes applying bonding material to the first collector, second collector, and the emitter and coupling a first die to the first collector and a second die to the second collector. The bonding material may be any disclosed in this document. The method also includes simultaneously mechanically and electrically coupling the first collector, the second collector, and the emitter through bonding the clip including the M-shape to the first die, the second die, and the emitter through the bonding material. As the clip contacts the die and the emitter, it simultaneously connects the components. It also allows the emitter to be located between the first collector and second collector due to the M-shape of the clip.
[0036] Various clip designs use multiple pieces to form a single clip to make contact with the semiconductor components. Examples of such designs may be found in U.S. Pat. No. 8,354,733 to Chang, Hsueh-Rong, entitled IGBT Power Semiconductor Package Having a Conductive Clip, issued Jan. 15, 2013; U.S. Pat. No. 6,475,834 to Embong et al. entitled Method of Manufacturing a Semiconductor Component and Semiconductor Component Thereof, issued Nov. 5, 2002; U.S. Pat. No. 8,138,600 to Muto et al. entitled Semiconductor Device and Method of Manufacturing the Same, issued Mar. 20, 2012; and U.S. Pat. No. 6,175,148 to Schwarzbauer, Herbert entitled Electrical Connection for a Power Semiconductor Component, issued Jan. 16, 2001; the disclosures of each of which are hereby incorporated entirely herein by reference.
[0037] In particular implementations, the clip may have more rigidity than a corresponding aluminum wire. This rigidity of the clip may aid in keeping the various components separated from each other and maintaining a low profile within the semiconductor package. Copper may be a good material for the construction of clip implementations because it has higher thermal and electrical conductivity than traditional materials used in semiconductor manufacturing. The clip made of copper can be thicker than the aluminum wire often used, permitting the clip to carry more current while maintaining a cooler temperature leading to less risk of hot spots and metal fatigue. In various implementations, the use of clip implementations like those disclosed herein in semiconductor packages eliminates the need for wire bonds because the clip is connected to the dies directly through the bonding material. This direct connection may also allow for a better flow of current within the device.
[0038] In places where the description above refers to particular implementations of clip for a semiconductor package and implementing components, sub-components, methods and sub-methods, it should be readily apparent that a number of modifications may be made without departing from the spirit thereof and that these implementations, implementing components, sub-components, methods and sub-methods may be applied to other clips.