SOI ACTIVE TRANSFER BOARD FOR THREE-DIMENSIONAL PACKAGING AND PREPARATION METHOD THEREOF

Abstract

Disclosed is an SOI active interposer for three-dimensional packaging and a fabrication method thereof. An SOI substrate is used as the substrate, and a CMOS inverter is formed on the top silicon of the SOI by using standard integrated circuit manufacturing processes, so that short channel effect and latch-up effect can be suppressed. A via hole structure is etched on the SOI substrate between the PMOS and NMOS transistors of the CMOS inverter, which on the one hand can be used as a conductive channel between the chips in a vertical direction, and on the other hand, can be used as an electrical isolation layer between the PMOS and NMOS transistors.

Claims

1. An SOI active interposer for three-dimensional packaging, comprising: an SOI substrate; a CMOS inverter, including a PMOS transistor (203) and an NMOS transistor (204) and formed on the SOI substrate; an SOI via hole formed between the PMOS transistor (203) and the NMOS transistor (204) and penetrating through the SOI substrate; a first insulating medium (205) covering the PMOS transistor (203) and the NMOS transistor (204); a second insulating medium (206) formed on the sidewall of the SOI via hole and the surface of the first insulating medium (205); and source, drain and gate via holes respectively formed on a source, drain and gate of the PMOS transistor (203) and the NMOS transistor (204), and penetrating through the first insulating medium (205) and the second insulating medium (206); wherein the sidewall of the SOI via hole is formed with a copper diffusion barrier layer (207) and a seed layer (208), the inside thereof is filled with copper (209), the top thereof is formed with an adhesion layer/seed layer laminated film (210) and a micro bump (211), and the bottom thereof is formed with an adhesion layer/seed layer laminated film (212) and a C4 bump (213); and the bottoms and the sidewalls of the source, drain and gate via holes are formed with a copper diffusion barrier layer (207) and a seed layer (208), the insides thereof are filled with copper (209), and the tops thereof are formed with an adhesion layer/seed layer laminated film (210) and micro bumps (211).

2. The SOI active interposer for three-dimensional packaging according to claim 1, wherein: the first insulating medium (205) and the second insulating medium (206) are silicon dioxide, silicon nitride, SiOCH or SiOCFH.

3. The SOI active interposer for three-dimensional packaging according to claim 1, wherein: the copper diffusion barrier layer (207) is at least one of TaN, TiN, ZrN, and MnSiO.sub.3.

4. The SOI active interposer for three-dimensional packaging according to claim 1, wherein: the seed layer (208) is at least one of Cu, Co and Ru.

5. A method for fabricating an SOI active interposer for three-dimensional packaging, comprising: providing an SOI substrate including a silicon substrate (200), a silicon dioxide (201) and a top silicon (202); producing a CMOS inverter on the surface of the SOI substrate, the CMOS inverter including a PMOS transistor (203) and an NMOS transistor (204); forming a first insulating medium (205) to cover the PMOS transistor (203) and the NMOS transistor (204); performing photolithography and etching on an area between the PMOS transistor (203) and the NMOS transistor (204) until a part of the silicon substrate (200) is etched away; forming a second insulating medium (206) on the resulting structure; removing the first insulating medium (205) and the second insulating medium (206) on the sources, drains and gates of the PMOS transistor (203) and the NMOS transistor (204) by photolithography and etching to form source, drain and gate via holes; forming a copper diffusion barrier layer (207), a seed layer (208) and copper (209), and removing the copper (209), the seed layer (208) and the copper diffusion barrier layer (207)above the second insulating medium (206) by a chemical mechanical polishing process; forming a top adhesion layer/seed layer laminated film (210) and micro bumps (211); and thinning the silicon substrate (200) on the back of the SOI substrate by a combined process of mechanical grinding and chemical mechanical polishing, so that the bottom of the copper (209) is exposed to form a bottom adhesion layer/seed layer laminated film (212) and a C4 bump (213).

6. The method for fabricating an SOI active interposer for three-dimensional packaging according to claim 5, wherein: the first insulating medium (205) and the second insulating medium (206) are silicon dioxide, silicon nitride, SiOCH or SiOCFH.

7. The method for fabricating an SOI active interposer for three-dimensional packaging according to claim 5, wherein: the copper diffusion barrier layer (207) is at least one of TaN, TiN, ZrN, and MnSiO.sub.3.

8. The method for fabricating an SOI active interposer for three-dimensional packaging according to claim 5, wherein: the seed layer (208) is at least one of Cu, Co and Ru.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0013] FIG. 1 is a flow chart of a method for fabricating an SOI active interposer for three-dimensional packaging.

[0014] FIGS. 2-13 are schematic structural diagrams of the steps of the method for fabricating SOI active interposer for three-dimensional packaging.

DETAILED DESCRIPTION OF THE INVENTION

[0015] In order to make the objectives, technical solutions and advantages of the present invention clearer, the following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention. The described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative work shall fall within the protection scope of the present invention.

[0016] In the description of the present invention, it should be noted that the orientation or positional relationship indicated by the terms “upper”, “lower”, “vertical”, “horizontal”, and the like is based on the orientation or positional relationship shown in the drawings, and is only for convenient description of the present invention and simplify the description, rather than indicating or implying that the device or element referred to must have a specific orientation, or must be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation of the present invention. In addition, the terms “first” and “second” are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance.

[0017] In addition, many specific details of the present invention are described below, such as the structure, materials, dimensions, processing method and technology of the device, in order to understand the present invention more clearly. However, as those skilled in the art can understand, the present invention may not be implemented according to these specific details. Unless specifically indicated in the following, each part of the device may be made of materials known to those skilled in the art, or materials with similar functions developed in the future.

[0018] The technical solution of the present invention will be further described below in combination with FIGS. 1 to 13 and embodiments.

[0019] FIG. 1 is a flow chart of a method for fabricating an SOI (Silicon-On-Insulator) active interposer for three-dimensional packaging, and FIGS. 2-13 show schematic structural diagrams of the steps of the method for fabricating an SOI active interposer for three-dimensional packaging. As shown in FIG. 1, the specific fabrication steps are:

[0020] Step S1: producing a CMOS inverter on the surface of an SOI substrate, An SOI substrate with a p-type doped single crystal silicon substrate 200 and p-type doped top single crystal silicon 202 is chosen as a substrate, and the obtained structure is shown in FIG. 2. The material between the silicon substrate 200 and the top silicon 202 is silicon dioxide 201, and the thickness of the top silicon 202 ranges from 100 to 400 nm. Next, a CMOS inverter is fabricated on the surface of the top silicon 202 by using standard integrated circuit processes such as photolithography, etching, ion implantation, and sputtering, and a structure as shown in FIG. 3 is obtained. In FIG. 3, a device structure circled by dotted lines is a PMOS transistor 203 and an NMOS transistor 204, and the TOMOS transistor 203 and the NMOS transistor 204 form a CMOS inverter. In this embodiment, the silicon substrate and the top silicon are both p-type doped, but the present invention is not limited to this, and an n-type doping may also be used. Using SOI as the substrate for fabricating the active interposer, and fabricating the CMOS inverter on the top silicon of the SOI, the short channel effect and the latch-up effect can be suppressed.

[0021] Step S2: etching the SOI substrate to form an SOI via hole structure. First, a chemical vapor deposition process is used to grow a layer of silicon dioxide as the first insulating medium 205 on the surface of the above-mentioned structure, the first insulating medium 205 completely covering the CMOS inverter. The resulting structure is shown in FIG. 4. Then, photoresist is spin-coated, and a pattern of the SOI via hole structure is defined through exposure and development processes. Next, a deep reactive ion etching (DRIE) process is used to etch an SOI region between the PMOS and NMOS transistors until a part of the silicon substrate 200 is etched away. Finally, the photoresist is dissolved in a solvent or is ached, and the resulting structure is shown in FIG. 5. On the one hand, the via hole structure can be used as a conductive channel to connect chips in a vertical direction, and on the other hand, it can be used as an electrical isolation layer between the PMOS transistor and the NMOS transistor, acting like a short trench isolation (STI). The plasma used to etch the silicon dioxide 202 and the first insulating medium 205 can be CF.sub.4, CHF.sub.3, CF.sub.4/CHF.sub.3, CF.sub.4/O.sub.2 or CHF.sub.3/O.sub.2, and for the top silicon 203 and the silicon substrate 200, at least one of CF.sub.4 and SF.sub.6 can be chosen.

[0022] Step S3: forming via hole structures on a source, drain and gate of the CMOS inverter. First, a chemical vapor deposition process is used to grow a layer of silicon dioxide as the second insulating medium 206 on the surface of the above structure, with a thickness ranging from 200 to 500 nm, so that the surface of the SOI via hole will be covered with a layer of the second insulating medium 206. This second insulating medium can be used as an isolation layer between the PMOS transistor and the NMOS transistor, and also as an isolation layer of the CMOS inverter and the silicon substrate from metal interconnection lines. The resulting structure is shown in FIG. 6. Then, photoresist is spin-coated, and patterns of the via holes of the source, drain and gate of the CMOS inverter are defined through exposure and development processes. Then, the first insulating medium 205 and the second insulating medium 206 are etched by a DRIE process until the source, drain and gate are exposed. The resulting structure is shown in FIG. 7. In the present invention, silicon dioxide is used as the insulating medium, but the present invention is not limited to this, and silicon dioxide, silicon nitride, low dielectric constant materials (such as SiOCH, SiOCFH), etc. can be selected.

[0023] Step S4: depositing a copper diffusion barrier layer, a seed layer, and electroplating copper. First, a physical vapor deposition method is used to sequentially grow a TaN film and a Cu film inside the SOI via hole and the source, drain and gate via holes as the copper diffusion barrier layer 207 and the seed layer 208 respectively. The resulting structure is shown in FIG. 8. Then, the Cu film is used as a seed layer, and the copper material 209 is electroplated on it by an electroplating process. The copper material 209 completely fills the SOI via hole and the source, drain and gate via holes. The resulting structure is shown in FIG. 9. Finally, a chemical mechanical polishing process is used to remove the copper material 209, the Cu seed layer 208 and the TaN copper diffusion barrier layer 207 above the second insulating medium 206. The resulting structure is shown in FIG. 10. In this embodiment, TaN is used as the copper diffusion barrier layer and Cu is used as the seed layer, but the present invention is not limited to this. At least one of TaN, TiN, ZrN, and MnSiO.sub.3 can be selected as the copper diffusion barrier layer, and at least one of Cu, Co and Ru can be selected as the seed layer. For the growth modes of the copper diffusion barrier layer and the seed layer, at least one of physical vapor deposition, chemical vapor deposition, and atomic layer deposition can be selected.

[0024] Step S5: performing metal wiring and making contact bumps. First, a laminated film 210 composed of a Ti film and a Cu film is grown on the surface of the above-mentioned structure by physical vapor deposition. The Ti film and the Cu film serve as adhesion layer and seed layer, respectively. Then, the surface of the adhesion layer/seed layer laminated film 210 is electroplated with a laminated metal composed of Cu material and Sn material as the micro bumps 211 by electroplating. Then, photolithography and etching processes are used to remove unnecessary adhesion layer/seed layer laminated film 210 to ensure that there is no conduction between adjacent micro bumps. The resulting structure is shown in FIG. 11. Thereafter, a combined process of mechanical grinding and chemical mechanical polishing is used to thin the silicon substrate on the back of the SOI substrate so that the bottom of the copper material 209 is exposed. The resulting structure is shown in FIG. 12. Finally, the adhesion layer/seed layer laminated film 212 and a C4 bump 213 are sequentially fabricated on the bottom of the copper material 209 by using the same process as the micro bumps 211, and the resulting structure is shown in FIGS. 13.

[0025] As shown in FIG. 13, the SOI active interposer for three-dimensional packaging of the present invention comprises the 501 substrate; the CMOS inverter, including the PMOS transistor 203 and the NMOS transistor 204 and formed on the SOI substrate; the SOI via hole, formed between the PMOS transistor 203 and the NMOS transistor 204 and penetrating through the SOI substrate; the first insulating medium 205, covering the PMOS transistor 203 and the NMOS transistor 204; the second insulating medium 206, formed on the sidewall of the SOI via hole and the surface of the first insulating medium 205; source, drain and gate via holes, formed on the sources, drains and gates of the PMOS transistor 203 and the CMOS transistor 204, respectively, and penetrating through the first insulating medium 205 and the second insulating medium 206. The sidewall of the SOI via hole is formed with the copper diffusion barrier layer 207 and the seed layer 208, the inside thereof is filled with copper 209, the top thereof is formed with an adhesion layer/seed layer laminated film 210 and micro bumps 211, and the bottom thereof is formed with an adhesion layer/seed layer laminated film 212 and a C4 bump 213, The bottoms and sidewalk of the source, drain and gate via holes are formed with a copper diffusion barrier layer 207 and a seed layer 208, the insides thereof are filled with copper 209, and the tops thereof are formed with an adhesion layer/seed layer laminated film 210 and micro bumps 211.

[0026] Preferably, the first insulating medium and the second insulating medium are silicon dioxide, silicon nitride, SiOCH, SiOCFH, or the like. Preferably, the copper diffusion harder layer is at least one of TaN, TiN, ZrN, and MnSiO.sub.3. Preferably, the seed layer is at least one of Cu, Co, and Ru.

[0027] The above are only specific embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions easily occurred to those skilled in the art within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention.